diff options
author | Jacob Bramley <jacob.bramley@arm.com> | 2018-06-08 17:14:58 +0100 |
---|---|---|
committer | Jacob Bramley <jacob.bramley@arm.com> | 2018-06-14 17:05:47 +0100 |
commit | c41760bef82c9431a06a970d48103fb67ac55cd0 (patch) | |
tree | 14ea3ee1cc20a43b4d521d2d215a43f385cd0b55 /src | |
parent | 1ea48ea5783f53409531258758848b670c311e69 (diff) |
Fix some erroneous uses of instr->Mask(0).
Change-Id: I7b12ee533713677bdac3f5801a95b86517c81529
Diffstat (limited to 'src')
-rw-r--r-- | src/aarch64/constants-aarch64.h | 2 | ||||
-rw-r--r-- | src/aarch64/decoder-aarch64.cc | 3 | ||||
-rw-r--r-- | src/aarch64/instructions-aarch64.h | 5 | ||||
-rw-r--r-- | src/aarch64/simulator-aarch64.cc | 35 |
4 files changed, 29 insertions, 16 deletions
diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h index 6b8454fc..02422ef2 100644 --- a/src/aarch64/constants-aarch64.h +++ b/src/aarch64/constants-aarch64.h @@ -414,6 +414,8 @@ enum DataCacheOp { enum GenericInstrField { SixtyFourBits = 0x80000000, ThirtyTwoBits = 0x00000000, + + FPTypeMask = 0x00C00000, FP16 = 0x00C00000, FP32 = 0x00000000, FP64 = 0x00400000 diff --git a/src/aarch64/decoder-aarch64.cc b/src/aarch64/decoder-aarch64.cc index 1a981864..77900441 100644 --- a/src/aarch64/decoder-aarch64.cc +++ b/src/aarch64/decoder-aarch64.cc @@ -895,7 +895,8 @@ void Decoder::DecodeNEONScalarDataProcessing(const Instruction* instr) { #define DEFINE_VISITOR_CALLERS(A) \ void Decoder::Visit##A(const Instruction* instr) { \ - VIXL_ASSERT(instr->Mask(A##FMask) == A##Fixed); \ + VIXL_ASSERT(((A##FMask == 0) && (A##Fixed == 0)) || \ + (instr->Mask(A##FMask) == A##Fixed)); \ std::list<DecoderVisitor*>::iterator it; \ for (it = visitors_.begin(); it != visitors_.end(); it++) { \ (*it)->Visit##A(instr); \ diff --git a/src/aarch64/instructions-aarch64.h b/src/aarch64/instructions-aarch64.h index 66ddf624..39c21a11 100644 --- a/src/aarch64/instructions-aarch64.h +++ b/src/aarch64/instructions-aarch64.h @@ -194,7 +194,10 @@ class Instruction { return ExtractSignedBits(msb, lsb); } - Instr Mask(uint32_t mask) const { return GetInstructionBits() & mask; } + Instr Mask(uint32_t mask) const { + VIXL_ASSERT(mask != 0); + return GetInstructionBits() & mask; + } #define DEFINE_GETTER(Name, HighBit, LowBit, Func) \ int32_t Get##Name() const { return this->Func(HighBit, LowBit); } \ diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index f1a57d97..787ee2ec 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -2829,13 +2829,18 @@ void Simulator::VisitFPDataProcessing1Source(const Instruction* instr) { FPRounding fpcr_rounding = static_cast<FPRounding>(ReadFpcr().GetRMode()); VectorFormat vform; - if (instr->Mask(FP64) == FP64) { - vform = kFormatD; - } else if (instr->Mask(FP32) == FP32) { - vform = kFormatS; - } else { - VIXL_ASSERT(instr->Mask(FP16) == FP16); - vform = kFormatH; + switch (instr->Mask(FPTypeMask)) { + default: + VIXL_UNREACHABLE_OR_FALLTHROUGH(); + case FP64: + vform = kFormatD; + break; + case FP32: + vform = kFormatS; + break; + case FP16: + vform = kFormatH; + break; } SimVRegister& rd = ReadVRegister(instr->GetRd()); SimVRegister& rn = ReadVRegister(instr->GetRn()); @@ -2934,13 +2939,15 @@ void Simulator::VisitFPDataProcessing2Source(const Instruction* instr) { AssertSupportedFPCR(); VectorFormat vform; - if (instr->Mask(FP64) == FP64) { - vform = kFormatD; - } else if (instr->Mask(FP32) == FP32) { - vform = kFormatS; - } else { - VIXL_ASSERT(instr->Mask(FP16) == FP16); - vform = kFormatH; + switch (instr->Mask(FPTypeMask)) { + default: + VIXL_UNREACHABLE_OR_FALLTHROUGH(); + case FP64: + vform = kFormatD; + break; + case FP32: + vform = kFormatS; + break; } SimVRegister& rd = ReadVRegister(instr->GetRd()); SimVRegister& rn = ReadVRegister(instr->GetRn()); |