diff options
author | Vincent Belliard <vincent.belliard@arm.com> | 2016-12-13 14:38:55 -0800 |
---|---|---|
committer | Vincent Belliard <vincent.belliard@arm.com> | 2016-12-20 07:20:11 -0800 |
commit | a576eb92e2a877984e6e5c1e409e23c49c8b96a1 (patch) | |
tree | b0f07b8a2db5079222ea075b7dda06a27784e381 | |
parent | 34ecc5b8b9af49df5727cfc357db1fddc674cb44 (diff) |
Add more identities.
Change-Id: I52ff78a7b101de88146ead71b555a17541f9b863
-rw-r--r-- | src/aarch32/macro-assembler-aarch32.h | 22 | ||||
-rw-r--r-- | test/aarch32/test-disasm-a32.cc | 18 |
2 files changed, 40 insertions, 0 deletions
diff --git a/src/aarch32/macro-assembler-aarch32.h b/src/aarch32/macro-assembler-aarch32.h index eeed17c5..c695c5aa 100644 --- a/src/aarch32/macro-assembler-aarch32.h +++ b/src/aarch32/macro-assembler-aarch32.h @@ -1246,6 +1246,10 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(OutsideITBlock()); MacroEmissionCheckScope guard(this); + if (rd.Is(rn) && operand.IsPlainRegister() && + rd.Is(operand.GetBaseRegister())) { + return; + } if (cond.Is(al) && operand.IsImmediate()) { uint32_t immediate = operand.GetImmediate(); if (immediate == 0) { @@ -1279,6 +1283,10 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { Ands(cond, rd, rn, operand); break; case DontCare: + if (operand.IsPlainRegister() && rd.Is(rn) && + rd.Is(operand.GetBaseRegister())) { + return; + } bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && rn.Is(rd) && operand.IsPlainRegister() && operand.GetBaseRegister().IsLow(); @@ -2559,6 +2567,9 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(OutsideITBlock()); MacroEmissionCheckScope guard(this); + if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) { + return; + } bool can_use_it = // MOV<c>{<q>} <Rd>, #<imm8> ; T1 (operand.IsImmediate() && rd.IsLow() && @@ -2596,6 +2607,9 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { Movs(cond, rd, operand); break; case DontCare: + if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) { + return; + } bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && ((operand.IsImmediateShiftedRegister() && rd.IsLow() && @@ -2852,6 +2866,10 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(OutsideITBlock()); MacroEmissionCheckScope guard(this); + if (rd.Is(rn) && operand.IsPlainRegister() && + rd.Is(operand.GetBaseRegister())) { + return; + } if (cond.Is(al) && operand.IsImmediate()) { uint32_t immediate = operand.GetImmediate(); if ((immediate == 0) && rd.Is(rn)) { @@ -2885,6 +2903,10 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { Orrs(cond, rd, rn, operand); break; case DontCare: + if (operand.IsPlainRegister() && rd.Is(rn) && + rd.Is(operand.GetBaseRegister())) { + return; + } bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && rn.Is(rd) && operand.IsPlainRegister() && operand.GetBaseRegister().IsLow(); diff --git a/test/aarch32/test-disasm-a32.cc b/test/aarch32/test-disasm-a32.cc index 03fffc6b..08737b8b 100644 --- a/test/aarch32/test-disasm-a32.cc +++ b/test/aarch32/test-disasm-a32.cc @@ -3825,5 +3825,23 @@ TEST(macro_assembler_T32_16bit) { #undef CHECK_T32_16 #undef CHECK_T32_16_IT_BLOCK + +TEST(nop_code) { + SETUP(); + + COMPARE_BOTH(Nop(), "nop\n"); + + COMPARE_BOTH(And(r0, r0, r0), ""); + COMPARE_BOTH(And(DontCare, r0, r0, r0), ""); + + COMPARE_BOTH(Mov(r0, r0), ""); + COMPARE_BOTH(Mov(DontCare, r0, r0), ""); + + COMPARE_BOTH(Orr(r0, r0, r0), ""); + COMPARE_BOTH(Orr(DontCare, r0, r0, r0), ""); + + CLEANUP(); +} + } // namespace aarch32 } // namespace vixl |