gator: Version 5.215.21

Signed-off-by: Drew Richardson <drew.richardson@arm.com>

1 files changed, 47 insertions, 70 deletions

diff --git a/daemon/events-Cortex-A53.xml b/daemon/events-Cortex-A53.xml
index 5ba1790..acdfe4e 100644
--- a/daemon/events-Cortex-A53.xml
+++ b/daemon/events-Cortex-A53.xml
@@ -1,87 +1,64 @@
   <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
   <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
     <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
+    <event event="0x00" title="Software" name="Increment" description="Software increment. The register is incremented only on writes to the Software Increment Register."/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
     <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
     <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
     <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
+    <event event="0x06" title="Instruction" name="Data Read" description="Instruction architecturally executed, condition check pass - load"/>
+    <event event="0x07" title="Instruction" name="Memory write" description="Instruction architecturally executed, condition check pass - store"/>
     <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
+    <event event="0x09" title="Exception" name="Taken" description="Exception taken"/>
+    <event event="0x0a" title="Exception" name="Return" description="Exception return"/>
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Change to Context ID retired"/>
+    <event event="0x0c" title="Branch" name="PC change" description="Instruction architecturally executed, condition check pass, software change of the PC"/>
+    <event event="0x0d" title="Branch" name="Immediate" description="Instruction architecturally executed, immediate branch"/>
+    <event event="0x0e" title="Procedure" name="Return" description="Instruction architecturally executed, condition code check pass, procedure return"/>
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Instruction architecturally executed, condition check pass, unaligned load or store"/>
+    <event event="0x10" title="Branch" name="Mispredicted" description="Mispredicted or not predicted branch speculatively executed"/>
     <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
     <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
-    <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
-    <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
-    <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
-    <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
-    <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
+    <event event="0x14" title="Cache" name="L1 inst access" description="L1 Instruction cache access"/>
+    <event event="0x15" title="Cache" name="L1 data write" description="L1 Data cache Write-Back"/>
+    <event event="0x16" title="Cache" name="L2 data access" description="L2 Data cache access"/>
+    <event event="0x17" title="Cache" name="L2 data refill" description="L2 Data cache refill"/>
+    <event event="0x18" title="Cache" name="L2 data write" description="L2 Data cache Write-Back"/>
     <event event="0x19" title="Bus" name="Access" description="Bus access"/>
-    <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
-    <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
-    <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
-    <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
-    <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
-    <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
-    <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
-    <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
-    <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
-    <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
-    <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
-    <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
-    <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
-    <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
-    <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
-    <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
-    <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
-    <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
-    <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
-    <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
-    <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
+    <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
+    <event event="0x1d" title="Bus" name="Cycle" description="Bus cycle"/>
+    <event event="0x1e" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
     <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
     <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
-    <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
-    <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
-    <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
-    <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
-    <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
-    <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
-    <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
-    <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
-    <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
-    <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
-    <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
-    <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
-    <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
-    <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
-    <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
-    <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
-    <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
-    <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
-    <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
-    <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
-    <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
-    <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
-    <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
-    <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
-    <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
-    <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
-    <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
-    <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
-    <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
-    <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
+    <event event="0x7a" title="Branch" name="Indirect" description="Branch speculatively executed - Indirect branch"/>
     <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
     <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
-    <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
-    <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
-    <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
-    <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
-    <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
-    <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
-    <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
-    <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
-    <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
+    <event event="0xc0" title="Memory" name="External request" description="External memory request"/>
+    <event event="0xc1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
+    <event event="0xc2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
+    <event event="0xc3" title="Cache" name="Throttle" description="Instruction Cache Throttle occurred"/>
+    <event event="0xc4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
+    <event event="0xc5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
+    <event event="0xc6" title="Pre-decode" name="error" description="Pre-decode error"/>
+    <event event="0xc7" title="Memory" name="Write stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
+    <event event="0xc8" title="Memory" name="Snoop" description="SCU Snooped data from another CPU for this CPU"/>
+    <event event="0xc9" title="Branch" name="Taken" description="Conditional branch executed"/>
+    <!--
+    <event event="0xca" title="Branch" name="Mispredicted a" description="Indirect branch mispredicted"/>
+    <event event="0xcb" title="Branch" name="Mispredicted b" description="Indirect branch mispredicted because of address miscompare"/>
+    <event event="0xcc" title="Branch" name="Mispredicted c" description="Conditional branch mispredicted"/>
+    -->
+    <event event="0xd0" title="Cache" name="L1 inst error" description="L1 Instruction Cache (data or tag) memory error"/>
+    <event event="0xd1" title="Cache" name="L1 data error" description="L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"/>
+    <event event="0xd2" title="Cache" name="TLB error" description="TLB memory error"/>
+    <event event="0xe0" title="Stall" name="DPU IP empty" description="Attributable Performance Impact Event. Counts every cycle that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error."/>
+    <event event="0xe1" title="Stall" name="Cache miss" description="Attributable Performance Impact Event. Counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed."/>
+    <event event="0xe2" title="Stall" name="TLB miss" description="Attributable Performance Impact Event. Counts every cycle the DPU IQ is empty and there is an instruction micro-TLB miss being processed."/>
+    <event event="0xe3" title="Stall" name="Pre-decode error" description="Attributable Performance Impact Event. Counts every cycle the DPU IQ is empty and there is a pre-decode error being processed."/>
+    <event event="0xe4" title="Stall" name="Interlock other" description="Attributable Performance Impact Event. Counts every cycle there is an interlock that is not because of an Advanced SIMD or Floating-point instruction, and not because of a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles because of a stall in Wr, typically awaiting load data, are excluded."/>
+    <event event="0xe5" title="Stall" name="Interlock address" description="Attributable Performance Impact Event. Counts every cycle there is an interlock that is because of a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles because of a stall in Wr, typically awaiting load data, are excluded."/>
+    <event event="0xe6" title="Stall" name="Interlock SIMD/FPU" description="Attributable Performance Impact Event. Counts every cycle there is an interlock that is because of an Advanced SIMD or Floating-point instruction. Stall cycles because of a stall in the Wr stage, typically awaiting load data, are excluded."/>
+    <event event="0xe7" title="Stall" name="Load miss" description="Attributable Performance Impact Event. Counts every cycle there is a stall in the Wr stage because of a load miss"/>
+    <event event="0xe8" title="Stall" name="Store" description="Attributable Performance Impact Event. Counts every cycle there is a stall in the Wr stage because of a store."/>
   </category>