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path: root/daemon/events-Cortex-A53.xml
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  <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
  <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
    <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
    <event event="0x00" title="Software" name="Increment" description="Software increment. The register is incremented only on writes to the Software Increment Register."/>
    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
    <event event="0x06" title="Instruction" name="Data Read" description="Instruction architecturally executed, condition check pass - load"/>
    <event event="0x07" title="Instruction" name="Memory write" description="Instruction architecturally executed, condition check pass - store"/>
    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
    <event event="0x09" title="Exception" name="Taken" description="Exception taken"/>
    <event event="0x0a" title="Exception" name="Return" description="Exception return"/>
    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Change to Context ID retired"/>
    <event event="0x0c" title="Branch" name="PC change" description="Instruction architecturally executed, condition check pass, software change of the PC"/>
    <event event="0x0d" title="Branch" name="Immediate" description="Instruction architecturally executed, immediate branch"/>
    <event event="0x0e" title="Procedure" name="Return" description="Instruction architecturally executed, condition code check pass, procedure return"/>
    <event event="0x0f" title="Memory" name="Unaligned access" description="Instruction architecturally executed, condition check pass, unaligned load or store"/>
    <event event="0x10" title="Branch" name="Mispredicted" description="Mispredicted or not predicted branch speculatively executed"/>
    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
    <event event="0x14" title="Cache" name="L1 inst access" description="L1 Instruction cache access"/>
    <event event="0x15" title="Cache" name="L1 data write" description="L1 Data cache Write-Back"/>
    <event event="0x16" title="Cache" name="L2 data access" description="L2 Data cache access"/>
    <event event="0x17" title="Cache" name="L2 data refill" description="L2 Data cache refill"/>
    <event event="0x18" title="Cache" name="L2 data write" description="L2 Data cache Write-Back"/>
    <event event="0x19" title="Bus" name="Access" description="Bus access"/>
    <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
    <event event="0x1d" title="Bus" name="Cycle" description="Bus cycle"/>
    <event event="0x1e" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
    <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
    <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
    <event event="0x7a" title="Branch" name="Indirect" description="Branch speculatively executed - Indirect branch"/>
    <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
    <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
    <event event="0xc0" title="Memory" name="External request" description="External memory request"/>
    <event event="0xc1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
    <event event="0xc2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
    <event event="0xc3" title="Cache" name="Throttle" description="Instruction Cache Throttle occurred"/>
    <event event="0xc4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
    <event event="0xc5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
    <event event="0xc6" title="Pre-decode" name="error" description="Pre-decode error"/>
    <event event="0xc7" title="Memory" name="Write stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
    <event event="0xc8" title="Memory" name="Snoop" description="SCU Snooped data from another CPU for this CPU"/>
    <event event="0xc9" title="Branch" name="Taken" description="Conditional branch executed"/>
    <!--
    <event event="0xca" title="Branch" name="Mispredicted a" description="Indirect branch mispredicted"/>
    <event event="0xcb" title="Branch" name="Mispredicted b" description="Indirect branch mispredicted because of address miscompare"/>
    <event event="0xcc" title="Branch" name="Mispredicted c" description="Conditional branch mispredicted"/>
    -->
    <event event="0xd0" title="Cache" name="L1 inst error" description="L1 Instruction Cache (data or tag) memory error"/>
    <event event="0xd1" title="Cache" name="L1 data error" description="L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"/>
    <event event="0xd2" title="Cache" name="TLB error" description="TLB memory error"/>
    <event event="0xe0" title="Stall" name="DPU IP empty" description="Attributable Performance Impact Event. Counts every cycle that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error."/>
    <event event="0xe1" title="Stall" name="Cache miss" description="Attributable Performance Impact Event. Counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed."/>
    <event event="0xe2" title="Stall" name="TLB miss" description="Attributable Performance Impact Event. Counts every cycle the DPU IQ is empty and there is an instruction micro-TLB miss being processed."/>
    <event event="0xe3" title="Stall" name="Pre-decode error" description="Attributable Performance Impact Event. Counts every cycle the DPU IQ is empty and there is a pre-decode error being processed."/>
    <event event="0xe4" title="Stall" name="Interlock other" description="Attributable Performance Impact Event. Counts every cycle there is an interlock that is not because of an Advanced SIMD or Floating-point instruction, and not because of a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles because of a stall in Wr, typically awaiting load data, are excluded."/>
    <event event="0xe5" title="Stall" name="Interlock address" description="Attributable Performance Impact Event. Counts every cycle there is an interlock that is because of a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles because of a stall in Wr, typically awaiting load data, are excluded."/>
    <event event="0xe6" title="Stall" name="Interlock SIMD/FPU" description="Attributable Performance Impact Event. Counts every cycle there is an interlock that is because of an Advanced SIMD or Floating-point instruction. Stall cycles because of a stall in the Wr stage, typically awaiting load data, are excluded."/>
    <event event="0xe7" title="Stall" name="Load miss" description="Attributable Performance Impact Event. Counts every cycle there is a stall in the Wr stage because of a load miss"/>
    <event event="0xe8" title="Stall" name="Store" description="Attributable Performance Impact Event. Counts every cycle there is a stall in the Wr stage because of a store."/>
  </category>