diff options
| author | Marcin Wojtas <mw@semihalf.com> | 2017-04-13 15:28:38 +0200 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-07-07 15:26:14 +0100 |
| commit | 114e00612c93bc9166405bb0a30663e273aa6fab (patch) | |
| tree | c6589a6bef318b058faf3457186fffc0b01e00a4 | |
| parent | 4b9d75a22be7d1d1d1e7f774090f24e68cdfa379 (diff) | |
Platform/Marvell: ComPhyLib: Rename KR to SFI
The actual SerDes type present by the HW is SFI, whose
suppport is added in the following patches. KR mode is
its subset of the SFI and it will be enabled in future.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
| -rwxr-xr-x | Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 6 | ||||
| -rw-r--r-- | Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 2 | ||||
| -rw-r--r-- | Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c index 6214bed..cee7519 100755 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -50,7 +50,7 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; * PIPE selector include USB and PCIe options.
* PHY selector include the Ethernet and SATA options, every Ethernet option
* has different options, for example: serdes Lane2 have option Eth_port_0
- * that include (SGMII0, RXAUI0, KR)
+ * that include (SGMII0, RXAUI0, SFI)
*/
COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
/* Lane 0 */
@@ -59,13 +59,13 @@ COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA0, 0x4}}},
/* Lane 2 */
{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
- {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4}}},
+ {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}},
/* Lane 3 */
{8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII1, 0x2},
{PHY_TYPE_SATA1, 0x4}}},
/* Lane 4 */
{7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAUI0, 0x2},
- {PHY_TYPE_KR, 0x2}, {PHY_TYPE_SGMII1, 0x1}}},
+ {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}},
/* Lane 5 */
{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAUI1, 0x2},
{PHY_TYPE_SATA1, 0x4}}},
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c index 9efefb2..88680fc 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -39,7 +39,7 @@ CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3",
L"QSGMII", L"USB3_HOST0", L"USB3_HOST1",
L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2",
- L"XAUI3", L"RXAUI0", L"RXAUI1", L"KR"};
+ L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"};
CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps",
L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps",
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h index 945f266..24839b2 100644 --- a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -109,7 +109,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PHY_TYPE_XAUI3 20
#define PHY_TYPE_RXAUI0 21
#define PHY_TYPE_RXAUI1 22
-#define PHY_TYPE_KR 23
+#define PHY_TYPE_SFI 23
#define PHY_TYPE_MAX 24
#define PHY_TYPE_INVALID 0xff
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