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bellard7d132992003-03-06 23:23:54 +00001/*
陳韋任e965fc32012-02-06 14:02:55 +08002 * emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard7d132992003-03-06 23:23:54 +000018 */
bellarde4533c72003-06-15 19:51:39 +000019#include "config.h"
Blue Swirlcea5f9a2011-05-15 16:03:25 +000020#include "cpu.h"
bellard956034d2003-04-29 20:40:53 +000021#include "disas.h"
bellard7cb69ca2008-05-10 10:55:51 +000022#include "tcg.h"
Jan Kiszka1d93f0f2010-06-25 16:56:49 +020023#include "qemu-barrier.h"
Anthony Liguoric7f0f3b2012-03-28 15:42:02 +020024#include "qtest.h"
bellard7d132992003-03-06 23:23:54 +000025
bellard36bdbe52003-11-19 22:12:02 +000026int tb_invalidated_flag;
27
Juan Quintelaf0667e62009-07-27 16:13:05 +020028//#define CONFIG_DEBUG_EXEC
bellard7d132992003-03-06 23:23:54 +000029
Andreas Färber9349b4f2012-03-14 01:38:32 +010030bool qemu_cpu_has_work(CPUArchState *env)
aliguori6a4955a2009-04-24 18:03:20 +000031{
32 return cpu_has_work(env);
33}
34
Andreas Färber9349b4f2012-03-14 01:38:32 +010035void cpu_loop_exit(CPUArchState *env)
bellarde4533c72003-06-15 19:51:39 +000036{
Blue Swirlcea5f9a2011-05-15 16:03:25 +000037 env->current_tb = NULL;
38 longjmp(env->jmp_env, 1);
bellarde4533c72003-06-15 19:51:39 +000039}
thsbfed01f2007-06-03 17:44:37 +000040
bellardfbf9eeb2004-04-25 21:21:33 +000041/* exit the current TB from a signal handler. The host registers are
42 restored in a state compatible with the CPU emulator
43 */
Blue Swirl9eff14f2011-05-21 08:42:35 +000044#if defined(CONFIG_SOFTMMU)
Andreas Färber9349b4f2012-03-14 01:38:32 +010045void cpu_resume_from_signal(CPUArchState *env, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000046{
Blue Swirl9eff14f2011-05-21 08:42:35 +000047 /* XXX: restore cpu registers saved in host registers */
48
49 env->exception_index = -1;
50 longjmp(env->jmp_env, 1);
51}
Blue Swirl9eff14f2011-05-21 08:42:35 +000052#endif
bellardfbf9eeb2004-04-25 21:21:33 +000053
pbrook2e70f6e2008-06-29 01:03:05 +000054/* Execute the code without caching the generated code. An interpreter
55 could be used if available. */
Andreas Färber9349b4f2012-03-14 01:38:32 +010056static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000057 TranslationBlock *orig_tb)
pbrook2e70f6e2008-06-29 01:03:05 +000058{
Stefan Weil69784ea2012-03-16 23:50:54 +010059 tcg_target_ulong next_tb;
pbrook2e70f6e2008-06-29 01:03:05 +000060 TranslationBlock *tb;
61
62 /* Should never happen.
63 We only end up here when an existing TB is too long. */
64 if (max_cycles > CF_COUNT_MASK)
65 max_cycles = CF_COUNT_MASK;
66
67 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
68 max_cycles);
69 env->current_tb = tb;
70 /* execute the generated code */
Blue Swirlcea5f9a2011-05-15 16:03:25 +000071 next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr);
Paolo Bonzini1c3569f2010-01-15 09:42:07 +010072 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +000073
74 if ((next_tb & 3) == 2) {
75 /* Restore PC. This may happen if async event occurs before
76 the TB starts executing. */
aliguori622ed362008-11-18 19:36:03 +000077 cpu_pc_from_tb(env, tb);
pbrook2e70f6e2008-06-29 01:03:05 +000078 }
79 tb_phys_invalidate(tb, -1);
80 tb_free(tb);
81}
82
Andreas Färber9349b4f2012-03-14 01:38:32 +010083static TranslationBlock *tb_find_slow(CPUArchState *env,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000084 target_ulong pc,
bellard8a40a182005-11-20 10:35:40 +000085 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +000086 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +000087{
88 TranslationBlock *tb, **ptb1;
bellard8a40a182005-11-20 10:35:40 +000089 unsigned int h;
Blue Swirl337fc752011-09-04 11:06:22 +000090 tb_page_addr_t phys_pc, phys_page1;
Paul Brook41c1b1c2010-03-12 16:54:58 +000091 target_ulong virt_page2;
ths3b46e622007-09-17 08:09:54 +000092
bellard8a40a182005-11-20 10:35:40 +000093 tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +000094
bellard8a40a182005-11-20 10:35:40 +000095 /* find translated block using physical mappings */
Paul Brook41c1b1c2010-03-12 16:54:58 +000096 phys_pc = get_page_addr_code(env, pc);
bellard8a40a182005-11-20 10:35:40 +000097 phys_page1 = phys_pc & TARGET_PAGE_MASK;
bellard8a40a182005-11-20 10:35:40 +000098 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000104 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000105 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000106 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
Blue Swirl337fc752011-09-04 11:06:22 +0000110 tb_page_addr_t phys_page2;
111
ths5fafdf22007-09-16 21:08:06 +0000112 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000113 TARGET_PAGE_SIZE;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000114 phys_page2 = get_page_addr_code(env, virt_page2);
bellard8a40a182005-11-20 10:35:40 +0000115 if (tb->page_addr[1] == phys_page2)
116 goto found;
117 } else {
118 goto found;
119 }
120 }
121 ptb1 = &tb->phys_hash_next;
122 }
123 not_found:
pbrook2e70f6e2008-06-29 01:03:05 +0000124 /* if no translated code available, then translate it now */
125 tb = tb_gen_code(env, pc, cs_base, flags, 0);
ths3b46e622007-09-17 08:09:54 +0000126
bellard8a40a182005-11-20 10:35:40 +0000127 found:
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300128 /* Move the last found TB to the head of the list */
129 if (likely(*ptb1)) {
130 *ptb1 = tb->phys_hash_next;
131 tb->phys_hash_next = tb_phys_hash[h];
132 tb_phys_hash[h] = tb;
133 }
bellard8a40a182005-11-20 10:35:40 +0000134 /* we add the TB in the virtual pc hash table */
135 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
bellard8a40a182005-11-20 10:35:40 +0000136 return tb;
137}
138
Andreas Färber9349b4f2012-03-14 01:38:32 +0100139static inline TranslationBlock *tb_find_fast(CPUArchState *env)
bellard8a40a182005-11-20 10:35:40 +0000140{
141 TranslationBlock *tb;
142 target_ulong cs_base, pc;
aliguori6b917542008-11-18 19:46:41 +0000143 int flags;
bellard8a40a182005-11-20 10:35:40 +0000144
145 /* we record a subset of the CPU state. It will
146 always be the same before a given translated block
147 is executed. */
aliguori6b917542008-11-18 19:46:41 +0000148 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bellardbce61842008-02-01 22:18:51 +0000149 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
ths551bd272008-07-03 17:57:36 +0000150 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
151 tb->flags != flags)) {
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000152 tb = tb_find_slow(env, pc, cs_base, flags);
bellard8a40a182005-11-20 10:35:40 +0000153 }
154 return tb;
155}
156
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100157static CPUDebugExcpHandler *debug_excp_handler;
158
159CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
160{
161 CPUDebugExcpHandler *old_handler = debug_excp_handler;
162
163 debug_excp_handler = handler;
164 return old_handler;
165}
166
Andreas Färber9349b4f2012-03-14 01:38:32 +0100167static void cpu_handle_debug_exception(CPUArchState *env)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100168{
169 CPUWatchpoint *wp;
170
171 if (!env->watchpoint_hit) {
172 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
173 wp->flags &= ~BP_WATCHPOINT_HIT;
174 }
175 }
176 if (debug_excp_handler) {
177 debug_excp_handler(env);
178 }
179}
180
bellard7d132992003-03-06 23:23:54 +0000181/* main execution loop */
182
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300183volatile sig_atomic_t exit_request;
184
Andreas Färber9349b4f2012-03-14 01:38:32 +0100185int cpu_exec(CPUArchState *env)
bellard7d132992003-03-06 23:23:54 +0000186{
Andreas Färberc356a1b2012-05-04 19:39:23 +0200187#ifdef TARGET_PPC
188 CPUState *cpu = ENV_GET_CPU(env);
189#endif
bellard8a40a182005-11-20 10:35:40 +0000190 int ret, interrupt_request;
bellard8a40a182005-11-20 10:35:40 +0000191 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000192 uint8_t *tc_ptr;
Stefan Weil69784ea2012-03-16 23:50:54 +0100193 tcg_target_ulong next_tb;
bellard8c6939c2003-06-09 15:28:00 +0000194
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000195 if (env->halted) {
196 if (!cpu_has_work(env)) {
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100197 return EXCP_HALTED;
198 }
199
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000200 env->halted = 0;
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100201 }
bellard5a1e3cf2005-11-23 21:02:53 +0000202
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000203 cpu_single_env = env;
bellarde4533c72003-06-15 19:51:39 +0000204
Jan Kiszkac629a4b2010-06-25 16:56:52 +0200205 if (unlikely(exit_request)) {
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300206 env->exit_request = 1;
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300207 }
208
thsecb644f2007-06-03 18:45:53 +0000209#if defined(TARGET_I386)
Jan Kiszka6792a572011-02-07 12:19:18 +0100210 /* put eflags in CPU temporary format */
211 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
212 DF = 1 - (2 * ((env->eflags >> 10) & 1));
213 CC_OP = CC_OP_EFLAGS;
214 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard93ac68b2003-09-30 20:57:29 +0000215#elif defined(TARGET_SPARC)
pbrooke6e59062006-10-22 00:18:54 +0000216#elif defined(TARGET_M68K)
217 env->cc_op = CC_OP_FLAGS;
218 env->cc_dest = env->sr & 0xf;
219 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000220#elif defined(TARGET_ALPHA)
221#elif defined(TARGET_ARM)
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800222#elif defined(TARGET_UNICORE32)
thsecb644f2007-06-03 18:45:53 +0000223#elif defined(TARGET_PPC)
Elie Richa4e85f822011-07-22 05:58:39 +0000224 env->reserve_addr = -1;
Michael Walle81ea0e12011-02-17 23:45:02 +0100225#elif defined(TARGET_LM32)
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200226#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000227#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000228#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000229#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100230#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400231#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000232 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000233#else
234#error unsupported target CPU
235#endif
bellard3fb2ded2003-06-24 13:22:59 +0000236 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000237
bellard7d132992003-03-06 23:23:54 +0000238 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000239 for(;;) {
240 if (setjmp(env->jmp_env) == 0) {
241 /* if an exception is pending, we execute it here */
242 if (env->exception_index >= 0) {
243 if (env->exception_index >= EXCP_INTERRUPT) {
244 /* exit request from the cpu execution loop */
245 ret = env->exception_index;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100246 if (ret == EXCP_DEBUG) {
247 cpu_handle_debug_exception(env);
248 }
bellard3fb2ded2003-06-24 13:22:59 +0000249 break;
aurel3272d239e2009-01-14 19:40:27 +0000250 } else {
251#if defined(CONFIG_USER_ONLY)
bellard3fb2ded2003-06-24 13:22:59 +0000252 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000253 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000254 loop */
bellard83479e72003-06-25 16:12:37 +0000255#if defined(TARGET_I386)
Blue Swirle694d4e2011-05-16 19:38:48 +0000256 do_interrupt(env);
bellard83479e72003-06-25 16:12:37 +0000257#endif
bellard3fb2ded2003-06-24 13:22:59 +0000258 ret = env->exception_index;
259 break;
aurel3272d239e2009-01-14 19:40:27 +0000260#else
Blue Swirle694d4e2011-05-16 19:38:48 +0000261 do_interrupt(env);
Paolo Bonzini301d2902010-01-15 09:41:01 +0100262 env->exception_index = -1;
aurel3272d239e2009-01-14 19:40:27 +0000263#endif
bellard3fb2ded2003-06-24 13:22:59 +0000264 }
ths5fafdf22007-09-16 21:08:06 +0000265 }
bellard9df217a2005-02-10 22:05:51 +0000266
blueswir1b5fc09a2008-05-04 06:38:18 +0000267 next_tb = 0; /* force lookup of first TB */
bellard3fb2ded2003-06-24 13:22:59 +0000268 for(;;) {
bellard68a79312003-06-30 13:12:32 +0000269 interrupt_request = env->interrupt_request;
malce1638bd2008-11-06 18:54:46 +0000270 if (unlikely(interrupt_request)) {
271 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
272 /* Mask out external interrupts for this step. */
Richard Henderson3125f762011-05-04 13:34:25 -0700273 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
malce1638bd2008-11-06 18:54:46 +0000274 }
pbrook6658ffb2007-03-16 23:58:11 +0000275 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
276 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
277 env->exception_index = EXCP_DEBUG;
Blue Swirl1162c042011-05-14 12:52:35 +0000278 cpu_loop_exit(env);
pbrook6658ffb2007-03-16 23:58:11 +0000279 }
balroga90b7312007-05-01 01:28:01 +0000280#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200281 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800282 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
balroga90b7312007-05-01 01:28:01 +0000283 if (interrupt_request & CPU_INTERRUPT_HALT) {
284 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
285 env->halted = 1;
286 env->exception_index = EXCP_HLT;
Blue Swirl1162c042011-05-14 12:52:35 +0000287 cpu_loop_exit(env);
balroga90b7312007-05-01 01:28:01 +0000288 }
289#endif
bellard68a79312003-06-30 13:12:32 +0000290#if defined(TARGET_I386)
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300291 if (interrupt_request & CPU_INTERRUPT_INIT) {
Blue Swirle694d4e2011-05-16 19:38:48 +0000292 svm_check_intercept(env, SVM_EXIT_INIT);
Andreas Färber232fc232012-05-05 01:14:41 +0200293 do_cpu_init(x86_env_get_cpu(env));
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300294 env->exception_index = EXCP_HALTED;
Blue Swirl1162c042011-05-14 12:52:35 +0000295 cpu_loop_exit(env);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300296 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
Andreas Färber232fc232012-05-05 01:14:41 +0200297 do_cpu_sipi(x86_env_get_cpu(env));
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300298 } else if (env->hflags2 & HF2_GIF_MASK) {
bellarddb620f42008-06-04 17:02:19 +0000299 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
300 !(env->hflags & HF_SMM_MASK)) {
Blue Swirle694d4e2011-05-16 19:38:48 +0000301 svm_check_intercept(env, SVM_EXIT_SMI);
bellarddb620f42008-06-04 17:02:19 +0000302 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
Blue Swirle694d4e2011-05-16 19:38:48 +0000303 do_smm_enter(env);
bellarddb620f42008-06-04 17:02:19 +0000304 next_tb = 0;
305 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
306 !(env->hflags2 & HF2_NMI_MASK)) {
307 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
308 env->hflags2 |= HF2_NMI_MASK;
Blue Swirle694d4e2011-05-16 19:38:48 +0000309 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
bellarddb620f42008-06-04 17:02:19 +0000310 next_tb = 0;
陳韋任e965fc32012-02-06 14:02:55 +0800311 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
Huang Ying79c4f6b2009-06-23 10:05:14 +0800312 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
Blue Swirle694d4e2011-05-16 19:38:48 +0000313 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
Huang Ying79c4f6b2009-06-23 10:05:14 +0800314 next_tb = 0;
bellarddb620f42008-06-04 17:02:19 +0000315 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
316 (((env->hflags2 & HF2_VINTR_MASK) &&
317 (env->hflags2 & HF2_HIF_MASK)) ||
318 (!(env->hflags2 & HF2_VINTR_MASK) &&
319 (env->eflags & IF_MASK &&
320 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
321 int intno;
Blue Swirle694d4e2011-05-16 19:38:48 +0000322 svm_check_intercept(env, SVM_EXIT_INTR);
bellarddb620f42008-06-04 17:02:19 +0000323 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
324 intno = cpu_get_pic_interrupt(env);
aliguori93fcfe32009-01-15 22:34:14 +0000325 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
Blue Swirle694d4e2011-05-16 19:38:48 +0000326 do_interrupt_x86_hardirq(env, intno, 1);
bellarddb620f42008-06-04 17:02:19 +0000327 /* ensure that no TB jump will be modified as
328 the program flow was changed */
329 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000330#if !defined(CONFIG_USER_ONLY)
bellarddb620f42008-06-04 17:02:19 +0000331 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
332 (env->eflags & IF_MASK) &&
333 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
334 int intno;
335 /* FIXME: this should respect TPR */
Blue Swirle694d4e2011-05-16 19:38:48 +0000336 svm_check_intercept(env, SVM_EXIT_VINTR);
bellarddb620f42008-06-04 17:02:19 +0000337 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
aliguori93fcfe32009-01-15 22:34:14 +0000338 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
Blue Swirle694d4e2011-05-16 19:38:48 +0000339 do_interrupt_x86_hardirq(env, intno, 1);
aurel32d40c54d2008-12-13 12:33:02 +0000340 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
bellarddb620f42008-06-04 17:02:19 +0000341 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000342#endif
bellarddb620f42008-06-04 17:02:19 +0000343 }
bellard68a79312003-06-30 13:12:32 +0000344 }
bellardce097762004-01-04 23:53:18 +0000345#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000346 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
Andreas Färberc356a1b2012-05-04 19:39:23 +0200347 cpu_reset(cpu);
bellard9fddaa02004-05-21 12:59:32 +0000348 }
j_mayer47103572007-03-30 09:38:04 +0000349 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000350 ppc_hw_interrupt(env);
351 if (env->pending_interrupts == 0)
352 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
blueswir1b5fc09a2008-05-04 06:38:18 +0000353 next_tb = 0;
bellardce097762004-01-04 23:53:18 +0000354 }
Michael Walle81ea0e12011-02-17 23:45:02 +0100355#elif defined(TARGET_LM32)
356 if ((interrupt_request & CPU_INTERRUPT_HARD)
357 && (env->ie & IE_IE)) {
358 env->exception_index = EXCP_IRQ;
359 do_interrupt(env);
360 next_tb = 0;
361 }
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200362#elif defined(TARGET_MICROBLAZE)
363 if ((interrupt_request & CPU_INTERRUPT_HARD)
364 && (env->sregs[SR_MSR] & MSR_IE)
365 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
366 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
367 env->exception_index = EXCP_IRQ;
368 do_interrupt(env);
369 next_tb = 0;
370 }
bellard6af0bf92005-07-02 14:58:51 +0000371#elif defined(TARGET_MIPS)
372 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100373 cpu_mips_hw_interrupts_pending(env)) {
bellard6af0bf92005-07-02 14:58:51 +0000374 /* Raise it */
375 env->exception_index = EXCP_EXT_INTERRUPT;
376 env->error_code = 0;
377 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000378 next_tb = 0;
bellard6af0bf92005-07-02 14:58:51 +0000379 }
bellarde95c8d52004-09-30 22:22:08 +0000380#elif defined(TARGET_SPARC)
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300381 if (interrupt_request & CPU_INTERRUPT_HARD) {
382 if (cpu_interrupts_enabled(env) &&
383 env->interrupt_index > 0) {
384 int pil = env->interrupt_index & 0xf;
385 int type = env->interrupt_index & 0xf0;
bellard66321a12005-04-06 20:47:48 +0000386
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300387 if (((type == TT_EXTINT) &&
388 cpu_pil_allowed(env, pil)) ||
389 type != TT_EXTINT) {
390 env->exception_index = env->interrupt_index;
391 do_interrupt(env);
392 next_tb = 0;
393 }
394 }
陳韋任e965fc32012-02-06 14:02:55 +0800395 }
bellardb5ff1b32005-11-26 10:38:39 +0000396#elif defined(TARGET_ARM)
397 if (interrupt_request & CPU_INTERRUPT_FIQ
398 && !(env->uncached_cpsr & CPSR_F)) {
399 env->exception_index = EXCP_FIQ;
400 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000401 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000402 }
pbrook9ee6e8b2007-11-11 00:04:49 +0000403 /* ARMv7-M interrupt return works by loading a magic value
404 into the PC. On real hardware the load causes the
405 return to occur. The qemu implementation performs the
406 jump normally, then does the exception return when the
407 CPU tries to execute code at the magic address.
408 This will cause the magic PC value to be pushed to
Stefan Weila1c72732011-04-28 17:20:38 +0200409 the stack if an interrupt occurred at the wrong time.
pbrook9ee6e8b2007-11-11 00:04:49 +0000410 We avoid this by disabling interrupts when
411 pc contains a magic address. */
bellardb5ff1b32005-11-26 10:38:39 +0000412 if (interrupt_request & CPU_INTERRUPT_HARD
pbrook9ee6e8b2007-11-11 00:04:49 +0000413 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
414 || !(env->uncached_cpsr & CPSR_I))) {
bellardb5ff1b32005-11-26 10:38:39 +0000415 env->exception_index = EXCP_IRQ;
416 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000417 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000418 }
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800419#elif defined(TARGET_UNICORE32)
420 if (interrupt_request & CPU_INTERRUPT_HARD
421 && !(env->uncached_asr & ASR_I)) {
422 do_interrupt(env);
423 next_tb = 0;
424 }
bellardfdf9b3e2006-04-27 21:07:38 +0000425#elif defined(TARGET_SH4)
thse96e2042007-12-02 06:18:24 +0000426 if (interrupt_request & CPU_INTERRUPT_HARD) {
427 do_interrupt(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000428 next_tb = 0;
thse96e2042007-12-02 06:18:24 +0000429 }
j_mayereddf68a2007-04-05 07:22:49 +0000430#elif defined(TARGET_ALPHA)
Richard Henderson6a80e082011-04-18 15:09:09 -0700431 {
432 int idx = -1;
433 /* ??? This hard-codes the OSF/1 interrupt levels. */
陳韋任e965fc32012-02-06 14:02:55 +0800434 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
Richard Henderson6a80e082011-04-18 15:09:09 -0700435 case 0 ... 3:
436 if (interrupt_request & CPU_INTERRUPT_HARD) {
437 idx = EXCP_DEV_INTERRUPT;
438 }
439 /* FALLTHRU */
440 case 4:
441 if (interrupt_request & CPU_INTERRUPT_TIMER) {
442 idx = EXCP_CLK_INTERRUPT;
443 }
444 /* FALLTHRU */
445 case 5:
446 if (interrupt_request & CPU_INTERRUPT_SMP) {
447 idx = EXCP_SMP_INTERRUPT;
448 }
449 /* FALLTHRU */
450 case 6:
451 if (interrupt_request & CPU_INTERRUPT_MCHK) {
452 idx = EXCP_MCHK;
453 }
454 }
455 if (idx >= 0) {
456 env->exception_index = idx;
457 env->error_code = 0;
458 do_interrupt(env);
459 next_tb = 0;
460 }
j_mayereddf68a2007-04-05 07:22:49 +0000461 }
thsf1ccf902007-10-08 13:16:14 +0000462#elif defined(TARGET_CRIS)
edgar_igl1b1a38b2008-06-09 23:18:06 +0000463 if (interrupt_request & CPU_INTERRUPT_HARD
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100464 && (env->pregs[PR_CCS] & I_FLAG)
465 && !env->locked_irq) {
edgar_igl1b1a38b2008-06-09 23:18:06 +0000466 env->exception_index = EXCP_IRQ;
467 do_interrupt(env);
468 next_tb = 0;
469 }
Lars Persson82193142012-06-14 16:23:55 +0200470 if (interrupt_request & CPU_INTERRUPT_NMI) {
471 unsigned int m_flag_archval;
472 if (env->pregs[PR_VR] < 32) {
473 m_flag_archval = M_FLAG_V10;
474 } else {
475 m_flag_archval = M_FLAG_V32;
476 }
477 if ((env->pregs[PR_CCS] & m_flag_archval)) {
478 env->exception_index = EXCP_NMI;
479 do_interrupt(env);
480 next_tb = 0;
481 }
thsf1ccf902007-10-08 13:16:14 +0000482 }
pbrook06338792007-05-23 19:58:11 +0000483#elif defined(TARGET_M68K)
484 if (interrupt_request & CPU_INTERRUPT_HARD
485 && ((env->sr & SR_I) >> SR_I_SHIFT)
486 < env->pending_level) {
487 /* Real hardware gets the interrupt vector via an
488 IACK cycle at this point. Current emulated
489 hardware doesn't rely on this, so we
490 provide/save the vector when the interrupt is
491 first signalled. */
492 env->exception_index = env->pending_vector;
Blue Swirl3c688822011-05-21 07:55:24 +0000493 do_interrupt_m68k_hardirq(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000494 next_tb = 0;
pbrook06338792007-05-23 19:58:11 +0000495 }
Alexander Graf3110e292011-04-15 17:32:48 +0200496#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
497 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
498 (env->psw.mask & PSW_MASK_EXT)) {
499 do_interrupt(env);
500 next_tb = 0;
501 }
Max Filippov40643d72011-09-06 03:55:41 +0400502#elif defined(TARGET_XTENSA)
503 if (interrupt_request & CPU_INTERRUPT_HARD) {
504 env->exception_index = EXC_IRQ;
505 do_interrupt(env);
506 next_tb = 0;
507 }
bellard68a79312003-06-30 13:12:32 +0000508#endif
Stefan Weilff2712b2011-04-28 17:20:35 +0200509 /* Don't use the cached interrupt_request value,
bellard9d050952006-05-22 22:03:52 +0000510 do_interrupt may have updated the EXITTB flag. */
bellardb5ff1b32005-11-26 10:38:39 +0000511 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bellardbf3e8bf2004-02-16 21:58:54 +0000512 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
513 /* ensure that no TB jump will be modified as
514 the program flow was changed */
blueswir1b5fc09a2008-05-04 06:38:18 +0000515 next_tb = 0;
bellardbf3e8bf2004-02-16 21:58:54 +0000516 }
aurel32be214e62009-03-06 21:48:00 +0000517 }
518 if (unlikely(env->exit_request)) {
519 env->exit_request = 0;
520 env->exception_index = EXCP_INTERRUPT;
Blue Swirl1162c042011-05-14 12:52:35 +0000521 cpu_loop_exit(env);
bellard3fb2ded2003-06-24 13:22:59 +0000522 }
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700523#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
aliguori8fec2b82009-01-15 22:36:53 +0000524 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
bellard3fb2ded2003-06-24 13:22:59 +0000525 /* restore flags in standard format */
thsecb644f2007-06-03 18:45:53 +0000526#if defined(TARGET_I386)
Blue Swirle694d4e2011-05-16 19:38:48 +0000527 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
528 | (DF & DF_MASK);
aliguori93fcfe32009-01-15 22:34:14 +0000529 log_cpu_state(env, X86_DUMP_CCOP);
bellard3fb2ded2003-06-24 13:22:59 +0000530 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
pbrooke6e59062006-10-22 00:18:54 +0000531#elif defined(TARGET_M68K)
532 cpu_m68k_flush_flags(env, env->cc_op);
533 env->cc_op = CC_OP_FLAGS;
534 env->sr = (env->sr & 0xffe0)
535 | env->cc_dest | (env->cc_x << 4);
aliguori93fcfe32009-01-15 22:34:14 +0000536 log_cpu_state(env, 0);
bellarde4533c72003-06-15 19:51:39 +0000537#else
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700538 log_cpu_state(env, 0);
bellarde4533c72003-06-15 19:51:39 +0000539#endif
bellard3fb2ded2003-06-24 13:22:59 +0000540 }
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700541#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
pbrookd5975362008-06-07 20:50:51 +0000542 spin_lock(&tb_lock);
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000543 tb = tb_find_fast(env);
pbrookd5975362008-06-07 20:50:51 +0000544 /* Note: we do it here to avoid a gcc bug on Mac OS X when
545 doing it in tb_find_slow */
546 if (tb_invalidated_flag) {
547 /* as some TB could have been invalidated because
548 of memory exceptions while generating the code, we
549 must recompute the hash index here */
550 next_tb = 0;
pbrook2e70f6e2008-06-29 01:03:05 +0000551 tb_invalidated_flag = 0;
pbrookd5975362008-06-07 20:50:51 +0000552 }
Juan Quintelaf0667e62009-07-27 16:13:05 +0200553#ifdef CONFIG_DEBUG_EXEC
Stefan Weil3ba19252012-04-12 15:44:24 +0200554 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
555 tb->tc_ptr, tb->pc,
aliguori93fcfe32009-01-15 22:34:14 +0000556 lookup_symbol(tb->pc));
bellard9d27abd2003-05-10 13:13:54 +0000557#endif
bellard8a40a182005-11-20 10:35:40 +0000558 /* see if we can patch the calling TB. When the TB
559 spans two pages, we cannot safely do a direct
560 jump. */
Paolo Bonzini040f2fb2010-01-15 08:56:36 +0100561 if (next_tb != 0 && tb->page_addr[1] == -1) {
blueswir1b5fc09a2008-05-04 06:38:18 +0000562 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
bellard3fb2ded2003-06-24 13:22:59 +0000563 }
pbrookd5975362008-06-07 20:50:51 +0000564 spin_unlock(&tb_lock);
malc55e8b852008-11-04 14:18:13 +0000565
566 /* cpu_interrupt might be called while translating the
567 TB, but before it is linked into a potentially
568 infinite loop and becomes env->current_tb. Avoid
569 starting execution if there is a pending interrupt. */
Jan Kiszkab0052d12010-06-25 16:56:50 +0200570 env->current_tb = tb;
571 barrier();
572 if (likely(!env->exit_request)) {
pbrook2e70f6e2008-06-29 01:03:05 +0000573 tc_ptr = tb->tc_ptr;
陳韋任e965fc32012-02-06 14:02:55 +0800574 /* execute the generated code */
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000575 next_tb = tcg_qemu_tb_exec(env, tc_ptr);
pbrook2e70f6e2008-06-29 01:03:05 +0000576 if ((next_tb & 3) == 2) {
thsbf20dc02008-06-30 17:22:19 +0000577 /* Instruction counter expired. */
pbrook2e70f6e2008-06-29 01:03:05 +0000578 int insns_left;
Stefan Weil69784ea2012-03-16 23:50:54 +0100579 tb = (TranslationBlock *)(next_tb & ~3);
pbrook2e70f6e2008-06-29 01:03:05 +0000580 /* Restore PC. */
aliguori622ed362008-11-18 19:36:03 +0000581 cpu_pc_from_tb(env, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000582 insns_left = env->icount_decr.u32;
583 if (env->icount_extra && insns_left >= 0) {
584 /* Refill decrementer and continue execution. */
585 env->icount_extra += insns_left;
586 if (env->icount_extra > 0xffff) {
587 insns_left = 0xffff;
588 } else {
589 insns_left = env->icount_extra;
590 }
591 env->icount_extra -= insns_left;
592 env->icount_decr.u16.low = insns_left;
593 } else {
594 if (insns_left > 0) {
595 /* Execute remaining instructions. */
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000596 cpu_exec_nocache(env, insns_left, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000597 }
598 env->exception_index = EXCP_INTERRUPT;
599 next_tb = 0;
Blue Swirl1162c042011-05-14 12:52:35 +0000600 cpu_loop_exit(env);
pbrook2e70f6e2008-06-29 01:03:05 +0000601 }
602 }
603 }
Jan Kiszkab0052d12010-06-25 16:56:50 +0200604 env->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000605 /* reset soft MMU for next block (it can currently
606 only be set by a memory fault) */
ths50a518e2007-06-03 18:52:15 +0000607 } /* for(;;) */
Jan Kiszka0d101932011-07-02 09:50:51 +0200608 } else {
609 /* Reload env after longjmp - the compiler may have smashed all
610 * local variables as longjmp is marked 'noreturn'. */
611 env = cpu_single_env;
bellard7d132992003-03-06 23:23:54 +0000612 }
bellard3fb2ded2003-06-24 13:22:59 +0000613 } /* for(;;) */
614
bellard7d132992003-03-06 23:23:54 +0000615
bellarde4533c72003-06-15 19:51:39 +0000616#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000617 /* restore flags in standard format */
Blue Swirle694d4e2011-05-16 19:38:48 +0000618 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
619 | (DF & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000620#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000621 /* XXX: Save/restore host fpu exception state?. */
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800622#elif defined(TARGET_UNICORE32)
bellard93ac68b2003-09-30 20:57:29 +0000623#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000624#elif defined(TARGET_PPC)
Michael Walle81ea0e12011-02-17 23:45:02 +0100625#elif defined(TARGET_LM32)
pbrooke6e59062006-10-22 00:18:54 +0000626#elif defined(TARGET_M68K)
627 cpu_m68k_flush_flags(env, env->cc_op);
628 env->cc_op = CC_OP_FLAGS;
629 env->sr = (env->sr & 0xffe0)
630 | env->cc_dest | (env->cc_x << 4);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200631#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000632#elif defined(TARGET_MIPS)
bellardfdf9b3e2006-04-27 21:07:38 +0000633#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000634#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000635#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100636#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400637#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000638 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000639#else
640#error unsupported target CPU
641#endif
pbrook1057eaa2007-02-04 13:37:44 +0000642
bellard6a00d602005-11-21 23:25:50 +0000643 /* fail safe : never use cpu_single_env outside cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000644 cpu_single_env = NULL;
bellard7d132992003-03-06 23:23:54 +0000645 return ret;
646}