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balrog80f515e2007-10-04 21:53:55 +00001#ifndef __SH_INTC_H__
2#define __SH_INTC_H__
3
aurel3296e2fc42008-11-21 21:06:42 +00004#include "qemu-common.h"
5#include "irq.h"
Benoît Canetb279e5e2011-11-17 14:23:01 +01006#include "exec-memory.h"
aurel3296e2fc42008-11-21 21:06:42 +00007
balrog80f515e2007-10-04 21:53:55 +00008typedef unsigned char intc_enum;
9
10struct intc_vect {
11 intc_enum enum_id;
12 unsigned short vect;
13};
14
15#define INTC_VECT(enum_id, vect) { enum_id, vect }
16
17struct intc_group {
18 intc_enum enum_id;
19 intc_enum enum_ids[32];
20};
21
Blue Swirl001faf32009-05-13 17:53:17 +000022#define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
balrog80f515e2007-10-04 21:53:55 +000023
24struct intc_mask_reg {
25 unsigned long set_reg, clr_reg, reg_width;
26 intc_enum enum_ids[32];
27 unsigned long value;
28};
29
30struct intc_prio_reg {
31 unsigned long set_reg, clr_reg, reg_width, field_width;
32 intc_enum enum_ids[16];
33 unsigned long value;
34};
35
malcb1503cd2008-12-22 20:33:55 +000036#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
balrog80f515e2007-10-04 21:53:55 +000037
38struct intc_source {
39 unsigned short vect;
40 intc_enum next_enum_id;
41
thse96e2042007-12-02 06:18:24 +000042 int asserted; /* emulates the interrupt signal line from device to intc */
balrog80f515e2007-10-04 21:53:55 +000043 int enable_count;
44 int enable_max;
thse96e2042007-12-02 06:18:24 +000045 int pending; /* emulates the result of signal and masking */
46 struct intc_desc *parent;
balrog80f515e2007-10-04 21:53:55 +000047};
48
49struct intc_desc {
Benoît Canetb279e5e2011-11-17 14:23:01 +010050 MemoryRegion iomem;
51 MemoryRegion *iomem_aliases;
aurel3296e2fc42008-11-21 21:06:42 +000052 qemu_irq *irqs;
balrog80f515e2007-10-04 21:53:55 +000053 struct intc_source *sources;
54 int nr_sources;
55 struct intc_mask_reg *mask_regs;
56 int nr_mask_regs;
57 struct intc_prio_reg *prio_regs;
58 int nr_prio_regs;
thse96e2042007-12-02 06:18:24 +000059 int pending; /* number of interrupt sources that has pending set */
balrog80f515e2007-10-04 21:53:55 +000060};
61
thse96e2042007-12-02 06:18:24 +000062int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
balrog80f515e2007-10-04 21:53:55 +000063struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
thse96e2042007-12-02 06:18:24 +000064void sh_intc_toggle_source(struct intc_source *source,
65 int enable_adj, int assert_adj);
balrog80f515e2007-10-04 21:53:55 +000066
67void sh_intc_register_sources(struct intc_desc *desc,
68 struct intc_vect *vectors,
69 int nr_vectors,
70 struct intc_group *groups,
71 int nr_groups);
72
Benoît Canetb279e5e2011-11-17 14:23:01 +010073int sh_intc_init(MemoryRegion *sysmem,
74 struct intc_desc *desc,
balrog80f515e2007-10-04 21:53:55 +000075 int nr_sources,
76 struct intc_mask_reg *mask_regs,
77 int nr_mask_regs,
78 struct intc_prio_reg *prio_regs,
79 int nr_prio_regs);
80
balrogc6d86a32008-12-07 18:49:57 +000081void sh_intc_set_irl(void *opaque, int n, int level);
82
balrog80f515e2007-10-04 21:53:55 +000083#endif /* __SH_INTC_H__ */