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review.linaro.org / people / peter.maydell / qemu-arm.git / f82a3d488a41d706b21c6eb8ada1dfaf8f03fb35 / . / sparc-dis.c
blob: dea6b11d78196c1c78057df81d67c7efb3686258 [file] [log] [blame]
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1/* Print SPARC instructions.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2002 Free Software Foundation, Inc.
4
5This program is free software; you can redistribute it and/or modify
6it under the terms of the GNU General Public License as published by
7the Free Software Foundation; either version 2 of the License, or
8(at your option) any later version.
9
10This program is distributed in the hope that it will be useful,
11but WITHOUT ANY WARRANTY; without even the implied warranty of
12MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13GNU General Public License for more details.
14
15You should have received a copy of the GNU General Public License
16along with this program; if not, write to the Free Software
17Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18#include <stdlib.h>
19#include "dis-asm.h"
20
21/* The SPARC opcode table (and other related data) is defined in
22 the opcodes library in sparc-opc.c. If you change anything here, make
23 sure you fix up that file, and vice versa. */
24
25 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
26 instruction's name rather than the args. This would make gas faster, pinsn
27 slower, but would mess up some macros a bit. xoxorich. */
28
29/* List of instruction sets variations.
30 These values are such that each element is either a superset of a
31 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
32 returns non-zero.
33 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
34 Don't change this without updating sparc-opc.c. */
35
36enum sparc_opcode_arch_val {
37 SPARC_OPCODE_ARCH_V6 = 0,
38 SPARC_OPCODE_ARCH_V7,
39 SPARC_OPCODE_ARCH_V8,
40 SPARC_OPCODE_ARCH_SPARCLET,
41 SPARC_OPCODE_ARCH_SPARCLITE,
42 /* v9 variants must appear last */
43 SPARC_OPCODE_ARCH_V9,
44 SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
45 SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
46 SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
47};
48
49/* The highest architecture in the table. */
50#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
51
52/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
53 insn encoding/decoding. */
54#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
55
56/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
57#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
58
59/* Table of cpu variants. */
60
61struct sparc_opcode_arch {
62 const char *name;
63 /* Mask of sparc_opcode_arch_val's supported.
64 EG: For v7 this would be
65 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
66 These are short's because sparc_opcode.architecture is. */
67 short supported;
68};
69
blueswir1f82a3d42008-10-01 18:13:13 +0000[diff] [blame^]70static const struct sparc_opcode_arch sparc_opcode_archs[];
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]71
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]72/* Return the bitmask of supported architectures for ARCH. */
73#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
74
75/* Non-zero if ARCH1 conflicts with ARCH2.
76 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
77#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
78(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
79 != SPARC_OPCODE_SUPPORTED (ARCH1)) \
80 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
81 != SPARC_OPCODE_SUPPORTED (ARCH2)))
82
83/* Structure of an opcode table entry. */
84
85struct sparc_opcode {
86 const char *name;
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]87 unsigned long match; /* Bits that must be set. */
88 unsigned long lose; /* Bits that must not be set. */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]89 const char *args;
90 /* This was called "delayed" in versions before the flags. */
91 char flags;
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]92 short architecture; /* Bitmask of sparc_opcode_arch_val's. */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]93};
94
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]95#define F_DELAYED 1 /* Delayed branch */
96#define F_ALIAS 2 /* Alias for a "real" instruction */
97#define F_UNBR 4 /* Unconditional branch */
98#define F_CONDBR 8 /* Conditional branch */
99#define F_JSR 16 /* Subroutine call */
100#define F_FLOAT 32 /* Floating point instruction (not a branch) */
101#define F_FBR 64 /* Floating point branch */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]102/* FIXME: Add F_ANACHRONISTIC flag for v9. */
103
104/*
105
106All sparc opcodes are 32 bits, except for the `set' instruction (really a
107macro), which is 64 bits. It is handled as a special case.
108
109The match component is a mask saying which bits must match a particular
110opcode in order for an instruction to be an instance of that opcode.
111
112The args component is a string containing one character for each operand of the
113instruction.
114
115Kinds of operands:
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]116 # Number used by optimizer. It is ignored.
117 1 rs1 register.
118 2 rs2 register.
119 d rd register.
120 e frs1 floating point register.
121 v frs1 floating point register (double/even).
122 V frs1 floating point register (quad/multiple of 4).
123 f frs2 floating point register.
124 B frs2 floating point register (double/even).
125 R frs2 floating point register (quad/multiple of 4).
126 g frsd floating point register.
127 H frsd floating point register (double/even).
128 J frsd floating point register (quad/multiple of 4).
129 b crs1 coprocessor register
130 c crs2 coprocessor register
131 D crsd coprocessor register
132 m alternate space register (asr) in rd
133 M alternate space register (asr) in rs1
134 h 22 high bits.
135 X 5 bit unsigned immediate
136 Y 6 bit unsigned immediate
137 3 SIAM mode (3 bits). (v9b)
138 K MEMBAR mask (7 bits). (v9)
139 j 10 bit Immediate. (v9)
140 I 11 bit Immediate. (v9)
141 i 13 bit Immediate.
142 n 22 bit immediate.
143 k 2+14 bit PC relative immediate. (v9)
144 G 19 bit PC relative immediate. (v9)
145 l 22 bit PC relative immediate.
146 L 30 bit PC relative immediate.
147 a Annul. The annul bit is set.
148 A Alternate address space. Stored as 8 bits.
149 C Coprocessor state register.
150 F floating point state register.
151 p Processor state register.
152 N Branch predict clear ",pn" (v9)
153 T Branch predict set ",pt" (v9)
154 z %icc. (v9)
155 Z %xcc. (v9)
156 q Floating point queue.
157 r Single register that is both rs1 and rd.
158 O Single register that is both rs2 and rd.
159 Q Coprocessor queue.
160 S Special case.
161 t Trap base register.
162 w Window invalid mask register.
163 y Y register.
164 u sparclet coprocessor registers in rd position
165 U sparclet coprocessor registers in rs1 position
166 E %ccr. (v9)
167 s %fprs. (v9)
168 P %pc. (v9)
169 W %tick. (v9)
170 o %asi. (v9)
171 6 %fcc0. (v9)
172 7 %fcc1. (v9)
173 8 %fcc2. (v9)
174 9 %fcc3. (v9)
175 ! Privileged Register in rd (v9)
176 ? Privileged Register in rs1 (v9)
177 * Prefetch function constant. (v9)
178 x OPF field (v9 impdep).
179 0 32/64 bit immediate for set or setx (v9) insns
180 _ Ancillary state register in rd (v9a)
181 / Ancillary state register in rs1 (v9a)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]182
183The following chars are unused: (note: ,[] are used as punctuation)
184[45]
185
186*/
187
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]188#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
189#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
190#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
191#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
192#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
193#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
194#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
195#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
196#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
197#define F1(x) (OP(x))
198#define DISP30(x) ((x)&0x3fffffff)
199#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
200#define RS2(x) ((x)&0x1f) /* rs2 field */
201#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
202#define RD(x) (((x)&0x1f) << 25) /* destination register field */
203#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
204#define ASI_RS2(x) (SIMM13(x))
205#define MEMBAR(x) ((x)&0x7f)
206#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]207
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]208#define ANNUL (1<<29)
209#define BPRED (1<<19) /* v9 */
210#define IMMED F3I(1)
211#define RD_G0 RD(~0)
212#define RS1_G0 RS1(~0)
213#define RS2_G0 RS2(~0)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]214
blueswir1f82a3d42008-10-01 18:13:13 +0000[diff] [blame^]215static const struct sparc_opcode sparc_opcodes[];
216static const int sparc_num_opcodes;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]217
blueswir1f82a3d42008-10-01 18:13:13 +0000[diff] [blame^]218static const char *sparc_decode_asi_v8 PARAMS ((int));
219static const char *sparc_decode_asi_v9 PARAMS ((int));
220static const char *sparc_decode_membar PARAMS ((int));
221static const char *sparc_decode_prefetch PARAMS ((int));
222static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]223
224/* Some defines to make life easy. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]225#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
226#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
227#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
228#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
229#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
230#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
231#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
232#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]233
234/* Bit masks of architectures supporting the insn. */
235
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]236#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
237 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]238/* v6 insns not supported on the sparclet */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]239#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
240 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
241#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
242 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]243/* Although not all insns are implemented in hardware, sparclite is defined
244 to be a superset of v8. Unimplemented insns trap and are then theoretically
245 implemented in software.
246 It's not clear that the same is true for sparclet, although the docs
247 suggest it is. Rather than complicating things, the sparclet assembler
248 recognizes all v8 insns. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]249#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
250 | MASK_V9 | MASK_V9A | MASK_V9B)
251#define sparclet (MASK_SPARCLET)
252#define sparclite (MASK_SPARCLITE)
253#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
254#define v9a (MASK_V9A | MASK_V9B)
255#define v9b (MASK_V9B)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]256/* v6 insns not supported by v9 */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]257#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
258 | MASK_SPARCLET | MASK_SPARCLITE)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]259/* v9a instructions which would appear to be aliases to v9's impdep's
260 otherwise */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]261#define v9notv9a (MASK_V9)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]262
263/* Table of opcode architectures.
264 The order is defined in opcode/sparc.h. */
265
blueswir1f82a3d42008-10-01 18:13:13 +0000[diff] [blame^]266static const struct sparc_opcode_arch sparc_opcode_archs[] = {
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]267 { "v6", MASK_V6 },
268 { "v7", MASK_V6 | MASK_V7 },
269 { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
270 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
271 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
blueswir17f75ffd2007-05-27 19:39:27 +0000[diff] [blame]272 /* ??? Don't some v8 privileged insns conflict with v9? */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]273 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
274 /* v9 with ultrasparc additions */
275 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
276 /* v9 with cheetah additions */
277 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
278 { NULL, 0 }
279};
280
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]281/* Branch condition field. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]282#define COND(x) (((x)&0xf)<<25)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]283
284/* v9: Move (MOVcc and FMOVcc) condition field. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]285#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]286
287/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]288#define RCOND(x) (((x)&0x7)<<10) /* v9 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]289
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]290#define CONDA (COND(0x8))
291#define CONDCC (COND(0xd))
292#define CONDCS (COND(0x5))
293#define CONDE (COND(0x1))
294#define CONDG (COND(0xa))
295#define CONDGE (COND(0xb))
296#define CONDGU (COND(0xc))
297#define CONDL (COND(0x3))
298#define CONDLE (COND(0x2))
299#define CONDLEU (COND(0x4))
300#define CONDN (COND(0x0))
301#define CONDNE (COND(0x9))
302#define CONDNEG (COND(0x6))
303#define CONDPOS (COND(0xe))
304#define CONDVC (COND(0xf))
305#define CONDVS (COND(0x7))
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]306
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]307#define CONDNZ CONDNE
308#define CONDZ CONDE
309#define CONDGEU CONDCC
310#define CONDLU CONDCS
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]311
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]312#define FCONDA (COND(0x8))
313#define FCONDE (COND(0x9))
314#define FCONDG (COND(0x6))
315#define FCONDGE (COND(0xb))
316#define FCONDL (COND(0x4))
317#define FCONDLE (COND(0xd))
318#define FCONDLG (COND(0x2))
319#define FCONDN (COND(0x0))
320#define FCONDNE (COND(0x1))
321#define FCONDO (COND(0xf))
322#define FCONDU (COND(0x7))
323#define FCONDUE (COND(0xa))
324#define FCONDUG (COND(0x5))
325#define FCONDUGE (COND(0xc))
326#define FCONDUL (COND(0x3))
327#define FCONDULE (COND(0xe))
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]328
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]329#define FCONDNZ FCONDNE
330#define FCONDZ FCONDE
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]331
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]332#define ICC (0) /* v9 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]333#define XCC (1<<12) /* v9 */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]334#define FCC(x) (((x)&0x3)<<11) /* v9 */
335#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]336
337/* The order of the opcodes in the table is significant:
ths5fafdf22007-09-16 21:08:06 +0000[diff] [blame]338
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]339 * The assembler requires that all instances of the same mnemonic must
340 be consecutive. If they aren't, the assembler will bomb at runtime.
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]341
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]342 * The disassembler should not care about the order of the opcodes.
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]343
344*/
345
346/* Entries for commutative arithmetic operations. */
347/* ??? More entries can make use of this. */
348#define COMMUTEOP(opcode, op3, arch_mask) \
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]349{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
350{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
351{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]352
blueswir1f82a3d42008-10-01 18:13:13 +0000[diff] [blame^]353static const struct sparc_opcode sparc_opcodes[] = {
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]354
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]355{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
356{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
357{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 },
358{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 },
359{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 },
360{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */
361{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 },
362{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
363{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 },
364{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 },
365{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 },
366{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]367
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]368{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 },
369{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
370{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 },
371{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 },
372{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
373{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]374
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]375{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 },
376{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
377{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 },
378{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 },
379{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
380{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
381{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 },
382{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
383{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 },
384{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 },
385{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 },
386{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]387
388/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
389 'ld' pseudo-op in v9. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]390{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 },
391{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
392{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 },
393{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 },
394{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 },
395{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]396
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]397{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
398{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
399{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 },
400{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 },
401{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 },
402{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */
403{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
404{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
405{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 },
406{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 },
407{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 },
408{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]409
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]410{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
411{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
412{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 },
413{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 },
414{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
415{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]416
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]417{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
418{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
419{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 },
420{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 },
421{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 },
422{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]423
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]424{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
425{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
426{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 },
427{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 },
428{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 },
429{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]430
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]431{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
432{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
433{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 },
434{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 },
435{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 },
436{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]437
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]438{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
439{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
440{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 },
441{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 },
442{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 },
443{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]444
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]445{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
446{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
447{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 },
448{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 },
449{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 },
450{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]451
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]452{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
453{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
454{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 },
455{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 },
456{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 },
457{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]458
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]459{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
460{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
461{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 },
462{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 },
463{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 },
464{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]465
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]466{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
467{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
468{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 },
469{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 },
470{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 },
471{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]472
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]473{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
474{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
475{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
476{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
477{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 },
478{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]479
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]480{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 },
481{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
482{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 },
483{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 },
484{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 },
485{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
486{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 },
487{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
488{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 },
489{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 },
490{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 },
491{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]492
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]493{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 },
494{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
495{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 },
496{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 },
497{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 },
498{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]499
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]500{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 },
501{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
502{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 },
503{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 },
504{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 },
505{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]506
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]507{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 },
508{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
509{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 },
510{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 },
511{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 },
512{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]513
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]514{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 },
515{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
516{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 },
517{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 },
518{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 },
519{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]520
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]521{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 },
522{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
523{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 },
524{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 },
525{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 },
526{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]527
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]528{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 },
529{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
530{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 },
531{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 },
532{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 },
533{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]534
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]535{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 },
536{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
537{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 },
538{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 },
539{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 },
540{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]541
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]542{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 },
543{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
544{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 },
545{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 },
546{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 },
547{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]548
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]549{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 },
550{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
551{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 },
552{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 },
553{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 },
554{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]555
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]556{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
557{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
558{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 },
559{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 },
560{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 },
561{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]562
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]563{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 },
564{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
565{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 },
566{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 },
567{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 },
568{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]569
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]570{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
571{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
572{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 },
573{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 },
574{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 },
575{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */
576{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 },
577{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
578{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 },
579{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 },
580{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 },
581{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]582
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]583{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
584{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
585{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 },
586{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 },
587{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
588{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
589{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 },
590{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
591{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 },
592{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 },
593{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 },
594{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]595
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]596{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 },
597{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
598{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 },
599{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 },
600{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 },
601{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]602
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]603{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
604{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
605{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
606{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
607{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
608{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
609{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
610{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
611{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
612{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
613{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
614{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
615{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
616{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
617{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
618{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
619{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
620{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]621
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]622{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
623{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
624{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 },
625{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 },
626{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
627{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]628
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]629{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 },
630{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
631{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 },
632{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 },
633{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 },
634{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]635
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]636{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 },
637{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
638{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 },
639{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 },
640{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 },
641{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]642
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]643{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
644{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
645{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
646{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
647{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
648{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
649{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
650{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
651{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
652{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
653{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
654{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
655{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
656{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
657{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
658{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
659{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
660{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]661
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]662{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
663{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
664{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 },
665{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 },
666{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 },
667{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]668
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]669{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
670{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
671{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
672{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
673{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
674{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
675{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
676{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
677{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
678{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
679{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
680{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]681
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]682{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 },
683{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
684{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 },
685{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 },
686{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 },
687{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]688
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]689{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
690{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
691{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
692{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
693{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
694{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
695{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
696{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
697{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
698{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
699{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
700{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]701
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]702{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
703{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
704{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 },
705{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 },
706{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 },
707{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]708
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]709{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
710{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
711{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 },
712{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 },
713{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 },
714{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
715{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
716{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
717{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 },
718{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 },
719{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 },
720{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]721
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]722{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
723{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
724{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 },
725{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 },
726{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 },
727{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
728{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
729{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
730{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 },
731{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 },
732{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
733{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]734
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]735{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
736{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
737{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 },
738{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 },
739{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
740{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]741
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]742{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 },
743{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
744{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 },
745{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 },
746{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 },
747{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
748{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 },
749{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
750{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 },
751{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 },
752{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 },
753{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]754
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]755{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
756{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
757{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 },
758{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 },
759{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 },
760{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]761
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]762{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
763{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
764{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
765{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
766{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
767{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
768{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
769{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
770{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
771{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
772{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
773{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]774
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]775{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 },
776{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
777{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 },
778{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 },
779{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 },
780{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]781
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]782{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
783{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
784{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
785{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
786{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
787{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
788{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
789{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
790{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
791{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
792{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
793{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]794
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]795{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
796{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
797{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 },
798{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 },
799{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 },
800{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]801
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]802{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
803{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
804{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 },
805{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 },
806{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 },
807{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]808
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]809{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 },
810{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
811{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 },
812{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 },
813{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 },
814{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]815
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]816{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
817{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
818{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 },
819{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 },
820{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 },
821{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]822
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]823{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
824{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
825{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 },
826{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 },
827{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 },
828{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]829
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]830{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
831{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
832{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 },
833{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 },
834{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 },
835{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]836
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]837{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 },
838{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
839{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 },
840{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 },
841{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 },
842{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]843
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]844{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 },
845{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */
846{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 },
847{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]848
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]849{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
850{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */
851{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
852{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
853{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
854{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */
855{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]856
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]857{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
858{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 },
859{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]860
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]861{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]862{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
863
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]864{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
865{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
866{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
867{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
868{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 },
869{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]870
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]871{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
872{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
873{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
874{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
875{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]876
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]877{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
878{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */
879{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */
880{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */
881{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 },
882{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]883
884/* IFLUSH was renamed to FLUSH in v8. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]885{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
886{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
887{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */
888{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 },
889{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 },
890{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]891
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]892{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
893{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */
894{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */
895{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */
896{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 },
897{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]898
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]899{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]900
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]901{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
902{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]903
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]904{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 },
905{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
906{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 },
907{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 },
908{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 },
909{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
910{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 },
911{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
912{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 },
913{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 },
914{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 },
915{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]916
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]917{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
918{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
919{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
920{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
921{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
922{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]923
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]924{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
925{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
926{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
927{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
928{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
929{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]930
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]931{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
932{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]933
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]934{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
935{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]936
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]937{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
938{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]939
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]940{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
941{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]942
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]943{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
944{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */
945{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
946{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
947{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
948{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
949{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
950{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]951
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]952{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
953{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
954{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
955{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
956{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
957{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]958
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]959{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
960{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
961{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
962{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
963{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
964{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]965
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]966{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 },
967{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
968{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 },
969{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 },
970{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 },
971{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]972
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]973{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
974{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 },
975{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]976
977/* This is not a commutative instruction. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]978{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
979{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]980
981/* This is not a commutative instruction. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]982{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
983{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]984
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]985{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
986{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
987{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]988
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]989{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */
990{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */
991{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
992{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */
993{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */
994{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
995{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
996{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
997{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
998{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
999{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
1000{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1001{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
1002{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
1003{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1004
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1005{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
1006{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */
1007{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
1008{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */
1009{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */
1010{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1011
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1012{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */
1013{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */
1014{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */
1015{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */
1016{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */
1017{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */
1018{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */
1019{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */
1020{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
1021{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
1022{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
1023{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
1024{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */
1025{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */
1026{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
1027{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
1028{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
1029{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
1030{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
1031{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1032
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1033{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
1034{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
1035{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
1036{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
1037{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1038
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1039{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
1040{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
1041{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
1042{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
1043{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1044
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1045{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */
1046{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */
1047{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */
1048{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
1049{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
1050{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
1051{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
1052{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1053
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1054{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
1055{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
1056{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */
1057{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
1058{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
1059{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1060
1061/* ??? This group seems wrong. A three operand move? */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1062{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1063{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
1064{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
1065{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
1066{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
1067{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
1068{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
1069{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
1070{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
1071{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1072
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1073{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
1074{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */
1075{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
1076{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
1077{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1078
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1079{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1080{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
1081{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
1082{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1083{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
1084{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
1085{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1086{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
1087{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
1088{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1089{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
1090{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
1091{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1092{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
1093{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1094
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1095{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */
1096{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */
1097{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */
1098{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1099
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1100{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
1101{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 },
1102{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1103
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1104{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */
1105{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1106
1107/* This is not a commutative instruction. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1108{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
1109{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1110
1111/* This is not a commutative instruction. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1112{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
1113{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1114
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1115{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */
1116{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1117
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1118{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
1119{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1120
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1121{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
1122{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1123
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1124{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
1125{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1126
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1127{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1128{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 },
1129{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 },
1130{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1131
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1132{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1133{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 },
1134{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 },
1135{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1136
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1137{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
1138{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 },
1139{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1140
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1141{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
1142{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 },
1143{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1144
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1145{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */
1146{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */
1147{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */
1148{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */
1149{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */
1150{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */
1151{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */
1152{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1153
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1154{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */
1155{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1156
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1157{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
1158{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1159
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1160{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
1161{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 },
1162{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 },
1163{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
1164{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 },
1165{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1166
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1167{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1168{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 },
1169{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 },
1170{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 },
1171{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 },
1172{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1173
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1174{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1175{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 },
1176{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 },
1177{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 },
1178{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 },
1179{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1180
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1181{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1182{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 },
1183{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 },
1184{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1185{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 },
1186{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 },
1187{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1188{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 },
1189{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 },
1190{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1191{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 },
1192{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 },
1193{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1194{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 },
1195{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 },
1196{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1197{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 },
1198{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 },
1199{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1200{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 },
1201{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 },
1202{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1203{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 },
1204{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1205
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1206{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
1207{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 },
1208{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1209{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 },
1210{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1211{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1212
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1213{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
1214{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1215
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1216{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
1217{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 },
1218{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
1219{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
1220{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
1221{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 },
1222{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
1223{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 },
1224{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
1225{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 },
1226{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
1227{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1228
1229
1230/* Conditional instructions.
1231
1232 Because this part of the table was such a mess earlier, I have
1233 macrofied it so that all the branches and traps are generated from
1234 a single-line description of each condition value. John Gilmore. */
1235
1236/* Define branches -- one annulled, one without, etc. */
1237#define br(opcode, mask, lose, flags) \
1238 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
1239 { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
1240
1241#define brx(opcode, mask, lose, flags) /* v9 */ \
1242 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
1243 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
1244 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
1245 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1246 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
1247 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1248 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
1249 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
1250 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
1251 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1252 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
1253 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1254
1255/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1256#define tr(opcode, mask, lose, flags) \
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1257 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \
1258 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1259 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1260 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \
1261 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1262 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1263 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1264 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1265 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
1266 { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
1267 { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
1268 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1269
1270/* v9: We must put `brx' before `br', to ensure that we never match something
1271 v9: against an expression unless it is an expression. Otherwise, we end
1272 v9: up with undefined symbol tables entries, because they get added, but
1273 v9: are not deleted if the pattern fails to match. */
1274
1275/* Define both branches and traps based on condition mask */
1276#define cond(bop, top, mask, flags) \
1277 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1278 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1279 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1280
1281/* Define all the conditions, all the branches, all the traps. */
1282
1283/* Standard branch, trap mnemonics */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1284cond ("b", "ta", CONDA, F_UNBR),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1285/* Alternative form (just for assembly, not for disassembly) */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1286cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1287
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1288cond ("bcc", "tcc", CONDCC, F_CONDBR),
1289cond ("bcs", "tcs", CONDCS, F_CONDBR),
1290cond ("be", "te", CONDE, F_CONDBR),
1291cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
1292cond ("bg", "tg", CONDG, F_CONDBR),
1293cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
1294cond ("bge", "tge", CONDGE, F_CONDBR),
1295cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1296cond ("bgu", "tgu", CONDGU, F_CONDBR),
1297cond ("bl", "tl", CONDL, F_CONDBR),
1298cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
1299cond ("ble", "tle", CONDLE, F_CONDBR),
1300cond ("bleu", "tleu", CONDLEU, F_CONDBR),
1301cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1302cond ("bn", "tn", CONDN, F_CONDBR),
1303cond ("bne", "tne", CONDNE, F_CONDBR),
1304cond ("bneg", "tneg", CONDNEG, F_CONDBR),
1305cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1306cond ("bpos", "tpos", CONDPOS, F_CONDBR),
1307cond ("bvc", "tvc", CONDVC, F_CONDBR),
1308cond ("bvs", "tvs", CONDVS, F_CONDBR),
1309cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1310
1311#undef cond
1312#undef br
1313#undef brr /* v9 */
1314#undef tr
1315
1316#define brr(opcode, mask, lose, flags) /* v9 */ \
1317 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
1318 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
1319 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
1320 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1321 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
1322 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1323
1324#define condr(bop, mask, flags) /* v9 */ \
1325 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1326
1327/* v9 */ condr("brnz", 0x5, F_CONDBR),
1328/* v9 */ condr("brz", 0x1, F_CONDBR),
1329/* v9 */ condr("brgez", 0x7, F_CONDBR),
1330/* v9 */ condr("brlz", 0x3, F_CONDBR),
1331/* v9 */ condr("brlez", 0x2, F_CONDBR),
1332/* v9 */ condr("brgz", 0x6, F_CONDBR),
1333
1334#undef condr /* v9 */
1335#undef brr /* v9 */
1336
1337#define movr(opcode, mask, flags) /* v9 */ \
1338 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1339 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1340
1341#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1342 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1343#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1344 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1345#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1346 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1347
1348#define fmovrs(mop, mask, flags) /* v9 */ \
1349 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1350#define fmovrd(mop, mask, flags) /* v9 */ \
1351 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1352#define fmovrq(mop, mask, flags) /* v9 */ \
1353 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1354
1355/* v9 */ movr("movrne", 0x5, 0),
1356/* v9 */ movr("movre", 0x1, 0),
1357/* v9 */ movr("movrgez", 0x7, 0),
1358/* v9 */ movr("movrlz", 0x3, 0),
1359/* v9 */ movr("movrlez", 0x2, 0),
1360/* v9 */ movr("movrgz", 0x6, 0),
1361/* v9 */ movr("movrnz", 0x5, F_ALIAS),
1362/* v9 */ movr("movrz", 0x1, F_ALIAS),
1363
1364/* v9 */ fmovrs("fmovrsne", 0x5, 0),
1365/* v9 */ fmovrs("fmovrse", 0x1, 0),
1366/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1367/* v9 */ fmovrs("fmovrslz", 0x3, 0),
1368/* v9 */ fmovrs("fmovrslez", 0x2, 0),
1369/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1370/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1371/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1372
1373/* v9 */ fmovrd("fmovrdne", 0x5, 0),
1374/* v9 */ fmovrd("fmovrde", 0x1, 0),
1375/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1376/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1377/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1378/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1379/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1380/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1381
1382/* v9 */ fmovrq("fmovrqne", 0x5, 0),
1383/* v9 */ fmovrq("fmovrqe", 0x1, 0),
1384/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1385/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1386/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1387/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1388/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1389/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1390
1391#undef movr /* v9 */
1392#undef fmovr /* v9 */
1393#undef fmrr /* v9 */
1394
1395#define movicc(opcode, cond, flags) /* v9 */ \
1396 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1397 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1398 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
1399 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
1400
1401#define movfcc(opcode, fcond, flags) /* v9 */ \
1402 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1403 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1404 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1405 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1406 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1407 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1408 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1409 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1410
1411#define movcc(opcode, cond, fcond, flags) /* v9 */ \
1412 movfcc (opcode, fcond, flags), /* v9 */ \
1413 movicc (opcode, cond, flags) /* v9 */
1414
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1415/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
1416/* v9 */ movicc ("movcc", CONDCC, 0),
1417/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
1418/* v9 */ movicc ("movcs", CONDCS, 0),
1419/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
1420/* v9 */ movcc ("move", CONDE, FCONDE, 0),
1421/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
1422/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
1423/* v9 */ movicc ("movgu", CONDGU, 0),
1424/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
1425/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
1426/* v9 */ movicc ("movleu", CONDLEU, 0),
1427/* v9 */ movfcc ("movlg", FCONDLG, 0),
1428/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
1429/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
1430/* v9 */ movicc ("movneg", CONDNEG, 0),
1431/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
1432/* v9 */ movfcc ("movo", FCONDO, 0),
1433/* v9 */ movicc ("movpos", CONDPOS, 0),
1434/* v9 */ movfcc ("movu", FCONDU, 0),
1435/* v9 */ movfcc ("movue", FCONDUE, 0),
1436/* v9 */ movfcc ("movug", FCONDUG, 0),
1437/* v9 */ movfcc ("movuge", FCONDUGE, 0),
1438/* v9 */ movfcc ("movul", FCONDUL, 0),
1439/* v9 */ movfcc ("movule", FCONDULE, 0),
1440/* v9 */ movicc ("movvc", CONDVC, 0),
1441/* v9 */ movicc ("movvs", CONDVS, 0),
1442/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1443
1444#undef movicc /* v9 */
1445#undef movfcc /* v9 */
1446#undef movcc /* v9 */
1447
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1448#define FM_SF 1 /* v9 - values for fpsize */
1449#define FM_DF 2 /* v9 */
1450#define FM_QF 3 /* v9 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1451
1452#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \
1453{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \
1454{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 }
1455
1456#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \
1457{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
1458{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
1459{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
1460{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
1461
1462/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1463#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \
1464{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \
1465{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \
1466{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \
1467{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \
1468{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \
1469{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 }
1470
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1471/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0),
1472/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0),
1473/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0),
1474/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0),
1475/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0),
1476/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0),
1477/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0),
1478/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0),
1479/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0),
1480/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0),
1481/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0),
1482/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0),
1483/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0),
1484/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0),
1485/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0),
1486/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0),
1487/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0),
1488/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0),
1489/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS),
1490/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS),
1491/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS),
1492/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0),
1493/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0),
1494/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0),
1495/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0),
1496/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0),
1497/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0),
1498/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0),
1499/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0),
1500/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0),
1501/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0),
1502/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0),
1503/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0),
1504/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0),
1505/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0),
1506/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0),
1507/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS),
1508/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS),
1509/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS),
1510/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0),
1511/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0),
1512/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0),
1513/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0),
1514/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0),
1515/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0),
1516/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0),
1517/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0),
1518/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0),
1519/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS),
1520/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS),
1521/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS),
1522/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0),
1523/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0),
1524/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0),
1525/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0),
1526/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0),
1527/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0),
1528/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0),
1529/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0),
1530/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0),
1531/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0),
1532/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0),
1533/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0),
1534/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0),
1535/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0),
1536/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0),
1537/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0),
1538/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0),
1539/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0),
1540/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0),
1541/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0),
1542/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0),
1543/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0),
1544/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0),
1545/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0),
1546/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0),
1547/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0),
1548/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0),
1549/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0),
1550/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0),
1551/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0),
1552/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS),
1553/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS),
1554/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1555
1556#undef fmovicc /* v9 */
1557#undef fmovfcc /* v9 */
1558#undef fmovcc /* v9 */
1559#undef FM_DF /* v9 */
1560#undef FM_QF /* v9 */
1561#undef FM_SF /* v9 */
1562
1563/* Coprocessor branches. */
1564#define CBR(opcode, mask, lose, flags, arch) \
1565 { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \
1566 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
1567
1568/* Floating point branches. */
1569#define FBR(opcode, mask, lose, flags) \
1570 { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \
1571 { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
1572
1573/* V9 extended floating point branches. */
1574#define FBRX(opcode, mask, lose, flags) /* v9 */ \
1575 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \
1576 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1577 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1578 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1579 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1580 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1581 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \
1582 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1583 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1584 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1585 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1586 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1587 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \
1588 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1589 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1590 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1591 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1592 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1593 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \
1594 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1595 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1596 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1597 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1598 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1599
1600/* v9: We must put `FBRX' before `FBR', to ensure that we never match
1601 v9: something against an expression unless it is an expression. Otherwise,
1602 v9: we end up with undefined symbol tables entries, because they get added,
1603 v9: but are not deleted if the pattern fails to match. */
1604
1605#define CONDFC(fop, cop, mask, flags) \
1606 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1607 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1608 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1609
1610#define CONDFCL(fop, cop, mask, flags) \
1611 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1612 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1613 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1614
1615#define CONDF(fop, mask, flags) \
1616 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1617 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1618
1619CONDFC ("fb", "cb", 0x8, F_UNBR),
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1620CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
1621CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1622CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1623CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1624CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1625CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1626CONDFC ("fble", "cb01", 0xd, F_CONDBR),
1627CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1628CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1629CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
1630CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1631CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
1632CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1633CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
1634CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
1635CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
1636CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
1637CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
1638
1639#undef CONDFC
1640#undef CONDFCL
1641#undef CONDF
1642#undef CBR
1643#undef FBR
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1644#undef FBRX /* v9 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1645
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1646{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
1647{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
1648{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
1649{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
1650{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
1651{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1652
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1653{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1654
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1655{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
1656{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1657{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1658{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1659
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1660{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1661
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1662{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
1663{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 },
1664{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 },
1665{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
1666{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 },
1667{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1668
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1669{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
1670{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 },
1671{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
1672{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1673
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1674{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
1675{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1676
1677/* This *is* a commutative instruction. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1678{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
1679{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 },
1680{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1681/* This *is* a commutative instruction. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1682{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
1683{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 },
1684{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 },
1685{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
1686{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 },
1687{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 },
1688{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
1689{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 },
1690{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1691
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1692{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
1693{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1694
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1695{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
1696{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1697
1698/* FPop1 and FPop2 are not instructions. Don't accept them. */
1699
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1700{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
1701{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1702{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1703
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1704{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 },
1705{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 },
1706{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1707
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1708{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1709{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1710{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1711
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1712{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 },
1713{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 },
1714{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1715
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1716{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1717{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
1718{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1719{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1720{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
1721{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1722
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1723{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
1724{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1725{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1726{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
1727{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
1728{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1729{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1730{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1731
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1732{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
1733{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
1734{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1735
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1736{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1737{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1738{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1739{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1740
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1741{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
1742{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1743{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1744{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
1745{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
1746{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1747{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1748{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
1749{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
1750{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1751{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1752{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1753
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1754{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
1755{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1756{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1757{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
1758{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
1759{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1760{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1761{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1762
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1763#define CMPFCC(x) (((x)&0x3)<<25)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1764
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1765{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 },
1766{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 },
1767{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 },
1768{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 },
1769{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 },
1770{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 },
1771{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 },
1772{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 },
1773{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 },
1774{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 },
1775{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 },
1776{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 },
1777{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 },
1778{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 },
1779{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 },
1780{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 },
1781{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 },
1782{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 },
1783{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 },
1784{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 },
1785{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1786{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1787{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1788{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1789{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1790{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1791{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1792{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1793{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1794{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1795{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 },
1796{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 },
1797{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 },
1798{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 },
1799{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 },
1800{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 },
1801{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 },
1802{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 },
1803{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 },
1804{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1805
1806/* These Extended FPop (FIFO) instructions are new in the Fujitsu
1807 MB86934, replacing the CPop instructions from v6 and later
1808 processors. */
1809
1810#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1811#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite }
1812#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite }
1813
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1814EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1815EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1816EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1817EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1818EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1819EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1820EFPOP1_2 ("efmovs", 0x001, "f,g"),
1821EFPOP1_2 ("efnegs", 0x005, "f,g"),
1822EFPOP1_2 ("efabss", 0x009, "f,g"),
1823EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1824EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1825EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1826EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1827EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1828EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1829EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1830EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1831EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1832EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1833EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1834EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1835EFPOP2_2 ("efcmped", 0x056, "v,B"),
1836EFPOP2_2 ("efcmps", 0x051, "e,f"),
1837EFPOP2_2 ("efcmpes", 0x055, "e,f"),
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1838
1839#undef EFPOP1_2
1840#undef EFPOP1_3
1841#undef EFPOP2_2
1842
1843/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1844 present. Otherwise, the F_ALIAS flag is ignored. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1845{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1846{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1847
1848/* sparclet specific insns */
1849
1850COMMUTEOP ("umac", 0x3e, sparclet),
1851COMMUTEOP ("smac", 0x3f, sparclet),
1852COMMUTEOP ("umacd", 0x2e, sparclet),
1853COMMUTEOP ("smacd", 0x2f, sparclet),
1854COMMUTEOP ("umuld", 0x09, sparclet),
1855COMMUTEOP ("smuld", 0x0d, sparclet),
1856
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1857{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
1858{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1859
1860/* The manual isn't completely accurate on these insns. The `rs2' field is
1861 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1862 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1863#define BIT5 (1<<5)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1864{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
1865{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
1866{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
1867{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet },
1868{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
1869{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet },
1870{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1871#undef BIT5
1872
1873/* sparclet coprocessor branch insns */
1874#define SLCBCC2(opcode, mask, lose) \
1875 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
1876 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1877#define SLCBCC(opcode, mask) \
1878 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1879
1880/* cbn,cba can't be defined here because they're defined elsewhere and GAS
1881 requires all mnemonics of the same name to be consecutive. */
1882/*SLCBCC("cbn", 0), - already defined */
1883SLCBCC("cbe", 1),
1884SLCBCC("cbf", 2),
1885SLCBCC("cbef", 3),
1886SLCBCC("cbr", 4),
1887SLCBCC("cber", 5),
1888SLCBCC("cbfr", 6),
1889SLCBCC("cbefr", 7),
1890/*SLCBCC("cba", 8), - already defined */
1891SLCBCC("cbne", 9),
1892SLCBCC("cbnf", 10),
1893SLCBCC("cbnef", 11),
1894SLCBCC("cbnr", 12),
1895SLCBCC("cbner", 13),
1896SLCBCC("cbnfr", 14),
1897SLCBCC("cbnefr", 15),
1898
1899#undef SLCBCC2
1900#undef SLCBCC
1901
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1902{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
1903{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
1904{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
1905{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1906
1907/* v9 synthetic insns */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1908{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
1909{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
1910{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
1911{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
1912{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
1913{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1914{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1915{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1916{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1917
1918/* Ultrasparc extensions */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1919{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1920
1921/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1922{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
1923{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
1924{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
1925{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
1926{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
1927{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
1928{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
1929{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1930
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1931{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
1932{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
1933{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
1934{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
1935{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1936
1937/* Note that the mixing of 32/64 bit regs is intentional. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1938{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
1939{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
1940{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
1941{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
1942{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
1943{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
1944{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1945
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1946{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
1947{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
1948{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1949
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1950{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
1951{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
1952{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
1953{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
1954{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
1955{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
1956{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
1957{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
1958{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
1959{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
1960{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
1961{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
1962{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
1963{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
1964{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
1965{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
1966{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
1967{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
1968{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
1969{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
1970{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
1971{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
1972{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
1973{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
1974{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
1975{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
1976{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
1977{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
1978{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
1979{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
1980{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
1981{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1982
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1983{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
1984{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
1985{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
1986{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
1987{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
1988{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
1989{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
1990{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1991
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1992{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
1993{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
1994{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
1995{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
1996{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
1997{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]1998
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]1999{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2000
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2001{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
2002{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
2003{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2004
2005/* Cheetah instructions */
2006{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
2007{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
2008{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
2009{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
2010{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
2011{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
2012
2013{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
2014{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
2015
2016{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
2017
2018/* More v9 specific insns, these need to come last so they do not clash
2019 with v9a instructions such as "edge8" which looks like impdep1. */
2020
2021#define IMPDEP(name, code) \
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2022{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2023{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2024{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \
2025{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a }
2026
2027IMPDEP ("impdep1", 0x36),
2028IMPDEP ("impdep2", 0x37),
2029
2030#undef IMPDEP
2031
2032};
2033
blueswir1f82a3d42008-10-01 18:13:13 +0000[diff] [blame^]2034static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2035
2036/* Utilities for argument parsing. */
2037
2038typedef struct
2039{
2040 int value;
2041 const char *name;
2042} arg;
2043
2044/* Look up NAME in TABLE. */
2045
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2046static const char *lookup_value PARAMS ((const arg *, int));
2047
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2048/* Look up VALUE in TABLE. */
2049
2050static const char *
2051lookup_value (table, value)
2052 const arg *table;
2053 int value;
2054{
2055 const arg *p;
2056
2057 for (p = table; p->name; ++p)
2058 if (value == p->value)
2059 return p->name;
2060
2061 return (char *) 0;
2062}
2063
2064/* Handle ASI's. */
2065
bellard1983a392005-10-30 15:45:19 +0000[diff] [blame]2066static const arg asi_table_v8[] =
2067{
2068 { 0x00, "#ASI_M_RES00" },
2069 { 0x01, "#ASI_M_UNA01" },
2070 { 0x02, "#ASI_M_MXCC" },
2071 { 0x03, "#ASI_M_FLUSH_PROBE" },
2072 { 0x04, "#ASI_M_MMUREGS" },
2073 { 0x05, "#ASI_M_TLBDIAG" },
2074 { 0x06, "#ASI_M_DIAGS" },
2075 { 0x07, "#ASI_M_IODIAG" },
2076 { 0x08, "#ASI_M_USERTXT" },
2077 { 0x09, "#ASI_M_KERNELTXT" },
2078 { 0x0A, "#ASI_M_USERDATA" },
2079 { 0x0B, "#ASI_M_KERNELDATA" },
2080 { 0x0C, "#ASI_M_TXTC_TAG" },
2081 { 0x0D, "#ASI_M_TXTC_DATA" },
2082 { 0x0E, "#ASI_M_DATAC_TAG" },
2083 { 0x0F, "#ASI_M_DATAC_DATA" },
2084 { 0x10, "#ASI_M_FLUSH_PAGE" },
2085 { 0x11, "#ASI_M_FLUSH_SEG" },
2086 { 0x12, "#ASI_M_FLUSH_REGION" },
2087 { 0x13, "#ASI_M_FLUSH_CTX" },
2088 { 0x14, "#ASI_M_FLUSH_USER" },
2089 { 0x17, "#ASI_M_BCOPY" },
2090 { 0x18, "#ASI_M_IFLUSH_PAGE" },
2091 { 0x19, "#ASI_M_IFLUSH_SEG" },
2092 { 0x1A, "#ASI_M_IFLUSH_REGION" },
2093 { 0x1B, "#ASI_M_IFLUSH_CTX" },
2094 { 0x1C, "#ASI_M_IFLUSH_USER" },
2095 { 0x1F, "#ASI_M_BFILL" },
2096 { 0x20, "#ASI_M_BYPASS" },
2097 { 0x29, "#ASI_M_FBMEM" },
2098 { 0x2A, "#ASI_M_VMEUS" },
2099 { 0x2B, "#ASI_M_VMEPS" },
2100 { 0x2C, "#ASI_M_VMEUT" },
2101 { 0x2D, "#ASI_M_VMEPT" },
2102 { 0x2E, "#ASI_M_SBUS" },
2103 { 0x2F, "#ASI_M_CTL" },
2104 { 0x31, "#ASI_M_FLUSH_IWHOLE" },
2105 { 0x36, "#ASI_M_IC_FLCLEAR" },
2106 { 0x37, "#ASI_M_DC_FLCLEAR" },
2107 { 0x39, "#ASI_M_DCDR" },
2108 { 0x40, "#ASI_M_VIKING_TMP1" },
2109 { 0x41, "#ASI_M_VIKING_TMP2" },
2110 { 0x4c, "#ASI_M_ACTION" },
2111 { 0, 0 }
2112};
2113
2114static const arg asi_table_v9[] =
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2115{
2116 /* These are in the v9 architecture manual. */
2117 /* The shorter versions appear first, they're here because Sun's as has them.
2118 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2119 UltraSPARC architecture manual). */
2120 { 0x04, "#ASI_N" },
2121 { 0x0c, "#ASI_N_L" },
2122 { 0x10, "#ASI_AIUP" },
2123 { 0x11, "#ASI_AIUS" },
2124 { 0x18, "#ASI_AIUP_L" },
2125 { 0x19, "#ASI_AIUS_L" },
2126 { 0x80, "#ASI_P" },
2127 { 0x81, "#ASI_S" },
2128 { 0x82, "#ASI_PNF" },
2129 { 0x83, "#ASI_SNF" },
2130 { 0x88, "#ASI_P_L" },
2131 { 0x89, "#ASI_S_L" },
2132 { 0x8a, "#ASI_PNF_L" },
2133 { 0x8b, "#ASI_SNF_L" },
2134 { 0x04, "#ASI_NUCLEUS" },
2135 { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2136 { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2137 { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2138 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2139 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2140 { 0x80, "#ASI_PRIMARY" },
2141 { 0x81, "#ASI_SECONDARY" },
2142 { 0x82, "#ASI_PRIMARY_NOFAULT" },
2143 { 0x83, "#ASI_SECONDARY_NOFAULT" },
2144 { 0x88, "#ASI_PRIMARY_LITTLE" },
2145 { 0x89, "#ASI_SECONDARY_LITTLE" },
2146 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2147 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2148 /* These are UltraSPARC extensions. */
2149 /* FIXME: There are dozens of them. Not sure we want them all.
2150 Most are for kernel building but some are for vis type stuff. */
2151 { 0, 0 }
2152};
2153
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2154/* Return the name for ASI value VALUE or NULL if not found. */
2155
bellard1983a392005-10-30 15:45:19 +0000[diff] [blame]2156static const char *
2157sparc_decode_asi_v9 (int value)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2158{
bellard1983a392005-10-30 15:45:19 +0000[diff] [blame]2159 return lookup_value (asi_table_v9, value);
2160}
2161
2162static const char *
2163sparc_decode_asi_v8 (int value)
2164{
2165 return lookup_value (asi_table_v8, value);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2166}
2167
2168/* Handle membar masks. */
2169
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2170static const arg membar_table[] =
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2171{
2172 { 0x40, "#Sync" },
2173 { 0x20, "#MemIssue" },
2174 { 0x10, "#Lookaside" },
2175 { 0x08, "#StoreStore" },
2176 { 0x04, "#LoadStore" },
2177 { 0x02, "#StoreLoad" },
2178 { 0x01, "#LoadLoad" },
2179 { 0, 0 }
2180};
2181
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2182/* Return the name for membar value VALUE or NULL if not found. */
2183
2184const char *
2185sparc_decode_membar (value)
2186 int value;
2187{
2188 return lookup_value (membar_table, value);
2189}
2190
2191/* Handle prefetch args. */
2192
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2193static const arg prefetch_table[] =
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2194{
2195 { 0, "#n_reads" },
2196 { 1, "#one_read" },
2197 { 2, "#n_writes" },
2198 { 3, "#one_write" },
2199 { 4, "#page" },
2200 { 16, "#invalidate" },
2201 { 0, 0 }
2202};
2203
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2204/* Return the name for prefetch value VALUE or NULL if not found. */
2205
2206const char *
2207sparc_decode_prefetch (value)
2208 int value;
2209{
2210 return lookup_value (prefetch_table, value);
2211}
2212
2213/* Handle sparclet coprocessor registers. */
2214
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2215static const arg sparclet_cpreg_table[] =
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2216{
2217 { 0, "%ccsr" },
2218 { 1, "%ccfr" },
2219 { 2, "%cccrcr" },
2220 { 3, "%ccpr" },
2221 { 4, "%ccsr2" },
2222 { 5, "%cccrr" },
2223 { 6, "%ccrstr" },
2224 { 0, 0 }
2225};
2226
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2227/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2228
2229const char *
2230sparc_decode_sparclet_cpreg (value)
2231 int value;
2232{
2233 return lookup_value (sparclet_cpreg_table, value);
2234}
2235
2236#undef MASK_V9
2237
2238/* Bitmask of v9 architectures. */
2239#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2240 | (1 << SPARC_OPCODE_ARCH_V9A) \
2241 | (1 << SPARC_OPCODE_ARCH_V9B))
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2242/* 1 if INSN is for v9 only. */
2243#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2244/* 1 if INSN is for v9. */
2245#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2246
2247/* The sorted opcode table. */
2248static const struct sparc_opcode **sorted_opcodes;
2249
2250/* For faster lookup, after insns are sorted they are hashed. */
2251/* ??? I think there is room for even more improvement. */
2252
2253#define HASH_SIZE 256
2254/* It is important that we only look at insn code bits as that is how the
2255 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
2256 of the main types (0,1,2,3). */
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2257static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2258#define HASH_INSN(INSN) \
2259 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
2260struct opcode_hash {
2261 struct opcode_hash *next;
2262 const struct sparc_opcode *opcode;
2263};
2264static struct opcode_hash *opcode_hash_table[HASH_SIZE];
2265
2266static void build_hash_table
2267 PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
2268static int is_delayed_branch PARAMS ((unsigned long));
2269static int compare_opcodes PARAMS ((const void *, const void *));
2270static int compute_arch_mask PARAMS ((unsigned long));
2271
2272/* Sign-extend a value which is N bits long. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2273#define SEX(value, bits) \
2274 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2275 >> ((8 * sizeof (int)) - bits) )
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2276
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2277static const char * const reg_names[] =
ths5fafdf22007-09-16 21:08:06 +0000[diff] [blame]2278{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2279 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2280 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2281 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2282 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2283 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2284 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2285 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
ths5fafdf22007-09-16 21:08:06 +0000[diff] [blame]2286 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
2287 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2288 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
2289 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
2290/* psr, wim, tbr, fpsr, cpsr are v8 only. */
2291 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2292};
2293
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2294#define freg_names (&reg_names[4 * 8])
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2295
2296/* These are ordered according to there register number in
2297 rdpr and wrpr insns. */
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2298static const char * const v9_priv_reg_names[] =
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2299{
2300 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2301 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2302 "wstate", "fq"
2303 /* "ver" - special cased */
2304};
2305
2306/* These are ordered according to there register number in
2307 rd and wr insns (-16). */
blueswir1d88bbf92007-06-01 16:59:44 +0000[diff] [blame]2308static const char * const v9a_asr_reg_names[] =
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2309{
2310 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2311 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
2312};
2313
2314/* Macros used to extract instruction fields. Not all fields have
2315 macros defined here, only those which are actually used. */
2316
2317#define X_RD(i) (((i) >> 25) & 0x1f)
2318#define X_RS1(i) (((i) >> 14) & 0x1f)
2319#define X_LDST_I(i) (((i) >> 13) & 1)
2320#define X_ASI(i) (((i) >> 5) & 0xff)
2321#define X_RS2(i) (((i) >> 0) & 0x1f)
2322#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2323#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
2324#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
2325#define X_IMM22(i) X_DISP22 (i)
2326#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
2327
2328/* These are for v9. */
2329#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2330#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
2331#define X_MEMBAR(i) ((i) & 0x7f)
2332
2333/* Here is the union which was used to extract instruction fields
2334 before the shift and mask macros were written.
2335
2336 union sparc_insn
2337 {
2338 unsigned long int code;
2339 struct
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2340 {
2341 unsigned int anop:2;
2342 #define op ldst.anop
2343 unsigned int anrd:5;
2344 #define rd ldst.anrd
2345 unsigned int op3:6;
2346 unsigned int anrs1:5;
2347 #define rs1 ldst.anrs1
2348 unsigned int i:1;
2349 unsigned int anasi:8;
2350 #define asi ldst.anasi
2351 unsigned int anrs2:5;
2352 #define rs2 ldst.anrs2
2353 #define shcnt rs2
2354 } ldst;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2355 struct
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2356 {
2357 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
2358 unsigned int IMM13:13;
2359 #define imm13 IMM13.IMM13
2360 } IMM13;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2361 struct
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2362 {
2363 unsigned int anop:2;
2364 unsigned int a:1;
2365 unsigned int cond:4;
2366 unsigned int op2:3;
2367 unsigned int DISP22:22;
2368 #define disp22 branch.DISP22
2369 #define imm22 disp22
2370 } branch;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2371 struct
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2372 {
2373 unsigned int anop:2;
2374 unsigned int a:1;
2375 unsigned int z:1;
2376 unsigned int rcond:3;
2377 unsigned int op2:3;
2378 unsigned int DISP16HI:2;
2379 unsigned int p:1;
2380 unsigned int _rs1:5;
2381 unsigned int DISP16LO:14;
2382 } branch16;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2383 struct
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2384 {
2385 unsigned int anop:2;
2386 unsigned int adisp30:30;
2387 #define disp30 call.adisp30
2388 } call;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2389 };
2390
2391 */
2392
2393/* Nonzero if INSN is the opcode for a delayed branch. */
2394static int
2395is_delayed_branch (insn)
2396 unsigned long insn;
2397{
2398 struct opcode_hash *op;
2399
2400 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2401 {
2402 const struct sparc_opcode *opcode = op->opcode;
2403 if ((opcode->match & insn) == opcode->match
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2404 && (opcode->lose & insn) == 0)
2405 return (opcode->flags & F_DELAYED);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2406 }
2407 return 0;
2408}
2409
2410/* extern void qsort (); */
2411
2412/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
2413 to compare_opcodes. */
2414static unsigned int current_arch_mask;
2415
2416/* Print one instruction from MEMADDR on INFO->STREAM.
2417
2418 We suffix the instruction with a comment that gives the absolute
2419 address involved, as well as its symbolic form, if the instruction
2420 is preceded by a findable `sethi' and it either adds an immediate
2421 displacement to that register, or it is an `add' or `or' instruction
2422 on that register. */
2423
2424int
2425print_insn_sparc (memaddr, info)
2426 bfd_vma memaddr;
2427 disassemble_info *info;
2428{
2429 FILE *stream = info->stream;
2430 bfd_byte buffer[4];
2431 unsigned long insn;
2432 register struct opcode_hash *op;
2433 /* Nonzero of opcode table has been initialized. */
2434 static int opcodes_initialized = 0;
2435 /* bfd mach number of last call. */
2436 static unsigned long current_mach = 0;
2437 bfd_vma (*getword) PARAMS ((const unsigned char *));
2438
2439 if (!opcodes_initialized
2440 || info->mach != current_mach)
2441 {
2442 int i;
2443
2444 current_arch_mask = compute_arch_mask (info->mach);
2445
2446 if (!opcodes_initialized)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2447 sorted_opcodes = (const struct sparc_opcode **)
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2448 malloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
2449 /* Reset the sorted table so we can resort it. */
2450 for (i = 0; i < sparc_num_opcodes; ++i)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2451 sorted_opcodes[i] = &sparc_opcodes[i];
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2452 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2453 sizeof (sorted_opcodes[0]), compare_opcodes);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2454
2455 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
2456 current_mach = info->mach;
2457 opcodes_initialized = 1;
2458 }
2459
2460 {
2461 int status =
2462 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
2463 if (status != 0)
2464 {
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2465 (*info->memory_error_func) (status, memaddr, info);
2466 return -1;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2467 }
2468 }
2469
2470 /* On SPARClite variants such as DANlite (sparc86x), instructions
2471 are always big-endian even when the machine is in little-endian mode. */
2472 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
2473 getword = bfd_getb32;
2474 else
2475 getword = bfd_getl32;
2476
2477 insn = getword (buffer);
2478
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2479 info->insn_info_valid = 1; /* We do return this info */
2480 info->insn_type = dis_nonbranch; /* Assume non branch insn */
2481 info->branch_delay_insns = 0; /* Assume no delay */
2482 info->target = 0; /* Assume no target known */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2483
2484 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2485 {
2486 const struct sparc_opcode *opcode = op->opcode;
2487
2488 /* If the insn isn't supported by the current architecture, skip it. */
2489 if (! (opcode->architecture & current_arch_mask))
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2490 continue;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2491
2492 if ((opcode->match & insn) == opcode->match
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2493 && (opcode->lose & insn) == 0)
2494 {
2495 /* Nonzero means that we have found an instruction which has
2496 the effect of adding or or'ing the imm13 field to rs1. */
2497 int imm_added_to_rs1 = 0;
2498 int imm_ored_to_rs1 = 0;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2499
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2500 /* Nonzero means that we have found a plus sign in the args
2501 field of the opcode table. */
2502 int found_plus = 0;
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2503
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2504 /* Nonzero means we have an annulled branch. */
2505 int is_annulled = 0;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2506
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2507 /* Do we have an `add' or `or' instruction combining an
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2508 immediate with rs1? */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2509 if (opcode->match == 0x80102000) /* or */
2510 imm_ored_to_rs1 = 1;
2511 if (opcode->match == 0x80002000) /* add */
2512 imm_added_to_rs1 = 1;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2513
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2514 if (X_RS1 (insn) != X_RD (insn)
2515 && strchr (opcode->args, 'r') != 0)
2516 /* Can't do simple format if source and dest are different. */
2517 continue;
2518 if (X_RS2 (insn) != X_RD (insn)
2519 && strchr (opcode->args, 'O') != 0)
2520 /* Can't do simple format if source and dest are different. */
2521 continue;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2522
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2523 (*info->fprintf_func) (stream, opcode->name);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2524
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2525 {
2526 register const char *s;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2527
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2528 if (opcode->args[0] != ',')
2529 (*info->fprintf_func) (stream, " ");
2530 for (s = opcode->args; *s != '\0'; ++s)
2531 {
2532 while (*s == ',')
2533 {
2534 (*info->fprintf_func) (stream, ",");
2535 ++s;
2536 switch (*s) {
2537 case 'a':
2538 (*info->fprintf_func) (stream, "a");
2539 is_annulled = 1;
2540 ++s;
2541 continue;
2542 case 'N':
2543 (*info->fprintf_func) (stream, "pn");
2544 ++s;
2545 continue;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2546
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2547 case 'T':
2548 (*info->fprintf_func) (stream, "pt");
2549 ++s;
2550 continue;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2551
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2552 default:
2553 break;
2554 } /* switch on arg */
2555 } /* while there are comma started args */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2556
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2557 (*info->fprintf_func) (stream, " ");
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2558
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2559 switch (*s)
2560 {
2561 case '+':
2562 found_plus = 1;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2563
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2564 /* note fall-through */
2565 default:
2566 (*info->fprintf_func) (stream, "%c", *s);
2567 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2568
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2569 case '#':
2570 (*info->fprintf_func) (stream, "0");
2571 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2572
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2573#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
2574 case '1':
2575 case 'r':
2576 reg (X_RS1 (insn));
2577 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2578
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2579 case '2':
2580 case 'O':
2581 reg (X_RS2 (insn));
2582 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2583
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2584 case 'd':
2585 reg (X_RD (insn));
2586 break;
2587#undef reg
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2588
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2589#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
2590#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
2591 case 'e':
2592 freg (X_RS1 (insn));
2593 break;
2594 case 'v': /* double/even */
2595 case 'V': /* quad/multiple of 4 */
2596 fregx (X_RS1 (insn));
2597 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2598
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2599 case 'f':
2600 freg (X_RS2 (insn));
2601 break;
2602 case 'B': /* double/even */
2603 case 'R': /* quad/multiple of 4 */
2604 fregx (X_RS2 (insn));
2605 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2606
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2607 case 'g':
2608 freg (X_RD (insn));
2609 break;
2610 case 'H': /* double/even */
2611 case 'J': /* quad/multiple of 4 */
2612 fregx (X_RD (insn));
2613 break;
2614#undef freg
2615#undef fregx
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2616
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2617#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
2618 case 'b':
2619 creg (X_RS1 (insn));
2620 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2621
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2622 case 'c':
2623 creg (X_RS2 (insn));
2624 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2625
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2626 case 'D':
2627 creg (X_RD (insn));
2628 break;
2629#undef creg
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2630
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2631 case 'h':
2632 (*info->fprintf_func) (stream, "%%hi(%#x)",
2633 ((unsigned) 0xFFFFFFFF
2634 & ((int) X_IMM22 (insn) << 10)));
2635 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2636
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2637 case 'i': /* 13 bit immediate */
2638 case 'I': /* 11 bit immediate */
2639 case 'j': /* 10 bit immediate */
2640 {
2641 int imm;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2642
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2643 if (*s == 'i')
2644 imm = X_SIMM (insn, 13);
2645 else if (*s == 'I')
2646 imm = X_SIMM (insn, 11);
2647 else
2648 imm = X_SIMM (insn, 10);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2649
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2650 /* Check to see whether we have a 1+i, and take
2651 note of that fact.
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2652
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2653 Note: because of the way we sort the table,
2654 we will be matching 1+i rather than i+1,
2655 so it is OK to assume that i is after +,
2656 not before it. */
2657 if (found_plus)
2658 imm_added_to_rs1 = 1;
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2659
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2660 if (imm <= 9)
2661 (*info->fprintf_func) (stream, "%d", imm);
2662 else
2663 (*info->fprintf_func) (stream, "%#x", imm);
2664 }
2665 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2666
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2667 case 'X': /* 5 bit unsigned immediate */
2668 case 'Y': /* 6 bit unsigned immediate */
2669 {
2670 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2671
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2672 if (imm <= 9)
2673 (info->fprintf_func) (stream, "%d", imm);
2674 else
2675 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
2676 }
2677 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2678
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2679 case '3':
2680 (info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
2681 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2682
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2683 case 'K':
2684 {
2685 int mask = X_MEMBAR (insn);
2686 int bit = 0x40, printed_one = 0;
2687 const char *name;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2688
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2689 if (mask == 0)
2690 (info->fprintf_func) (stream, "0");
2691 else
2692 while (bit)
2693 {
2694 if (mask & bit)
2695 {
2696 if (printed_one)
2697 (info->fprintf_func) (stream, "|");
2698 name = sparc_decode_membar (bit);
2699 (info->fprintf_func) (stream, "%s", name);
2700 printed_one = 1;
2701 }
2702 bit >>= 1;
2703 }
2704 break;
2705 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2706
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2707 case 'k':
2708 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
2709 (*info->print_address_func) (info->target, info);
2710 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2711
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2712 case 'G':
2713 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
2714 (*info->print_address_func) (info->target, info);
2715 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2716
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2717 case '6':
2718 case '7':
2719 case '8':
2720 case '9':
2721 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
2722 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2723
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2724 case 'z':
2725 (*info->fprintf_func) (stream, "%%icc");
2726 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2727
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2728 case 'Z':
2729 (*info->fprintf_func) (stream, "%%xcc");
2730 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2731
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2732 case 'E':
2733 (*info->fprintf_func) (stream, "%%ccr");
2734 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2735
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2736 case 's':
2737 (*info->fprintf_func) (stream, "%%fprs");
2738 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2739
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2740 case 'o':
2741 (*info->fprintf_func) (stream, "%%asi");
2742 break;
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2743
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2744 case 'W':
2745 (*info->fprintf_func) (stream, "%%tick");
2746 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2747
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2748 case 'P':
2749 (*info->fprintf_func) (stream, "%%pc");
2750 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2751
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2752 case '?':
2753 if (X_RS1 (insn) == 31)
2754 (*info->fprintf_func) (stream, "%%ver");
2755 else if ((unsigned) X_RS1 (insn) < 16)
2756 (*info->fprintf_func) (stream, "%%%s",
2757 v9_priv_reg_names[X_RS1 (insn)]);
2758 else
2759 (*info->fprintf_func) (stream, "%%reserved");
2760 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2761
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2762 case '!':
2763 if ((unsigned) X_RD (insn) < 15)
2764 (*info->fprintf_func) (stream, "%%%s",
2765 v9_priv_reg_names[X_RD (insn)]);
2766 else
2767 (*info->fprintf_func) (stream, "%%reserved");
2768 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2769
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2770 case '/':
2771 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
2772 (*info->fprintf_func) (stream, "%%reserved");
2773 else
2774 (*info->fprintf_func) (stream, "%%%s",
2775 v9a_asr_reg_names[X_RS1 (insn)-16]);
2776 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2777
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2778 case '_':
2779 if (X_RD (insn) < 16 || X_RD (insn) > 25)
2780 (*info->fprintf_func) (stream, "%%reserved");
2781 else
2782 (*info->fprintf_func) (stream, "%%%s",
2783 v9a_asr_reg_names[X_RD (insn)-16]);
2784 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2785
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2786 case '*':
2787 {
2788 const char *name = sparc_decode_prefetch (X_RD (insn));
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2789
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2790 if (name)
2791 (*info->fprintf_func) (stream, "%s", name);
2792 else
2793 (*info->fprintf_func) (stream, "%d", X_RD (insn));
2794 break;
2795 }
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2796
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2797 case 'M':
2798 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
2799 break;
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2800
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2801 case 'm':
2802 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
2803 break;
ths3b46e622007-09-17 08:09:54 +0000[diff] [blame]2804
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2805 case 'L':
2806 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
2807 (*info->print_address_func) (info->target, info);
2808 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2809
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2810 case 'n':
2811 (*info->fprintf_func)
2812 (stream, "%#x", SEX (X_DISP22 (insn), 22));
2813 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2814
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2815 case 'l':
2816 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
2817 (*info->print_address_func) (info->target, info);
2818 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2819
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2820 case 'A':
2821 {
2822 const char *name;
bellard1983a392005-10-30 15:45:19 +0000[diff] [blame]2823
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2824 if ((info->mach == bfd_mach_sparc_v8plusa) ||
bellard725cb902006-07-18 21:12:17 +0000[diff] [blame]2825 ((info->mach >= bfd_mach_sparc_v9) &&
2826 (info->mach <= bfd_mach_sparc_v9b)))
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2827 name = sparc_decode_asi_v9 (X_ASI (insn));
2828 else
2829 name = sparc_decode_asi_v8 (X_ASI (insn));
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2830
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2831 if (name)
2832 (*info->fprintf_func) (stream, "%s", name);
2833 else
2834 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
2835 break;
2836 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2837
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2838 case 'C':
2839 (*info->fprintf_func) (stream, "%%csr");
2840 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2841
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2842 case 'F':
2843 (*info->fprintf_func) (stream, "%%fsr");
2844 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2845
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2846 case 'p':
2847 (*info->fprintf_func) (stream, "%%psr");
2848 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2849
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2850 case 'q':
2851 (*info->fprintf_func) (stream, "%%fq");
2852 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2853
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2854 case 'Q':
2855 (*info->fprintf_func) (stream, "%%cq");
2856 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2857
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2858 case 't':
2859 (*info->fprintf_func) (stream, "%%tbr");
2860 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2861
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2862 case 'w':
2863 (*info->fprintf_func) (stream, "%%wim");
2864 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2865
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2866 case 'x':
2867 (*info->fprintf_func) (stream, "%d",
2868 ((X_LDST_I (insn) << 8)
2869 + X_ASI (insn)));
2870 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2871
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2872 case 'y':
2873 (*info->fprintf_func) (stream, "%%y");
2874 break;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2875
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2876 case 'u':
2877 case 'U':
2878 {
2879 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
2880 const char *name = sparc_decode_sparclet_cpreg (val);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2881
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2882 if (name)
2883 (*info->fprintf_func) (stream, "%s", name);
2884 else
2885 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
2886 break;
2887 }
2888 }
2889 }
2890 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2891
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2892 /* If we are adding or or'ing something to rs1, then
2893 check to see whether the previous instruction was
2894 a sethi to the same register as in the sethi.
2895 If so, attempt to print the result of the add or
2896 or (in this context add and or do the same thing)
2897 and its symbolic value. */
2898 if (imm_ored_to_rs1 || imm_added_to_rs1)
2899 {
2900 unsigned long prev_insn;
2901 int errcode;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2902
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2903 errcode =
2904 (*info->read_memory_func)
2905 (memaddr - 4, buffer, sizeof (buffer), info);
2906 prev_insn = getword (buffer);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2907
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2908 if (errcode == 0)
2909 {
2910 /* If it is a delayed branch, we need to look at the
2911 instruction before the delayed branch. This handles
2912 sequences such as
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2913
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2914 sethi %o1, %hi(_foo), %o1
2915 call _printf
2916 or %o1, %lo(_foo), %o1
2917 */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2918
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2919 if (is_delayed_branch (prev_insn))
2920 {
2921 errcode = (*info->read_memory_func)
2922 (memaddr - 8, buffer, sizeof (buffer), info);
2923 prev_insn = getword (buffer);
2924 }
2925 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2926
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2927 /* If there was a problem reading memory, then assume
2928 the previous instruction was not sethi. */
2929 if (errcode == 0)
2930 {
2931 /* Is it sethi to the same register? */
2932 if ((prev_insn & 0xc1c00000) == 0x01000000
2933 && X_RD (prev_insn) == X_RS1 (insn))
2934 {
2935 (*info->fprintf_func) (stream, "\t! ");
2936 info->target =
2937 ((unsigned) 0xFFFFFFFF
2938 & ((int) X_IMM22 (prev_insn) << 10));
2939 if (imm_added_to_rs1)
2940 info->target += X_SIMM (insn, 13);
2941 else
2942 info->target |= X_SIMM (insn, 13);
2943 (*info->print_address_func) (info->target, info);
2944 info->insn_type = dis_dref;
2945 info->data_size = 4; /* FIXME!!! */
2946 }
2947 }
2948 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2949
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2950 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
2951 {
2952 /* FIXME -- check is_annulled flag */
2953 if (opcode->flags & F_UNBR)
2954 info->insn_type = dis_branch;
2955 if (opcode->flags & F_CONDBR)
2956 info->insn_type = dis_condbranch;
2957 if (opcode->flags & F_JSR)
2958 info->insn_type = dis_jsr;
2959 if (opcode->flags & F_DELAYED)
2960 info->branch_delay_insns = 1;
2961 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2962
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2963 return sizeof (buffer);
2964 }
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2965 }
2966
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2967 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2968 (*info->fprintf_func) (stream, _("unknown"));
2969 return sizeof (buffer);
2970}
2971
2972/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
2973
2974static int
2975compute_arch_mask (mach)
2976 unsigned long mach;
2977{
2978 switch (mach)
2979 {
2980 case 0 :
2981 case bfd_mach_sparc :
2982 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
2983 case bfd_mach_sparc_sparclet :
2984 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
2985 case bfd_mach_sparc_sparclite :
2986 case bfd_mach_sparc_sparclite_le :
2987 /* sparclites insns are recognized by default (because that's how
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2988 they've always been treated, for better or worse). Kludge this by
2989 indicating generic v8 is also selected. */
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2990 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]2991 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]2992 case bfd_mach_sparc_v8plus :
2993 case bfd_mach_sparc_v9 :
2994 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2995 case bfd_mach_sparc_v8plusa :
2996 case bfd_mach_sparc_v9a :
2997 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
2998 case bfd_mach_sparc_v8plusb :
2999 case bfd_mach_sparc_v9b :
3000 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
3001 }
3002 abort ();
3003}
3004
3005/* Compare opcodes A and B. */
3006
3007static int
3008compare_opcodes (const void *a, const void *b)
3009{
3010 struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
3011 struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
3012 unsigned long int match0 = op0->match, match1 = op1->match;
3013 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
3014 register unsigned int i;
3015
3016 /* If one (and only one) insn isn't supported by the current architecture,
3017 prefer the one that is. If neither are supported, but they're both for
3018 the same architecture, continue processing. Otherwise (both unsupported
3019 and for different architectures), prefer lower numbered arch's (fudged
3020 by comparing the bitmasks). */
3021 if (op0->architecture & current_arch_mask)
3022 {
3023 if (! (op1->architecture & current_arch_mask))
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3024 return -1;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3025 }
3026 else
3027 {
3028 if (op1->architecture & current_arch_mask)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3029 return 1;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3030 else if (op0->architecture != op1->architecture)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3031 return op0->architecture - op1->architecture;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3032 }
3033
3034 /* If a bit is set in both match and lose, there is something
3035 wrong with the opcode table. */
3036 if (match0 & lose0)
3037 {
3038 fprintf
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3039 (stderr,
3040 /* xgettext:c-format */
3041 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
3042 op0->name, match0, lose0);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3043 op0->lose &= ~op0->match;
3044 lose0 = op0->lose;
3045 }
3046
3047 if (match1 & lose1)
3048 {
3049 fprintf
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3050 (stderr,
3051 /* xgettext:c-format */
3052 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
3053 op1->name, match1, lose1);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3054 op1->lose &= ~op1->match;
3055 lose1 = op1->lose;
3056 }
3057
3058 /* Because the bits that are variable in one opcode are constant in
3059 another, it is important to order the opcodes in the right order. */
3060 for (i = 0; i < 32; ++i)
3061 {
3062 unsigned long int x = 1 << i;
3063 int x0 = (match0 & x) != 0;
3064 int x1 = (match1 & x) != 0;
3065
3066 if (x0 != x1)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3067 return x1 - x0;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3068 }
3069
3070 for (i = 0; i < 32; ++i)
3071 {
3072 unsigned long int x = 1 << i;
3073 int x0 = (lose0 & x) != 0;
3074 int x1 = (lose1 & x) != 0;
3075
3076 if (x0 != x1)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3077 return x1 - x0;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3078 }
3079
3080 /* They are functionally equal. So as long as the opcode table is
3081 valid, we can put whichever one first we want, on aesthetic grounds. */
3082
3083 /* Our first aesthetic ground is that aliases defer to real insns. */
3084 {
3085 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
3086 if (alias_diff != 0)
3087 /* Put the one that isn't an alias first. */
3088 return alias_diff;
3089 }
3090
3091 /* Except for aliases, two "identical" instructions had
3092 better have the same opcode. This is a sanity check on the table. */
3093 i = strcmp (op0->name, op1->name);
3094 if (i)
3095 {
3096 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3097 return i;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3098 else
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3099 fprintf (stderr,
3100 /* xgettext:c-format */
3101 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
3102 op0->name, op1->name);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3103 }
3104
3105 /* Fewer arguments are preferred. */
3106 {
3107 int length_diff = strlen (op0->args) - strlen (op1->args);
3108 if (length_diff != 0)
3109 /* Put the one with fewer arguments first. */
3110 return length_diff;
3111 }
3112
3113 /* Put 1+i before i+1. */
3114 {
3115 char *p0 = (char *) strchr (op0->args, '+');
3116 char *p1 = (char *) strchr (op1->args, '+');
3117
3118 if (p0 && p1)
3119 {
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3120 /* There is a plus in both operands. Note that a plus
3121 sign cannot be the first character in args,
3122 so the following [-1]'s are valid. */
3123 if (p0[-1] == 'i' && p1[1] == 'i')
3124 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
3125 return 1;
3126 if (p0[1] == 'i' && p1[-1] == 'i')
3127 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
3128 return -1;
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3129 }
3130 }
3131
3132 /* Put 1,i before i,1. */
3133 {
3134 int i0 = strncmp (op0->args, "i,1", 3) == 0;
3135 int i1 = strncmp (op1->args, "i,1", 3) == 0;
3136
3137 if (i0 ^ i1)
3138 return i0 - i1;
3139 }
3140
3141 /* They are, as far as we can tell, identical.
3142 Since qsort may have rearranged the table partially, there is
3143 no way to tell which one was first in the opcode table as
3144 written, so just say there are equal. */
3145 /* ??? This is no longer true now that we sort a vector of pointers,
3146 not the table itself. */
3147 return 0;
3148}
3149
3150/* Build a hash table from the opcode table.
3151 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
3152
3153static void
3154build_hash_table (opcode_table, hash_table, num_opcodes)
3155 const struct sparc_opcode **opcode_table;
3156 struct opcode_hash **hash_table;
3157 int num_opcodes;
3158{
3159 register int i;
3160 int hash_count[HASH_SIZE];
3161 static struct opcode_hash *hash_buf = NULL;
3162
3163 /* Start at the end of the table and work backwards so that each
3164 chain is sorted. */
3165
3166 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
3167 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
3168 if (hash_buf != NULL)
3169 free (hash_buf);
3170 hash_buf = (struct opcode_hash *) malloc (sizeof (struct opcode_hash) * num_opcodes);
3171 for (i = num_opcodes - 1; i >= 0; --i)
3172 {
3173 register int hash = HASH_INSN (opcode_table[i]->match);
3174 register struct opcode_hash *h = &hash_buf[i];
3175 h->next = hash_table[hash];
3176 h->opcode = opcode_table[i];
3177 hash_table[hash] = h;
3178 ++hash_count[hash];
3179 }
3180
3181#if 0 /* for debugging */
3182 {
3183 int min_count = num_opcodes, max_count = 0;
3184 int total;
3185
3186 for (i = 0; i < HASH_SIZE; ++i)
3187 {
3188 if (hash_count[i] < min_count)
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3189 min_count = hash_count[i];
3190 if (hash_count[i] > max_count)
3191 max_count = hash_count[i];
3192 total += hash_count[i];
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3193 }
3194
3195 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
blueswir1f930d072007-10-06 11:28:21 +0000[diff] [blame]3196 min_count, max_count, (double) total / HASH_SIZE);
bellardaa0aa4f2003-06-09 15:23:31 +0000[diff] [blame]3197 }
3198#endif
3199}