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bellardb92e5a22003-08-08 23:58:05 +00001/*
2 * Software MMU support
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardb92e5a22003-08-08 23:58:05 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardb92e5a22003-08-08 23:58:05 +000018 */
19#if DATA_SIZE == 8
20#define SUFFIX q
bellard61382a52003-10-27 21:22:23 +000021#define USUFFIX q
bellardb92e5a22003-08-08 23:58:05 +000022#define DATA_TYPE uint64_t
23#elif DATA_SIZE == 4
24#define SUFFIX l
bellard61382a52003-10-27 21:22:23 +000025#define USUFFIX l
bellardb92e5a22003-08-08 23:58:05 +000026#define DATA_TYPE uint32_t
27#elif DATA_SIZE == 2
28#define SUFFIX w
bellard61382a52003-10-27 21:22:23 +000029#define USUFFIX uw
bellardb92e5a22003-08-08 23:58:05 +000030#define DATA_TYPE uint16_t
31#define DATA_STYPE int16_t
32#elif DATA_SIZE == 1
33#define SUFFIX b
bellard61382a52003-10-27 21:22:23 +000034#define USUFFIX ub
bellardb92e5a22003-08-08 23:58:05 +000035#define DATA_TYPE uint8_t
36#define DATA_STYPE int8_t
37#else
38#error unsupported data size
39#endif
40
j_mayer6ebbf392007-10-14 07:07:08 +000041#if ACCESS_TYPE < (NB_MMU_MODES)
bellard61382a52003-10-27 21:22:23 +000042
j_mayer6ebbf392007-10-14 07:07:08 +000043#define CPU_MMU_INDEX ACCESS_TYPE
bellard61382a52003-10-27 21:22:23 +000044#define MMUSUFFIX _mmu
45
j_mayer6ebbf392007-10-14 07:07:08 +000046#elif ACCESS_TYPE == (NB_MMU_MODES)
bellard61382a52003-10-27 21:22:23 +000047
j_mayer6ebbf392007-10-14 07:07:08 +000048#define CPU_MMU_INDEX (cpu_mmu_index(env))
bellard61382a52003-10-27 21:22:23 +000049#define MMUSUFFIX _mmu
50
j_mayer6ebbf392007-10-14 07:07:08 +000051#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
bellard61382a52003-10-27 21:22:23 +000052
j_mayer6ebbf392007-10-14 07:07:08 +000053#define CPU_MMU_INDEX (cpu_mmu_index(env))
bellard61382a52003-10-27 21:22:23 +000054#define MMUSUFFIX _cmmu
55
bellardb92e5a22003-08-08 23:58:05 +000056#else
bellard61382a52003-10-27 21:22:23 +000057#error invalid ACCESS_TYPE
bellardb92e5a22003-08-08 23:58:05 +000058#endif
59
60#if DATA_SIZE == 8
61#define RES_TYPE uint64_t
62#else
63#define RES_TYPE int
64#endif
65
j_mayer6ebbf392007-10-14 07:07:08 +000066#if ACCESS_TYPE == (NB_MMU_MODES + 1)
bellard84b7b8e2005-11-28 21:19:04 +000067#define ADDR_READ addr_code
68#else
69#define ADDR_READ addr_read
70#endif
bellardb92e5a22003-08-08 23:58:05 +000071
bellardc27004e2005-01-03 23:35:10 +000072#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
j_mayer6ebbf392007-10-14 07:07:08 +000073 (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
bellarde16c53f2004-01-04 18:15:29 +000074
bellardc27004e2005-01-03 23:35:10 +000075static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
bellarde16c53f2004-01-04 18:15:29 +000076{
77 int res;
78
79 asm volatile ("movl %1, %%edx\n"
80 "movl %1, %%eax\n"
81 "shrl %3, %%edx\n"
82 "andl %4, %%eax\n"
83 "andl %2, %%edx\n"
84 "leal %5(%%edx, %%ebp), %%edx\n"
85 "cmpl (%%edx), %%eax\n"
86 "movl %1, %%eax\n"
87 "je 1f\n"
bellardd6564692008-01-31 09:22:27 +000088 "movl %6, %%edx\n"
bellarde16c53f2004-01-04 18:15:29 +000089 "call %7\n"
bellarde16c53f2004-01-04 18:15:29 +000090 "movl %%eax, %0\n"
91 "jmp 2f\n"
92 "1:\n"
bellard84b7b8e2005-11-28 21:19:04 +000093 "addl 12(%%edx), %%eax\n"
bellarde16c53f2004-01-04 18:15:29 +000094#if DATA_SIZE == 1
95 "movzbl (%%eax), %0\n"
96#elif DATA_SIZE == 2
97 "movzwl (%%eax), %0\n"
98#elif DATA_SIZE == 4
99 "movl (%%eax), %0\n"
100#else
101#error unsupported size
102#endif
103 "2:\n"
104 : "=r" (res)
ths5fafdf22007-09-16 21:08:06 +0000105 : "r" (ptr),
106 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
107 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
bellarde16c53f2004-01-04 18:15:29 +0000108 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
j_mayer6ebbf392007-10-14 07:07:08 +0000109 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
110 "i" (CPU_MMU_INDEX),
bellarde16c53f2004-01-04 18:15:29 +0000111 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
112 : "%eax", "%ecx", "%edx", "memory", "cc");
113 return res;
114}
115
116#if DATA_SIZE <= 2
bellardc27004e2005-01-03 23:35:10 +0000117static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
bellarde16c53f2004-01-04 18:15:29 +0000118{
119 int res;
120
121 asm volatile ("movl %1, %%edx\n"
122 "movl %1, %%eax\n"
123 "shrl %3, %%edx\n"
124 "andl %4, %%eax\n"
125 "andl %2, %%edx\n"
126 "leal %5(%%edx, %%ebp), %%edx\n"
127 "cmpl (%%edx), %%eax\n"
128 "movl %1, %%eax\n"
129 "je 1f\n"
bellardd6564692008-01-31 09:22:27 +0000130 "movl %6, %%edx\n"
bellarde16c53f2004-01-04 18:15:29 +0000131 "call %7\n"
bellarde16c53f2004-01-04 18:15:29 +0000132#if DATA_SIZE == 1
133 "movsbl %%al, %0\n"
134#elif DATA_SIZE == 2
135 "movswl %%ax, %0\n"
136#else
137#error unsupported size
138#endif
139 "jmp 2f\n"
140 "1:\n"
bellard84b7b8e2005-11-28 21:19:04 +0000141 "addl 12(%%edx), %%eax\n"
bellarde16c53f2004-01-04 18:15:29 +0000142#if DATA_SIZE == 1
143 "movsbl (%%eax), %0\n"
144#elif DATA_SIZE == 2
145 "movswl (%%eax), %0\n"
146#else
147#error unsupported size
148#endif
149 "2:\n"
150 : "=r" (res)
ths5fafdf22007-09-16 21:08:06 +0000151 : "r" (ptr),
152 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
153 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
bellarde16c53f2004-01-04 18:15:29 +0000154 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
j_mayer6ebbf392007-10-14 07:07:08 +0000155 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
156 "i" (CPU_MMU_INDEX),
bellarde16c53f2004-01-04 18:15:29 +0000157 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
158 : "%eax", "%ecx", "%edx", "memory", "cc");
159 return res;
160}
161#endif
162
bellardc27004e2005-01-03 23:35:10 +0000163static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
bellarde16c53f2004-01-04 18:15:29 +0000164{
165 asm volatile ("movl %0, %%edx\n"
166 "movl %0, %%eax\n"
167 "shrl %3, %%edx\n"
168 "andl %4, %%eax\n"
169 "andl %2, %%edx\n"
170 "leal %5(%%edx, %%ebp), %%edx\n"
171 "cmpl (%%edx), %%eax\n"
172 "movl %0, %%eax\n"
173 "je 1f\n"
174#if DATA_SIZE == 1
175 "movzbl %b1, %%edx\n"
176#elif DATA_SIZE == 2
177 "movzwl %w1, %%edx\n"
178#elif DATA_SIZE == 4
179 "movl %1, %%edx\n"
180#else
181#error unsupported size
182#endif
bellardd6564692008-01-31 09:22:27 +0000183 "movl %6, %%ecx\n"
bellarde16c53f2004-01-04 18:15:29 +0000184 "call %7\n"
bellarde16c53f2004-01-04 18:15:29 +0000185 "jmp 2f\n"
186 "1:\n"
bellard84b7b8e2005-11-28 21:19:04 +0000187 "addl 8(%%edx), %%eax\n"
bellarde16c53f2004-01-04 18:15:29 +0000188#if DATA_SIZE == 1
189 "movb %b1, (%%eax)\n"
190#elif DATA_SIZE == 2
191 "movw %w1, (%%eax)\n"
192#elif DATA_SIZE == 4
193 "movl %1, (%%eax)\n"
194#else
195#error unsupported size
196#endif
197 "2:\n"
ths5fafdf22007-09-16 21:08:06 +0000198 :
199 : "r" (ptr),
bellardf220f4e2008-01-21 15:07:18 +0000200#if DATA_SIZE == 1
201 "q" (v),
202#else
ths5fafdf22007-09-16 21:08:06 +0000203 "r" (v),
bellardf220f4e2008-01-21 15:07:18 +0000204#endif
ths5fafdf22007-09-16 21:08:06 +0000205 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
206 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
bellarde16c53f2004-01-04 18:15:29 +0000207 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
j_mayer6ebbf392007-10-14 07:07:08 +0000208 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
209 "i" (CPU_MMU_INDEX),
bellarde16c53f2004-01-04 18:15:29 +0000210 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
211 : "%eax", "%ecx", "%edx", "memory", "cc");
212}
213
214#else
215
216/* generic load/store macros */
217
bellardc27004e2005-01-03 23:35:10 +0000218static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
bellardb92e5a22003-08-08 23:58:05 +0000219{
blueswir14d7a0882008-05-10 10:14:22 +0000220 int page_index;
bellardb92e5a22003-08-08 23:58:05 +0000221 RES_TYPE res;
bellardc27004e2005-01-03 23:35:10 +0000222 target_ulong addr;
223 unsigned long physaddr;
j_mayer6ebbf392007-10-14 07:07:08 +0000224 int mmu_idx;
bellard61382a52003-10-27 21:22:23 +0000225
bellardc27004e2005-01-03 23:35:10 +0000226 addr = ptr;
blueswir14d7a0882008-05-10 10:14:22 +0000227 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
j_mayer6ebbf392007-10-14 07:07:08 +0000228 mmu_idx = CPU_MMU_INDEX;
ths551bd272008-07-03 17:57:36 +0000229 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
230 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
j_mayer6ebbf392007-10-14 07:07:08 +0000231 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
bellardb92e5a22003-08-08 23:58:05 +0000232 } else {
blueswir14d7a0882008-05-10 10:14:22 +0000233 physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
bellard61382a52003-10-27 21:22:23 +0000234 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
bellardb92e5a22003-08-08 23:58:05 +0000235 }
236 return res;
237}
238
239#if DATA_SIZE <= 2
bellardc27004e2005-01-03 23:35:10 +0000240static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
bellardb92e5a22003-08-08 23:58:05 +0000241{
blueswir14d7a0882008-05-10 10:14:22 +0000242 int res, page_index;
bellardc27004e2005-01-03 23:35:10 +0000243 target_ulong addr;
244 unsigned long physaddr;
j_mayer6ebbf392007-10-14 07:07:08 +0000245 int mmu_idx;
bellard61382a52003-10-27 21:22:23 +0000246
bellardc27004e2005-01-03 23:35:10 +0000247 addr = ptr;
blueswir14d7a0882008-05-10 10:14:22 +0000248 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
j_mayer6ebbf392007-10-14 07:07:08 +0000249 mmu_idx = CPU_MMU_INDEX;
ths551bd272008-07-03 17:57:36 +0000250 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
251 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
j_mayer6ebbf392007-10-14 07:07:08 +0000252 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
bellardb92e5a22003-08-08 23:58:05 +0000253 } else {
blueswir14d7a0882008-05-10 10:14:22 +0000254 physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000255 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
256 }
257 return res;
258}
259#endif
260
j_mayer6ebbf392007-10-14 07:07:08 +0000261#if ACCESS_TYPE != (NB_MMU_MODES + 1)
bellard84b7b8e2005-11-28 21:19:04 +0000262
bellarde16c53f2004-01-04 18:15:29 +0000263/* generic store macro */
264
bellardc27004e2005-01-03 23:35:10 +0000265static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
bellardb92e5a22003-08-08 23:58:05 +0000266{
blueswir14d7a0882008-05-10 10:14:22 +0000267 int page_index;
bellardc27004e2005-01-03 23:35:10 +0000268 target_ulong addr;
269 unsigned long physaddr;
j_mayer6ebbf392007-10-14 07:07:08 +0000270 int mmu_idx;
bellard61382a52003-10-27 21:22:23 +0000271
bellardc27004e2005-01-03 23:35:10 +0000272 addr = ptr;
blueswir14d7a0882008-05-10 10:14:22 +0000273 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
j_mayer6ebbf392007-10-14 07:07:08 +0000274 mmu_idx = CPU_MMU_INDEX;
ths551bd272008-07-03 17:57:36 +0000275 if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
276 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
j_mayer6ebbf392007-10-14 07:07:08 +0000277 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
bellardb92e5a22003-08-08 23:58:05 +0000278 } else {
blueswir14d7a0882008-05-10 10:14:22 +0000279 physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000280 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
281 }
282}
283
j_mayer6ebbf392007-10-14 07:07:08 +0000284#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
bellard84b7b8e2005-11-28 21:19:04 +0000285
286#endif /* !asm */
287
j_mayer6ebbf392007-10-14 07:07:08 +0000288#if ACCESS_TYPE != (NB_MMU_MODES + 1)
bellarde16c53f2004-01-04 18:15:29 +0000289
bellard2d603d22004-01-04 23:56:24 +0000290#if DATA_SIZE == 8
bellard3f87bf62005-11-06 19:56:23 +0000291static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
bellard2d603d22004-01-04 23:56:24 +0000292{
293 union {
bellard3f87bf62005-11-06 19:56:23 +0000294 float64 d;
bellard2d603d22004-01-04 23:56:24 +0000295 uint64_t i;
296 } u;
297 u.i = glue(ldq, MEMSUFFIX)(ptr);
298 return u.d;
299}
300
bellard3f87bf62005-11-06 19:56:23 +0000301static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
bellard2d603d22004-01-04 23:56:24 +0000302{
303 union {
bellard3f87bf62005-11-06 19:56:23 +0000304 float64 d;
bellard2d603d22004-01-04 23:56:24 +0000305 uint64_t i;
306 } u;
307 u.d = v;
308 glue(stq, MEMSUFFIX)(ptr, u.i);
309}
310#endif /* DATA_SIZE == 8 */
311
312#if DATA_SIZE == 4
bellard3f87bf62005-11-06 19:56:23 +0000313static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
bellard2d603d22004-01-04 23:56:24 +0000314{
315 union {
bellard3f87bf62005-11-06 19:56:23 +0000316 float32 f;
bellard2d603d22004-01-04 23:56:24 +0000317 uint32_t i;
318 } u;
319 u.i = glue(ldl, MEMSUFFIX)(ptr);
320 return u.f;
321}
322
bellard3f87bf62005-11-06 19:56:23 +0000323static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
bellard2d603d22004-01-04 23:56:24 +0000324{
325 union {
bellard3f87bf62005-11-06 19:56:23 +0000326 float32 f;
bellard2d603d22004-01-04 23:56:24 +0000327 uint32_t i;
328 } u;
329 u.f = v;
330 glue(stl, MEMSUFFIX)(ptr, u.i);
331}
332#endif /* DATA_SIZE == 4 */
333
j_mayer6ebbf392007-10-14 07:07:08 +0000334#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
bellard84b7b8e2005-11-28 21:19:04 +0000335
bellardb92e5a22003-08-08 23:58:05 +0000336#undef RES_TYPE
337#undef DATA_TYPE
338#undef DATA_STYPE
339#undef SUFFIX
bellard61382a52003-10-27 21:22:23 +0000340#undef USUFFIX
bellardb92e5a22003-08-08 23:58:05 +0000341#undef DATA_SIZE
j_mayer6ebbf392007-10-14 07:07:08 +0000342#undef CPU_MMU_INDEX
bellard61382a52003-10-27 21:22:23 +0000343#undef MMUSUFFIX
bellard84b7b8e2005-11-28 21:19:04 +0000344#undef ADDR_READ