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balrog3e3d5812007-04-30 02:09:25 +00001/*
2 * Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash
3 * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
4 * Samsung Electronic.
5 *
6 * Copyright (c) 2006 Openedhand Ltd.
7 * Written by Andrzej Zaborowski <balrog@zabor.org>
8 *
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +01009 * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
10 * datasheet from Micron Technology and "NAND02G-B2C" datasheet
11 * from ST Microelectronics.
12 *
balrog3e3d5812007-04-30 02:09:25 +000013 * This code is licensed under the GNU GPL v2.
Paolo Bonzini6b620ca2012-01-13 17:44:23 +010014 *
15 * Contributions after 2012-01-13 are licensed under the terms of the
16 * GNU GPL, version 2 or (at your option) any later version.
balrog3e3d5812007-04-30 02:09:25 +000017 */
18
19#ifndef NAND_IO
20
pbrook87ecb682007-11-17 17:14:51 +000021# include "hw.h"
22# include "flash.h"
Markus Armbruster666daa62010-06-02 18:48:27 +020023# include "blockdev.h"
Juha Riihimäkid4220382011-07-29 16:35:24 +010024# include "sysbus.h"
Juha Riihimäki3fc3abf2011-10-20 14:53:34 +020025#include "qemu-error.h"
balrog3e3d5812007-04-30 02:09:25 +000026
27# define NAND_CMD_READ0 0x00
28# define NAND_CMD_READ1 0x01
29# define NAND_CMD_READ2 0x50
30# define NAND_CMD_LPREAD2 0x30
31# define NAND_CMD_NOSERIALREAD2 0x35
32# define NAND_CMD_RANDOMREAD1 0x05
33# define NAND_CMD_RANDOMREAD2 0xe0
34# define NAND_CMD_READID 0x90
35# define NAND_CMD_RESET 0xff
36# define NAND_CMD_PAGEPROGRAM1 0x80
37# define NAND_CMD_PAGEPROGRAM2 0x10
38# define NAND_CMD_CACHEPROGRAM2 0x15
39# define NAND_CMD_BLOCKERASE1 0x60
40# define NAND_CMD_BLOCKERASE2 0xd0
41# define NAND_CMD_READSTATUS 0x70
42# define NAND_CMD_COPYBACKPRG1 0x85
43
44# define NAND_IOSTATUS_ERROR (1 << 0)
45# define NAND_IOSTATUS_PLANE0 (1 << 1)
46# define NAND_IOSTATUS_PLANE1 (1 << 2)
47# define NAND_IOSTATUS_PLANE2 (1 << 3)
48# define NAND_IOSTATUS_PLANE3 (1 << 4)
49# define NAND_IOSTATUS_BUSY (1 << 6)
50# define NAND_IOSTATUS_UNPROTCT (1 << 7)
51
52# define MAX_PAGE 0x800
53# define MAX_OOB 0x40
54
Juha Riihimäkid4220382011-07-29 16:35:24 +010055typedef struct NANDFlashState NANDFlashState;
Paul Brookbc24a222009-05-10 01:44:56 +010056struct NANDFlashState {
Juha Riihimäkid4220382011-07-29 16:35:24 +010057 SysBusDevice busdev;
balrog3e3d5812007-04-30 02:09:25 +000058 uint8_t manf_id, chip_id;
Juha Riihimäki48197df2011-07-29 16:35:21 +010059 uint8_t buswidth; /* in BYTES */
balrog3e3d5812007-04-30 02:09:25 +000060 int size, pages;
61 int page_shift, oob_shift, erase_shift, addr_shift;
62 uint8_t *storage;
63 BlockDriverState *bdrv;
64 int mem_oob;
65
Juan Quintela51db57f2010-12-03 01:39:22 +010066 uint8_t cle, ale, ce, wp, gnd;
balrog3e3d5812007-04-30 02:09:25 +000067
68 uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
69 uint8_t *ioaddr;
70 int iolen;
71
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +010072 uint32_t cmd;
73 uint64_t addr;
balrog3e3d5812007-04-30 02:09:25 +000074 int addrlen;
75 int status;
76 int offset;
77
Paul Brookbc24a222009-05-10 01:44:56 +010078 void (*blk_write)(NANDFlashState *s);
79 void (*blk_erase)(NANDFlashState *s);
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +010080 void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
Juan Quintela7b9a3d82010-12-03 01:50:10 +010081
82 uint32_t ioaddr_vmstate;
balrog3e3d5812007-04-30 02:09:25 +000083};
84
Peter Maydell89f640b2011-07-29 16:35:23 +010085static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
86{
87 /* Like memcpy() but we logical-AND the data into the destination */
88 int i;
89 for (i = 0; i < n; i++) {
90 dest[i] &= src[i];
91 }
92}
93
balrog3e3d5812007-04-30 02:09:25 +000094# define NAND_NO_AUTOINCR 0x00000001
95# define NAND_BUSWIDTH_16 0x00000002
96# define NAND_NO_PADDING 0x00000004
97# define NAND_CACHEPRG 0x00000008
98# define NAND_COPYBACK 0x00000010
99# define NAND_IS_AND 0x00000020
100# define NAND_4PAGE_ARRAY 0x00000040
101# define NAND_NO_READRDY 0x00000100
102# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
103
104# define NAND_IO
105
106# define PAGE(addr) ((addr) >> ADDR_SHIFT)
107# define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
108# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
109# define OOB_SHIFT (PAGE_SHIFT - 5)
110# define OOB_SIZE (1 << OOB_SHIFT)
111# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
112# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
113
114# define PAGE_SIZE 256
115# define PAGE_SHIFT 8
116# define PAGE_SECTORS 1
117# define ADDR_SHIFT 8
118# include "nand.c"
119# define PAGE_SIZE 512
120# define PAGE_SHIFT 9
121# define PAGE_SECTORS 1
122# define ADDR_SHIFT 8
123# include "nand.c"
124# define PAGE_SIZE 2048
125# define PAGE_SHIFT 11
126# define PAGE_SECTORS 4
127# define ADDR_SHIFT 16
128# include "nand.c"
129
130/* Information based on Linux drivers/mtd/nand/nand_ids.c */
Paul Brookbc24a222009-05-10 01:44:56 +0100131static const struct {
balrog3e3d5812007-04-30 02:09:25 +0000132 int size;
133 int width;
134 int page_shift;
135 int erase_shift;
136 uint32_t options;
137} nand_flash_ids[0x100] = {
138 [0 ... 0xff] = { 0 },
139
140 [0x6e] = { 1, 8, 8, 4, 0 },
141 [0x64] = { 2, 8, 8, 4, 0 },
142 [0x6b] = { 4, 8, 9, 4, 0 },
143 [0xe8] = { 1, 8, 8, 4, 0 },
144 [0xec] = { 1, 8, 8, 4, 0 },
145 [0xea] = { 2, 8, 8, 4, 0 },
146 [0xd5] = { 4, 8, 9, 4, 0 },
147 [0xe3] = { 4, 8, 9, 4, 0 },
148 [0xe5] = { 4, 8, 9, 4, 0 },
149 [0xd6] = { 8, 8, 9, 4, 0 },
150
151 [0x39] = { 8, 8, 9, 4, 0 },
152 [0xe6] = { 8, 8, 9, 4, 0 },
153 [0x49] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
154 [0x59] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
155
156 [0x33] = { 16, 8, 9, 5, 0 },
157 [0x73] = { 16, 8, 9, 5, 0 },
158 [0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
159 [0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
160
161 [0x35] = { 32, 8, 9, 5, 0 },
162 [0x75] = { 32, 8, 9, 5, 0 },
163 [0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
164 [0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
165
166 [0x36] = { 64, 8, 9, 5, 0 },
167 [0x76] = { 64, 8, 9, 5, 0 },
168 [0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
169 [0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
170
171 [0x78] = { 128, 8, 9, 5, 0 },
172 [0x39] = { 128, 8, 9, 5, 0 },
173 [0x79] = { 128, 8, 9, 5, 0 },
174 [0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
175 [0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
176 [0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
177 [0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
178
179 [0x71] = { 256, 8, 9, 5, 0 },
180
181 /*
182 * These are the new chips with large page size. The pagesize and the
183 * erasesize is determined from the extended id bytes
184 */
185# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
186# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
187
188 /* 512 Megabit */
189 [0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
190 [0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
191 [0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
192 [0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
193
194 /* 1 Gigabit */
195 [0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
196 [0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
197 [0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
198 [0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
199
200 /* 2 Gigabit */
201 [0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
202 [0xda] = { 256, 8, 0, 0, LP_OPTIONS },
203 [0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
204 [0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
205
206 /* 4 Gigabit */
207 [0xac] = { 512, 8, 0, 0, LP_OPTIONS },
208 [0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
209 [0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
210 [0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
211
212 /* 8 Gigabit */
213 [0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
214 [0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
215 [0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
216 [0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
217
218 /* 16 Gigabit */
219 [0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
220 [0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
221 [0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
222 [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
223};
224
Juha Riihimäkid4220382011-07-29 16:35:24 +0100225static void nand_reset(DeviceState *dev)
balrog3e3d5812007-04-30 02:09:25 +0000226{
Juha Riihimäkid4220382011-07-29 16:35:24 +0100227 NANDFlashState *s = FROM_SYSBUS(NANDFlashState, sysbus_from_qdev(dev));
balrog3e3d5812007-04-30 02:09:25 +0000228 s->cmd = NAND_CMD_READ0;
229 s->addr = 0;
230 s->addrlen = 0;
231 s->iolen = 0;
232 s->offset = 0;
233 s->status &= NAND_IOSTATUS_UNPROTCT;
234}
235
Juha Riihimäki48197df2011-07-29 16:35:21 +0100236static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
237{
238 s->ioaddr[s->iolen++] = value;
239 for (value = s->buswidth; --value;) {
240 s->ioaddr[s->iolen++] = 0;
241 }
242}
243
Paul Brookbc24a222009-05-10 01:44:56 +0100244static void nand_command(NANDFlashState *s)
balrog3e3d5812007-04-30 02:09:25 +0000245{
Edgar E. Iglesiasfccd2612010-01-12 14:48:19 +0100246 unsigned int offset;
balrog3e3d5812007-04-30 02:09:25 +0000247 switch (s->cmd) {
248 case NAND_CMD_READ0:
249 s->iolen = 0;
250 break;
251
252 case NAND_CMD_READID:
balrog3e3d5812007-04-30 02:09:25 +0000253 s->ioaddr = s->io;
Juha Riihimäki48197df2011-07-29 16:35:21 +0100254 s->iolen = 0;
255 nand_pushio_byte(s, s->manf_id);
256 nand_pushio_byte(s, s->chip_id);
257 nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
258 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
259 /* Page Size, Block Size, Spare Size; bit 6 indicates
260 * 8 vs 16 bit width NAND.
261 */
262 nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
263 } else {
264 nand_pushio_byte(s, 0xc0); /* Multi-plane */
265 }
balrog3e3d5812007-04-30 02:09:25 +0000266 break;
267
268 case NAND_CMD_RANDOMREAD2:
269 case NAND_CMD_NOSERIALREAD2:
270 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
271 break;
Edgar E. Iglesiasfccd2612010-01-12 14:48:19 +0100272 offset = s->addr & ((1 << s->addr_shift) - 1);
273 s->blk_load(s, s->addr, offset);
274 if (s->gnd)
275 s->iolen = (1 << s->page_shift) - offset;
276 else
277 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
balrog3e3d5812007-04-30 02:09:25 +0000278 break;
279
280 case NAND_CMD_RESET:
Juha Riihimäkid4220382011-07-29 16:35:24 +0100281 nand_reset(&s->busdev.qdev);
balrog3e3d5812007-04-30 02:09:25 +0000282 break;
283
284 case NAND_CMD_PAGEPROGRAM1:
285 s->ioaddr = s->io;
286 s->iolen = 0;
287 break;
288
289 case NAND_CMD_PAGEPROGRAM2:
290 if (s->wp) {
291 s->blk_write(s);
292 }
293 break;
294
295 case NAND_CMD_BLOCKERASE1:
296 break;
297
298 case NAND_CMD_BLOCKERASE2:
299 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)
300 s->addr <<= 16;
301 else
302 s->addr <<= 8;
303
304 if (s->wp) {
305 s->blk_erase(s);
306 }
307 break;
308
309 case NAND_CMD_READSTATUS:
balrog3e3d5812007-04-30 02:09:25 +0000310 s->ioaddr = s->io;
Juha Riihimäki48197df2011-07-29 16:35:21 +0100311 s->iolen = 0;
312 nand_pushio_byte(s, s->status);
balrog3e3d5812007-04-30 02:09:25 +0000313 break;
314
315 default:
316 printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
317 }
318}
319
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100320static void nand_pre_save(void *opaque)
balrogaa941b92007-05-24 18:50:09 +0000321{
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100322 NANDFlashState *s = opaque;
balrogaa941b92007-05-24 18:50:09 +0000323
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100324 s->ioaddr_vmstate = s->ioaddr - s->io;
balrogaa941b92007-05-24 18:50:09 +0000325}
326
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100327static int nand_post_load(void *opaque, int version_id)
balrogaa941b92007-05-24 18:50:09 +0000328{
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100329 NANDFlashState *s = opaque;
balrogaa941b92007-05-24 18:50:09 +0000330
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100331 if (s->ioaddr_vmstate > sizeof(s->io)) {
332 return -EINVAL;
333 }
334 s->ioaddr = s->io + s->ioaddr_vmstate;
335
balrogaa941b92007-05-24 18:50:09 +0000336 return 0;
337}
338
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100339static const VMStateDescription vmstate_nand = {
340 .name = "nand",
Andrzej Zaborowskiac2466c2011-07-30 06:01:37 +0200341 .version_id = 1,
342 .minimum_version_id = 1,
343 .minimum_version_id_old = 1,
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100344 .pre_save = nand_pre_save,
345 .post_load = nand_post_load,
346 .fields = (VMStateField[]) {
347 VMSTATE_UINT8(cle, NANDFlashState),
348 VMSTATE_UINT8(ale, NANDFlashState),
349 VMSTATE_UINT8(ce, NANDFlashState),
350 VMSTATE_UINT8(wp, NANDFlashState),
351 VMSTATE_UINT8(gnd, NANDFlashState),
352 VMSTATE_BUFFER(io, NANDFlashState),
353 VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
354 VMSTATE_INT32(iolen, NANDFlashState),
355 VMSTATE_UINT32(cmd, NANDFlashState),
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100356 VMSTATE_UINT64(addr, NANDFlashState),
Juan Quintela7b9a3d82010-12-03 01:50:10 +0100357 VMSTATE_INT32(addrlen, NANDFlashState),
358 VMSTATE_INT32(status, NANDFlashState),
359 VMSTATE_INT32(offset, NANDFlashState),
360 /* XXX: do we want to save s->storage too? */
361 VMSTATE_END_OF_LIST()
362 }
363};
364
Juha Riihimäkid4220382011-07-29 16:35:24 +0100365static int nand_device_init(SysBusDevice *dev)
366{
367 int pagesize;
368 NANDFlashState *s = FROM_SYSBUS(NANDFlashState, dev);
369
370 s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
371 s->size = nand_flash_ids[s->chip_id].size << 20;
372 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
373 s->page_shift = 11;
374 s->erase_shift = 6;
375 } else {
376 s->page_shift = nand_flash_ids[s->chip_id].page_shift;
377 s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
378 }
379
380 switch (1 << s->page_shift) {
381 case 256:
382 nand_init_256(s);
383 break;
384 case 512:
385 nand_init_512(s);
386 break;
387 case 2048:
388 nand_init_2048(s);
389 break;
390 default:
Juha Riihimäki3fc3abf2011-10-20 14:53:34 +0200391 error_report("Unsupported NAND block size");
392 return -1;
Juha Riihimäkid4220382011-07-29 16:35:24 +0100393 }
394
395 pagesize = 1 << s->oob_shift;
396 s->mem_oob = 1;
Juha Riihimäki3fc3abf2011-10-20 14:53:34 +0200397 if (s->bdrv) {
398 if (bdrv_is_read_only(s->bdrv)) {
399 error_report("Can't use a read-only drive");
400 return -1;
401 }
402 if (bdrv_getlength(s->bdrv) >=
403 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
404 pagesize = 0;
405 s->mem_oob = 0;
406 }
407 } else {
Juha Riihimäkid4220382011-07-29 16:35:24 +0100408 pagesize += 1 << s->page_shift;
409 }
410 if (pagesize) {
Anthony Liguori7267c092011-08-20 22:09:37 -0500411 s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
Juha Riihimäkid4220382011-07-29 16:35:24 +0100412 0xff, s->pages * pagesize);
413 }
414 /* Give s->ioaddr a sane value in case we save state before it is used. */
415 s->ioaddr = s->io;
416
417 return 0;
418}
419
420static SysBusDeviceInfo nand_info = {
421 .init = nand_device_init,
422 .qdev.name = "nand",
423 .qdev.size = sizeof(NANDFlashState),
424 .qdev.reset = nand_reset,
425 .qdev.vmsd = &vmstate_nand,
426 .qdev.props = (Property[]) {
427 DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
428 DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
429 DEFINE_PROP_DRIVE("drive", NANDFlashState, bdrv),
430 DEFINE_PROP_END_OF_LIST()
431 }
432};
433
434static void nand_create_device(void)
435{
436 sysbus_register_withprop(&nand_info);
437}
438
balrog3e3d5812007-04-30 02:09:25 +0000439/*
440 * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip
441 * outputs are R/B and eight I/O pins.
442 *
443 * CE, WP and R/B are active low.
444 */
Juha Riihimäkid4220382011-07-29 16:35:24 +0100445void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
Juan Quintela51db57f2010-12-03 01:39:22 +0100446 uint8_t ce, uint8_t wp, uint8_t gnd)
balrog3e3d5812007-04-30 02:09:25 +0000447{
Juha Riihimäkid4220382011-07-29 16:35:24 +0100448 NANDFlashState *s = (NANDFlashState *) dev;
balrog3e3d5812007-04-30 02:09:25 +0000449 s->cle = cle;
450 s->ale = ale;
451 s->ce = ce;
452 s->wp = wp;
453 s->gnd = gnd;
454 if (wp)
455 s->status |= NAND_IOSTATUS_UNPROTCT;
456 else
457 s->status &= ~NAND_IOSTATUS_UNPROTCT;
458}
459
Juha Riihimäkid4220382011-07-29 16:35:24 +0100460void nand_getpins(DeviceState *dev, int *rb)
balrog3e3d5812007-04-30 02:09:25 +0000461{
462 *rb = 1;
463}
464
Juha Riihimäkid4220382011-07-29 16:35:24 +0100465void nand_setio(DeviceState *dev, uint32_t value)
balrog3e3d5812007-04-30 02:09:25 +0000466{
Juha Riihimäki48197df2011-07-29 16:35:21 +0100467 int i;
Juha Riihimäkid4220382011-07-29 16:35:24 +0100468 NANDFlashState *s = (NANDFlashState *) dev;
balrog3e3d5812007-04-30 02:09:25 +0000469 if (!s->ce && s->cle) {
470 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
471 if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
472 return;
473 if (value == NAND_CMD_RANDOMREAD1) {
474 s->addr &= ~((1 << s->addr_shift) - 1);
475 s->addrlen = 0;
476 return;
477 }
478 }
479 if (value == NAND_CMD_READ0)
480 s->offset = 0;
481 else if (value == NAND_CMD_READ1) {
482 s->offset = 0x100;
483 value = NAND_CMD_READ0;
484 }
485 else if (value == NAND_CMD_READ2) {
486 s->offset = 1 << s->page_shift;
487 value = NAND_CMD_READ0;
488 }
489
490 s->cmd = value;
491
492 if (s->cmd == NAND_CMD_READSTATUS ||
493 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
494 s->cmd == NAND_CMD_BLOCKERASE1 ||
495 s->cmd == NAND_CMD_BLOCKERASE2 ||
496 s->cmd == NAND_CMD_NOSERIALREAD2 ||
497 s->cmd == NAND_CMD_RANDOMREAD2 ||
498 s->cmd == NAND_CMD_RESET)
499 nand_command(s);
500
501 if (s->cmd != NAND_CMD_RANDOMREAD2) {
502 s->addrlen = 0;
balrog3e3d5812007-04-30 02:09:25 +0000503 }
504 }
505
506 if (s->ale) {
Edgar E. Iglesiasfccd2612010-01-12 14:48:19 +0100507 unsigned int shift = s->addrlen * 8;
508 unsigned int mask = ~(0xff << shift);
509 unsigned int v = value << shift;
510
511 s->addr = (s->addr & mask) | v;
balrog3e3d5812007-04-30 02:09:25 +0000512 s->addrlen ++;
513
Juha Riihimäki48197df2011-07-29 16:35:21 +0100514 switch (s->addrlen) {
515 case 1:
516 if (s->cmd == NAND_CMD_READID) {
517 nand_command(s);
518 }
519 break;
520 case 2: /* fix cache address as a byte address */
521 s->addr <<= (s->buswidth - 1);
522 break;
523 case 3:
524 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
525 (s->cmd == NAND_CMD_READ0 ||
526 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
527 nand_command(s);
528 }
529 break;
530 case 4:
531 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
532 nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
533 (s->cmd == NAND_CMD_READ0 ||
534 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
535 nand_command(s);
536 }
537 break;
538 case 5:
539 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
540 nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
541 (s->cmd == NAND_CMD_READ0 ||
542 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
543 nand_command(s);
544 }
545 break;
546 default:
547 break;
548 }
balrog3e3d5812007-04-30 02:09:25 +0000549 }
550
551 if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
Juha Riihimäki48197df2011-07-29 16:35:21 +0100552 if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
553 for (i = s->buswidth; i--; value >>= 8) {
554 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
555 }
556 }
balrog3e3d5812007-04-30 02:09:25 +0000557 } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
558 if ((s->addr & ((1 << s->addr_shift) - 1)) <
559 (1 << s->page_shift) + (1 << s->oob_shift)) {
Juha Riihimäki48197df2011-07-29 16:35:21 +0100560 for (i = s->buswidth; i--; s->addr++, value >>= 8) {
561 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
562 (uint8_t) (value & 0xff);
563 }
balrog3e3d5812007-04-30 02:09:25 +0000564 }
565 }
566}
567
Juha Riihimäkid4220382011-07-29 16:35:24 +0100568uint32_t nand_getio(DeviceState *dev)
balrog3e3d5812007-04-30 02:09:25 +0000569{
570 int offset;
Juha Riihimäki48197df2011-07-29 16:35:21 +0100571 uint32_t x = 0;
Juha Riihimäkid4220382011-07-29 16:35:24 +0100572 NANDFlashState *s = (NANDFlashState *) dev;
ths5fafdf22007-09-16 21:08:06 +0000573
balrog3e3d5812007-04-30 02:09:25 +0000574 /* Allow sequential reading */
575 if (!s->iolen && s->cmd == NAND_CMD_READ0) {
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100576 offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
balrog3e3d5812007-04-30 02:09:25 +0000577 s->offset = 0;
578
579 s->blk_load(s, s->addr, offset);
580 if (s->gnd)
581 s->iolen = (1 << s->page_shift) - offset;
582 else
583 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
584 }
585
586 if (s->ce || s->iolen <= 0)
587 return 0;
588
Juha Riihimäki48197df2011-07-29 16:35:21 +0100589 for (offset = s->buswidth; offset--;) {
590 x |= s->ioaddr[offset] << (offset << 3);
591 }
Juha Riihimäkid72245f2011-07-29 16:35:22 +0100592 /* after receiving READ STATUS command all subsequent reads will
593 * return the status register value until another command is issued
594 */
595 if (s->cmd != NAND_CMD_READSTATUS) {
596 s->addr += s->buswidth;
597 s->ioaddr += s->buswidth;
598 s->iolen -= s->buswidth;
599 }
Juha Riihimäki48197df2011-07-29 16:35:21 +0100600 return x;
601}
602
Juha Riihimäkid4220382011-07-29 16:35:24 +0100603uint32_t nand_getbuswidth(DeviceState *dev)
Juha Riihimäki48197df2011-07-29 16:35:21 +0100604{
Juha Riihimäkid4220382011-07-29 16:35:24 +0100605 NANDFlashState *s = (NANDFlashState *) dev;
Juha Riihimäki48197df2011-07-29 16:35:21 +0100606 return s->buswidth << 3;
balrog3e3d5812007-04-30 02:09:25 +0000607}
608
Juha Riihimäkid4220382011-07-29 16:35:24 +0100609DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id)
balrog3e3d5812007-04-30 02:09:25 +0000610{
Juha Riihimäkid4220382011-07-29 16:35:24 +0100611 DeviceState *dev;
balrog3e3d5812007-04-30 02:09:25 +0000612
613 if (nand_flash_ids[chip_id].size == 0) {
Paul Brook2ac71172009-05-08 02:35:15 +0100614 hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
balrog3e3d5812007-04-30 02:09:25 +0000615 }
Juha Riihimäkid4220382011-07-29 16:35:24 +0100616 dev = qdev_create(NULL, "nand");
617 qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
618 qdev_prop_set_uint8(dev, "chip_id", chip_id);
619 if (bdrv) {
620 qdev_prop_set_drive_nofail(dev, "drive", bdrv);
balrog3e3d5812007-04-30 02:09:25 +0000621 }
622
Juha Riihimäkid4220382011-07-29 16:35:24 +0100623 qdev_init_nofail(dev);
624 return dev;
balrog3e3d5812007-04-30 02:09:25 +0000625}
626
Juha Riihimäkid4220382011-07-29 16:35:24 +0100627device_init(nand_create_device)
balrog3e3d5812007-04-30 02:09:25 +0000628
629#else
630
631/* Program a single page */
Paul Brookbc24a222009-05-10 01:44:56 +0100632static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
balrog3e3d5812007-04-30 02:09:25 +0000633{
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100634 uint64_t off, page, sector, soff;
balrog3e3d5812007-04-30 02:09:25 +0000635 uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
636 if (PAGE(s->addr) >= s->pages)
637 return;
638
639 if (!s->bdrv) {
Peter Maydell89f640b2011-07-29 16:35:23 +0100640 mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
balrog3e3d5812007-04-30 02:09:25 +0000641 s->offset, s->io, s->iolen);
642 } else if (s->mem_oob) {
643 sector = SECTOR(s->addr);
644 off = (s->addr & PAGE_MASK) + s->offset;
645 soff = SECTOR_OFFSET(s->addr);
646 if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1) {
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100647 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
balrog3e3d5812007-04-30 02:09:25 +0000648 return;
649 }
650
Peter Maydell89f640b2011-07-29 16:35:23 +0100651 mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
balrog3e3d5812007-04-30 02:09:25 +0000652 if (off + s->iolen > PAGE_SIZE) {
653 page = PAGE(s->addr);
Peter Maydell89f640b2011-07-29 16:35:23 +0100654 mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
balrog3e3d5812007-04-30 02:09:25 +0000655 MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
656 }
657
658 if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100659 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
balrog3e3d5812007-04-30 02:09:25 +0000660 } else {
661 off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
662 sector = off >> 9;
663 soff = off & 0x1ff;
664 if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1) {
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100665 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
balrog3e3d5812007-04-30 02:09:25 +0000666 return;
667 }
668
Peter Maydell89f640b2011-07-29 16:35:23 +0100669 mem_and(iobuf + soff, s->io, s->iolen);
balrog3e3d5812007-04-30 02:09:25 +0000670
671 if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100672 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
balrog3e3d5812007-04-30 02:09:25 +0000673 }
674 s->offset = 0;
675}
676
677/* Erase a single block */
Paul Brookbc24a222009-05-10 01:44:56 +0100678static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
balrog3e3d5812007-04-30 02:09:25 +0000679{
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100680 uint64_t i, page, addr;
balrog3e3d5812007-04-30 02:09:25 +0000681 uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
682 addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
683
684 if (PAGE(addr) >= s->pages)
685 return;
686
687 if (!s->bdrv) {
688 memset(s->storage + PAGE_START(addr),
689 0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
690 } else if (s->mem_oob) {
691 memset(s->storage + (PAGE(addr) << OOB_SHIFT),
692 0xff, OOB_SIZE << s->erase_shift);
693 i = SECTOR(addr);
694 page = SECTOR(addr + (ADDR_SHIFT + s->erase_shift));
695 for (; i < page; i ++)
696 if (bdrv_write(s->bdrv, i, iobuf, 1) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100697 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
balrog3e3d5812007-04-30 02:09:25 +0000698 } else {
699 addr = PAGE_START(addr);
700 page = addr >> 9;
701 if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100702 printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
balrog3e3d5812007-04-30 02:09:25 +0000703 memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
704 if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100705 printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
balrog3e3d5812007-04-30 02:09:25 +0000706
707 memset(iobuf, 0xff, 0x200);
708 i = (addr & ~0x1ff) + 0x200;
709 for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
710 i < addr; i += 0x200)
711 if (bdrv_write(s->bdrv, i >> 9, iobuf, 1) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100712 printf("%s: write error in sector %" PRIu64 "\n",
713 __func__, i >> 9);
balrog3e3d5812007-04-30 02:09:25 +0000714
715 page = i >> 9;
716 if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100717 printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
balroga07dec22007-05-12 09:19:36 +0000718 memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
balrog3e3d5812007-04-30 02:09:25 +0000719 if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100720 printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
balrog3e3d5812007-04-30 02:09:25 +0000721 }
722}
723
Paul Brookbc24a222009-05-10 01:44:56 +0100724static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100725 uint64_t addr, int offset)
balrog3e3d5812007-04-30 02:09:25 +0000726{
727 if (PAGE(addr) >= s->pages)
728 return;
729
730 if (s->bdrv) {
731 if (s->mem_oob) {
732 if (bdrv_read(s->bdrv, SECTOR(addr), s->io, PAGE_SECTORS) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100733 printf("%s: read error in sector %" PRIu64 "\n",
734 __func__, SECTOR(addr));
balrog3e3d5812007-04-30 02:09:25 +0000735 memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
736 s->storage + (PAGE(s->addr) << OOB_SHIFT),
737 OOB_SIZE);
738 s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
739 } else {
740 if (bdrv_read(s->bdrv, PAGE_START(addr) >> 9,
741 s->io, (PAGE_SECTORS + 2)) == -1)
Juha Riihimäkid5f2fd52011-07-29 16:35:20 +0100742 printf("%s: read error in sector %" PRIu64 "\n",
743 __func__, PAGE_START(addr) >> 9);
balrog3e3d5812007-04-30 02:09:25 +0000744 s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
745 }
746 } else {
747 memcpy(s->io, s->storage + PAGE_START(s->addr) +
748 offset, PAGE_SIZE + OOB_SIZE - offset);
749 s->ioaddr = s->io;
750 }
balrog3e3d5812007-04-30 02:09:25 +0000751}
752
Paul Brookbc24a222009-05-10 01:44:56 +0100753static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
balrog3e3d5812007-04-30 02:09:25 +0000754{
755 s->oob_shift = PAGE_SHIFT - 5;
756 s->pages = s->size >> PAGE_SHIFT;
757 s->addr_shift = ADDR_SHIFT;
758
759 s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
760 s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
761 s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
762}
763
764# undef PAGE_SIZE
765# undef PAGE_SHIFT
766# undef PAGE_SECTORS
767# undef ADDR_SHIFT
768#endif /* NAND_IO */