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bellard574bbf72005-01-03 23:27:31 +00001/*
2 * APIC support
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard574bbf72005-01-03 23:27:31 +00004 * Copyright (c) 2004-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>
bellard574bbf72005-01-03 23:27:31 +000018 */
pbrook87ecb682007-11-17 17:14:51 +000019#include "hw.h"
Blue Swirlaa28b9b2010-03-21 19:46:26 +000020#include "apic.h"
Jan Kiszka0280b572011-02-03 22:54:11 +010021#include "ioapic.h"
pbrook87ecb682007-11-17 17:14:51 +000022#include "qemu-timer.h"
aurel32bb7e7292008-10-12 20:16:03 +000023#include "host-utils.h"
Blue Swirl8546b092010-06-19 07:44:07 +000024#include "sysbus.h"
Blue Swirld8023f32010-10-20 16:41:28 +000025#include "trace.h"
bellard574bbf72005-01-03 23:27:31 +000026
27/* APIC Local Vector Table */
28#define APIC_LVT_TIMER 0
29#define APIC_LVT_THERMAL 1
30#define APIC_LVT_PERFORM 2
31#define APIC_LVT_LINT0 3
32#define APIC_LVT_LINT1 4
33#define APIC_LVT_ERROR 5
34#define APIC_LVT_NB 6
35
36/* APIC delivery modes */
37#define APIC_DM_FIXED 0
38#define APIC_DM_LOWPRI 1
39#define APIC_DM_SMI 2
40#define APIC_DM_NMI 4
41#define APIC_DM_INIT 5
42#define APIC_DM_SIPI 6
43#define APIC_DM_EXTINT 7
44
bellardd592d302005-07-23 19:05:37 +000045/* APIC destination mode */
46#define APIC_DESTMODE_FLAT 0xf
47#define APIC_DESTMODE_CLUSTER 1
48
bellard574bbf72005-01-03 23:27:31 +000049#define APIC_TRIGGER_EDGE 0
50#define APIC_TRIGGER_LEVEL 1
51
52#define APIC_LVT_TIMER_PERIODIC (1<<17)
53#define APIC_LVT_MASKED (1<<16)
54#define APIC_LVT_LEVEL_TRIGGER (1<<15)
55#define APIC_LVT_REMOTE_IRR (1<<14)
56#define APIC_INPUT_POLARITY (1<<13)
57#define APIC_SEND_PENDING (1<<12)
58
59#define ESR_ILLEGAL_ADDRESS (1 << 7)
60
Jan Kiszka0280b572011-02-03 22:54:11 +010061#define APIC_SV_DIRECTED_IO (1<<12)
62#define APIC_SV_ENABLE (1<<8)
bellard574bbf72005-01-03 23:27:31 +000063
bellardd3e9db92005-12-17 01:27:28 +000064#define MAX_APICS 255
65#define MAX_APIC_WORDS 8
66
Michael S. Tsirkin54c96da2009-06-21 19:50:03 +030067/* Intel APIC constants: from include/asm/msidef.h */
68#define MSI_DATA_VECTOR_SHIFT 0
69#define MSI_DATA_VECTOR_MASK 0x000000ff
70#define MSI_DATA_DELIVERY_MODE_SHIFT 8
71#define MSI_DATA_TRIGGER_SHIFT 15
72#define MSI_DATA_LEVEL_SHIFT 14
73#define MSI_ADDR_DEST_MODE_SHIFT 2
74#define MSI_ADDR_DEST_ID_SHIFT 12
75#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
76
Michael S. Tsirkin54c96da2009-06-21 19:50:03 +030077#define MSI_ADDR_SIZE 0x100000
78
Blue Swirl92a16d72010-06-19 07:47:42 +000079typedef struct APICState APICState;
80
Blue Swirlcf6d64b2010-06-19 10:42:08 +030081struct APICState {
Blue Swirl8546b092010-06-19 07:44:07 +000082 SysBusDevice busdev;
Avi Kivity312b4232011-08-15 17:17:16 +030083 MemoryRegion io_memory;
Blue Swirl8546b092010-06-19 07:44:07 +000084 void *cpu_env;
bellard574bbf72005-01-03 23:27:31 +000085 uint32_t apicbase;
86 uint8_t id;
bellardd592d302005-07-23 19:05:37 +000087 uint8_t arb_id;
bellard574bbf72005-01-03 23:27:31 +000088 uint8_t tpr;
89 uint32_t spurious_vec;
bellardd592d302005-07-23 19:05:37 +000090 uint8_t log_dest;
91 uint8_t dest_mode;
bellard574bbf72005-01-03 23:27:31 +000092 uint32_t isr[8]; /* in service register */
93 uint32_t tmr[8]; /* trigger mode register */
94 uint32_t irr[8]; /* interrupt request register */
95 uint32_t lvt[APIC_LVT_NB];
96 uint32_t esr; /* error register */
97 uint32_t icr[2];
98
99 uint32_t divide_conf;
100 int count_shift;
101 uint32_t initial_count;
102 int64_t initial_count_load_time, next_time;
Gleb Natapov678e12c2009-06-10 15:40:48 +0300103 uint32_t idx;
bellard574bbf72005-01-03 23:27:31 +0000104 QEMUTimer *timer;
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300105 int sipi_vector;
106 int wait_for_sipi;
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300107};
bellard574bbf72005-01-03 23:27:31 +0000108
bellardd3e9db92005-12-17 01:27:28 +0000109static APICState *local_apics[MAX_APICS + 1];
aliguori73822ec2009-01-15 20:11:34 +0000110static int apic_irq_delivered;
111
bellardd592d302005-07-23 19:05:37 +0000112static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
113static void apic_update_irq(APICState *s);
aliguori610626a2009-03-12 20:25:12 +0000114static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
115 uint8_t dest, uint8_t dest_mode);
bellardd592d302005-07-23 19:05:37 +0000116
aurel323b63c042008-12-06 10:46:35 +0000117/* Find first bit starting from msb */
118static int fls_bit(uint32_t value)
119{
120 return 31 - clz32(value);
121}
122
aurel32e95f5492008-10-12 00:53:17 +0000123/* Find first bit starting from lsb */
bellardd3e9db92005-12-17 01:27:28 +0000124static int ffs_bit(uint32_t value)
125{
aurel32bb7e7292008-10-12 20:16:03 +0000126 return ctz32(value);
bellardd3e9db92005-12-17 01:27:28 +0000127}
128
129static inline void set_bit(uint32_t *tab, int index)
130{
131 int i, mask;
132 i = index >> 5;
133 mask = 1 << (index & 0x1f);
134 tab[i] |= mask;
135}
136
137static inline void reset_bit(uint32_t *tab, int index)
138{
139 int i, mask;
140 i = index >> 5;
141 mask = 1 << (index & 0x1f);
142 tab[i] &= ~mask;
143}
144
aliguori73822ec2009-01-15 20:11:34 +0000145static inline int get_bit(uint32_t *tab, int index)
146{
147 int i, mask;
148 i = index >> 5;
149 mask = 1 << (index & 0x1f);
150 return !!(tab[i] & mask);
151}
152
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300153static void apic_local_deliver(APICState *s, int vector)
aurel32a5b38b52008-04-13 16:08:30 +0000154{
aurel32a5b38b52008-04-13 16:08:30 +0000155 uint32_t lvt = s->lvt[vector];
156 int trigger_mode;
157
Blue Swirld8023f32010-10-20 16:41:28 +0000158 trace_apic_local_deliver(vector, (lvt >> 8) & 7);
159
aurel32a5b38b52008-04-13 16:08:30 +0000160 if (lvt & APIC_LVT_MASKED)
161 return;
162
163 switch ((lvt >> 8) & 7) {
164 case APIC_DM_SMI:
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300165 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
aurel32a5b38b52008-04-13 16:08:30 +0000166 break;
167
168 case APIC_DM_NMI:
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300169 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
aurel32a5b38b52008-04-13 16:08:30 +0000170 break;
171
172 case APIC_DM_EXTINT:
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300173 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
aurel32a5b38b52008-04-13 16:08:30 +0000174 break;
175
176 case APIC_DM_FIXED:
177 trigger_mode = APIC_TRIGGER_EDGE;
178 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
179 (lvt & APIC_LVT_LEVEL_TRIGGER))
180 trigger_mode = APIC_TRIGGER_LEVEL;
181 apic_set_irq(s, lvt & 0xff, trigger_mode);
182 }
183}
184
Blue Swirl92a16d72010-06-19 07:47:42 +0000185void apic_deliver_pic_intr(DeviceState *d, int level)
aurel321a7de942008-08-21 03:14:52 +0000186{
Blue Swirl92a16d72010-06-19 07:47:42 +0000187 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
188
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300189 if (level) {
190 apic_local_deliver(s, APIC_LVT_LINT0);
191 } else {
aurel321a7de942008-08-21 03:14:52 +0000192 uint32_t lvt = s->lvt[APIC_LVT_LINT0];
193
194 switch ((lvt >> 8) & 7) {
195 case APIC_DM_FIXED:
196 if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
197 break;
198 reset_bit(s->irr, lvt & 0xff);
199 /* fall through */
200 case APIC_DM_EXTINT:
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300201 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
aurel321a7de942008-08-21 03:14:52 +0000202 break;
203 }
204 }
205}
206
bellardd3e9db92005-12-17 01:27:28 +0000207#define foreach_apic(apic, deliver_bitmask, code) \
208{\
209 int __i, __j, __mask;\
210 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
211 __mask = deliver_bitmask[__i];\
212 if (__mask) {\
213 for(__j = 0; __j < 32; __j++) {\
214 if (__mask & (1 << __j)) {\
215 apic = local_apics[__i * 32 + __j];\
216 if (apic) {\
217 code;\
218 }\
219 }\
220 }\
221 }\
222 }\
223}
224
ths5fafdf22007-09-16 21:08:06 +0000225static void apic_bus_deliver(const uint32_t *deliver_bitmask,
bellardd3e9db92005-12-17 01:27:28 +0000226 uint8_t delivery_mode,
bellardd592d302005-07-23 19:05:37 +0000227 uint8_t vector_num, uint8_t polarity,
228 uint8_t trigger_mode)
229{
230 APICState *apic_iter;
231
232 switch (delivery_mode) {
233 case APIC_DM_LOWPRI:
bellard8dd69b82005-11-23 20:59:44 +0000234 /* XXX: search for focus processor, arbitration */
bellardd3e9db92005-12-17 01:27:28 +0000235 {
236 int i, d;
237 d = -1;
238 for(i = 0; i < MAX_APIC_WORDS; i++) {
239 if (deliver_bitmask[i]) {
240 d = i * 32 + ffs_bit(deliver_bitmask[i]);
241 break;
242 }
243 }
244 if (d >= 0) {
245 apic_iter = local_apics[d];
246 if (apic_iter) {
247 apic_set_irq(apic_iter, vector_num, trigger_mode);
248 }
249 }
bellard8dd69b82005-11-23 20:59:44 +0000250 }
bellardd3e9db92005-12-17 01:27:28 +0000251 return;
bellard8dd69b82005-11-23 20:59:44 +0000252
bellardd592d302005-07-23 19:05:37 +0000253 case APIC_DM_FIXED:
bellardd592d302005-07-23 19:05:37 +0000254 break;
255
256 case APIC_DM_SMI:
aurel32e2eb9d32008-04-13 16:08:23 +0000257 foreach_apic(apic_iter, deliver_bitmask,
258 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
259 return;
260
bellardd592d302005-07-23 19:05:37 +0000261 case APIC_DM_NMI:
aurel32e2eb9d32008-04-13 16:08:23 +0000262 foreach_apic(apic_iter, deliver_bitmask,
263 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
264 return;
bellardd592d302005-07-23 19:05:37 +0000265
266 case APIC_DM_INIT:
267 /* normal INIT IPI sent to processors */
ths5fafdf22007-09-16 21:08:06 +0000268 foreach_apic(apic_iter, deliver_bitmask,
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300269 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
bellardd592d302005-07-23 19:05:37 +0000270 return;
ths3b46e622007-09-17 08:09:54 +0000271
bellardd592d302005-07-23 19:05:37 +0000272 case APIC_DM_EXTINT:
bellardb1fc0342005-07-23 21:43:15 +0000273 /* handled in I/O APIC code */
bellardd592d302005-07-23 19:05:37 +0000274 break;
275
276 default:
277 return;
278 }
279
ths5fafdf22007-09-16 21:08:06 +0000280 foreach_apic(apic_iter, deliver_bitmask,
bellardd3e9db92005-12-17 01:27:28 +0000281 apic_set_irq(apic_iter, vector_num, trigger_mode) );
bellardd592d302005-07-23 19:05:37 +0000282}
bellard574bbf72005-01-03 23:27:31 +0000283
aliguori610626a2009-03-12 20:25:12 +0000284void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
285 uint8_t delivery_mode, uint8_t vector_num,
286 uint8_t polarity, uint8_t trigger_mode)
287{
288 uint32_t deliver_bitmask[MAX_APIC_WORDS];
289
Blue Swirld8023f32010-10-20 16:41:28 +0000290 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
291 polarity, trigger_mode);
292
aliguori610626a2009-03-12 20:25:12 +0000293 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
294 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
295 trigger_mode);
296}
297
Blue Swirl92a16d72010-06-19 07:47:42 +0000298void cpu_set_apic_base(DeviceState *d, uint64_t val)
bellard574bbf72005-01-03 23:27:31 +0000299{
Blue Swirl92a16d72010-06-19 07:47:42 +0000300 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
301
Blue Swirld8023f32010-10-20 16:41:28 +0000302 trace_cpu_set_apic_base(val);
303
aurel322c7c13d2009-04-08 22:56:26 +0000304 if (!s)
305 return;
ths5fafdf22007-09-16 21:08:06 +0000306 s->apicbase = (val & 0xfffff000) |
bellard574bbf72005-01-03 23:27:31 +0000307 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
308 /* if disabled, cannot be enabled again */
309 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
310 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300311 cpu_clear_apic_feature(s->cpu_env);
bellard574bbf72005-01-03 23:27:31 +0000312 s->spurious_vec &= ~APIC_SV_ENABLE;
313 }
314}
315
Blue Swirl92a16d72010-06-19 07:47:42 +0000316uint64_t cpu_get_apic_base(DeviceState *d)
bellard574bbf72005-01-03 23:27:31 +0000317{
Blue Swirl92a16d72010-06-19 07:47:42 +0000318 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
319
Blue Swirld8023f32010-10-20 16:41:28 +0000320 trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
321
aurel322c7c13d2009-04-08 22:56:26 +0000322 return s ? s->apicbase : 0;
bellard574bbf72005-01-03 23:27:31 +0000323}
324
Blue Swirl92a16d72010-06-19 07:47:42 +0000325void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
bellard9230e662005-01-23 20:46:56 +0000326{
Blue Swirl92a16d72010-06-19 07:47:42 +0000327 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
328
aurel322c7c13d2009-04-08 22:56:26 +0000329 if (!s)
330 return;
bellard9230e662005-01-23 20:46:56 +0000331 s->tpr = (val & 0x0f) << 4;
bellardd592d302005-07-23 19:05:37 +0000332 apic_update_irq(s);
bellard9230e662005-01-23 20:46:56 +0000333}
334
Blue Swirl92a16d72010-06-19 07:47:42 +0000335uint8_t cpu_get_apic_tpr(DeviceState *d)
bellard9230e662005-01-23 20:46:56 +0000336{
Blue Swirl92a16d72010-06-19 07:47:42 +0000337 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
338
aurel322c7c13d2009-04-08 22:56:26 +0000339 return s ? s->tpr >> 4 : 0;
bellard9230e662005-01-23 20:46:56 +0000340}
341
bellardd592d302005-07-23 19:05:37 +0000342/* return -1 if no bit is set */
343static int get_highest_priority_int(uint32_t *tab)
344{
345 int i;
346 for(i = 7; i >= 0; i--) {
347 if (tab[i] != 0) {
aurel323b63c042008-12-06 10:46:35 +0000348 return i * 32 + fls_bit(tab[i]);
bellardd592d302005-07-23 19:05:37 +0000349 }
350 }
351 return -1;
352}
353
bellard574bbf72005-01-03 23:27:31 +0000354static int apic_get_ppr(APICState *s)
355{
356 int tpr, isrv, ppr;
357
358 tpr = (s->tpr >> 4);
359 isrv = get_highest_priority_int(s->isr);
360 if (isrv < 0)
361 isrv = 0;
362 isrv >>= 4;
363 if (tpr >= isrv)
364 ppr = s->tpr;
365 else
366 ppr = isrv << 4;
367 return ppr;
368}
369
bellardd592d302005-07-23 19:05:37 +0000370static int apic_get_arb_pri(APICState *s)
371{
372 /* XXX: arbitration */
373 return 0;
374}
375
Gleb Natapov0fbfbb52011-02-07 16:14:44 +0200376
377/*
378 * <0 - low prio interrupt,
379 * 0 - no interrupt,
380 * >0 - interrupt number
381 */
382static int apic_irq_pending(APICState *s)
383{
384 int irrv, ppr;
385 irrv = get_highest_priority_int(s->irr);
386 if (irrv < 0) {
387 return 0;
388 }
389 ppr = apic_get_ppr(s);
390 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
391 return -1;
392 }
393
394 return irrv;
395}
396
bellard574bbf72005-01-03 23:27:31 +0000397/* signal the CPU if an irq is pending */
398static void apic_update_irq(APICState *s)
399{
Gleb Natapov0fbfbb52011-02-07 16:14:44 +0200400 if (!(s->spurious_vec & APIC_SV_ENABLE)) {
bellardd592d302005-07-23 19:05:37 +0000401 return;
Gleb Natapov0fbfbb52011-02-07 16:14:44 +0200402 }
403 if (apic_irq_pending(s) > 0) {
404 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
405 }
bellard574bbf72005-01-03 23:27:31 +0000406}
407
aliguori73822ec2009-01-15 20:11:34 +0000408void apic_reset_irq_delivered(void)
409{
Blue Swirld8023f32010-10-20 16:41:28 +0000410 trace_apic_reset_irq_delivered(apic_irq_delivered);
411
aliguori73822ec2009-01-15 20:11:34 +0000412 apic_irq_delivered = 0;
413}
414
415int apic_get_irq_delivered(void)
416{
Blue Swirld8023f32010-10-20 16:41:28 +0000417 trace_apic_get_irq_delivered(apic_irq_delivered);
418
aliguori73822ec2009-01-15 20:11:34 +0000419 return apic_irq_delivered;
420}
421
bellard574bbf72005-01-03 23:27:31 +0000422static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
423{
aliguori73822ec2009-01-15 20:11:34 +0000424 apic_irq_delivered += !get_bit(s->irr, vector_num);
Blue Swirld8023f32010-10-20 16:41:28 +0000425
426 trace_apic_set_irq(apic_irq_delivered);
aliguori73822ec2009-01-15 20:11:34 +0000427
bellard574bbf72005-01-03 23:27:31 +0000428 set_bit(s->irr, vector_num);
429 if (trigger_mode)
430 set_bit(s->tmr, vector_num);
431 else
432 reset_bit(s->tmr, vector_num);
433 apic_update_irq(s);
434}
435
436static void apic_eoi(APICState *s)
437{
438 int isrv;
439 isrv = get_highest_priority_int(s->isr);
440 if (isrv < 0)
441 return;
442 reset_bit(s->isr, isrv);
Jan Kiszka0280b572011-02-03 22:54:11 +0100443 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
444 ioapic_eoi_broadcast(isrv);
445 }
bellard574bbf72005-01-03 23:27:31 +0000446 apic_update_irq(s);
447}
448
Gleb Natapov678e12c2009-06-10 15:40:48 +0300449static int apic_find_dest(uint8_t dest)
450{
451 APICState *apic = local_apics[dest];
452 int i;
453
454 if (apic && apic->id == dest)
455 return dest; /* shortcut in case apic->id == apic->idx */
456
457 for (i = 0; i < MAX_APICS; i++) {
458 apic = local_apics[i];
459 if (apic && apic->id == dest)
460 return i;
Alex Williamsonb538e532010-11-05 16:01:29 -0600461 if (!apic)
462 break;
Gleb Natapov678e12c2009-06-10 15:40:48 +0300463 }
464
465 return -1;
466}
467
bellardd3e9db92005-12-17 01:27:28 +0000468static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
469 uint8_t dest, uint8_t dest_mode)
bellardd592d302005-07-23 19:05:37 +0000470{
bellardd592d302005-07-23 19:05:37 +0000471 APICState *apic_iter;
bellardd3e9db92005-12-17 01:27:28 +0000472 int i;
bellardd592d302005-07-23 19:05:37 +0000473
474 if (dest_mode == 0) {
bellardd3e9db92005-12-17 01:27:28 +0000475 if (dest == 0xff) {
476 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
477 } else {
Gleb Natapov678e12c2009-06-10 15:40:48 +0300478 int idx = apic_find_dest(dest);
bellardd3e9db92005-12-17 01:27:28 +0000479 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
Gleb Natapov678e12c2009-06-10 15:40:48 +0300480 if (idx >= 0)
481 set_bit(deliver_bitmask, idx);
bellardd3e9db92005-12-17 01:27:28 +0000482 }
bellardd592d302005-07-23 19:05:37 +0000483 } else {
484 /* XXX: cluster mode */
bellardd3e9db92005-12-17 01:27:28 +0000485 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
486 for(i = 0; i < MAX_APICS; i++) {
487 apic_iter = local_apics[i];
488 if (apic_iter) {
489 if (apic_iter->dest_mode == 0xf) {
490 if (dest & apic_iter->log_dest)
491 set_bit(deliver_bitmask, i);
492 } else if (apic_iter->dest_mode == 0x0) {
493 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
494 (dest & apic_iter->log_dest & 0x0f)) {
495 set_bit(deliver_bitmask, i);
496 }
497 }
Alex Williamsonb538e532010-11-05 16:01:29 -0600498 } else {
499 break;
bellardd3e9db92005-12-17 01:27:28 +0000500 }
bellardd592d302005-07-23 19:05:37 +0000501 }
502 }
bellardd592d302005-07-23 19:05:37 +0000503}
504
Blue Swirl92a16d72010-06-19 07:47:42 +0000505void apic_init_reset(DeviceState *d)
bellardd592d302005-07-23 19:05:37 +0000506{
Blue Swirl92a16d72010-06-19 07:47:42 +0000507 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
bellardd592d302005-07-23 19:05:37 +0000508 int i;
509
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300510 if (!s)
511 return;
512
bellardd592d302005-07-23 19:05:37 +0000513 s->tpr = 0;
514 s->spurious_vec = 0xff;
515 s->log_dest = 0;
bellarde0fd8782005-11-21 23:26:26 +0000516 s->dest_mode = 0xf;
bellardd592d302005-07-23 19:05:37 +0000517 memset(s->isr, 0, sizeof(s->isr));
518 memset(s->tmr, 0, sizeof(s->tmr));
519 memset(s->irr, 0, sizeof(s->irr));
bellardb4511722006-10-08 18:20:51 +0000520 for(i = 0; i < APIC_LVT_NB; i++)
521 s->lvt[i] = 1 << 16; /* mask LVT */
bellardd592d302005-07-23 19:05:37 +0000522 s->esr = 0;
523 memset(s->icr, 0, sizeof(s->icr));
524 s->divide_conf = 0;
525 s->count_shift = 0;
526 s->initial_count = 0;
527 s->initial_count_load_time = 0;
528 s->next_time = 0;
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300529 s->wait_for_sipi = 1;
bellardd592d302005-07-23 19:05:37 +0000530}
531
bellarde0fd8782005-11-21 23:26:26 +0000532static void apic_startup(APICState *s, int vector_num)
533{
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300534 s->sipi_vector = vector_num;
535 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
536}
537
Blue Swirl92a16d72010-06-19 07:47:42 +0000538void apic_sipi(DeviceState *d)
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300539{
Blue Swirl92a16d72010-06-19 07:47:42 +0000540 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
541
Blue Swirl4a942ce2010-06-19 10:42:31 +0300542 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300543
544 if (!s->wait_for_sipi)
bellarde0fd8782005-11-21 23:26:26 +0000545 return;
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300546 cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300547 s->wait_for_sipi = 0;
bellarde0fd8782005-11-21 23:26:26 +0000548}
549
Blue Swirl92a16d72010-06-19 07:47:42 +0000550static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
bellardd592d302005-07-23 19:05:37 +0000551 uint8_t delivery_mode, uint8_t vector_num,
552 uint8_t polarity, uint8_t trigger_mode)
553{
Blue Swirl92a16d72010-06-19 07:47:42 +0000554 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
bellardd3e9db92005-12-17 01:27:28 +0000555 uint32_t deliver_bitmask[MAX_APIC_WORDS];
bellardd592d302005-07-23 19:05:37 +0000556 int dest_shorthand = (s->icr[0] >> 18) & 3;
557 APICState *apic_iter;
558
bellarde0fd8782005-11-21 23:26:26 +0000559 switch (dest_shorthand) {
bellardd3e9db92005-12-17 01:27:28 +0000560 case 0:
561 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
562 break;
563 case 1:
564 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
Gleb Natapov678e12c2009-06-10 15:40:48 +0300565 set_bit(deliver_bitmask, s->idx);
bellardd3e9db92005-12-17 01:27:28 +0000566 break;
567 case 2:
568 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
569 break;
570 case 3:
571 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
Gleb Natapov678e12c2009-06-10 15:40:48 +0300572 reset_bit(deliver_bitmask, s->idx);
bellardd3e9db92005-12-17 01:27:28 +0000573 break;
bellarde0fd8782005-11-21 23:26:26 +0000574 }
575
bellardd592d302005-07-23 19:05:37 +0000576 switch (delivery_mode) {
bellardd592d302005-07-23 19:05:37 +0000577 case APIC_DM_INIT:
578 {
579 int trig_mode = (s->icr[0] >> 15) & 1;
580 int level = (s->icr[0] >> 14) & 1;
581 if (level == 0 && trig_mode == 1) {
ths5fafdf22007-09-16 21:08:06 +0000582 foreach_apic(apic_iter, deliver_bitmask,
bellardd3e9db92005-12-17 01:27:28 +0000583 apic_iter->arb_id = apic_iter->id );
bellardd592d302005-07-23 19:05:37 +0000584 return;
585 }
586 }
587 break;
588
589 case APIC_DM_SIPI:
ths5fafdf22007-09-16 21:08:06 +0000590 foreach_apic(apic_iter, deliver_bitmask,
bellardd3e9db92005-12-17 01:27:28 +0000591 apic_startup(apic_iter, vector_num) );
bellardd592d302005-07-23 19:05:37 +0000592 return;
593 }
594
bellardd592d302005-07-23 19:05:37 +0000595 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
596 trigger_mode);
597}
598
Blue Swirl92a16d72010-06-19 07:47:42 +0000599int apic_get_interrupt(DeviceState *d)
bellard574bbf72005-01-03 23:27:31 +0000600{
Blue Swirl92a16d72010-06-19 07:47:42 +0000601 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
bellard574bbf72005-01-03 23:27:31 +0000602 int intno;
603
604 /* if the APIC is installed or enabled, we let the 8259 handle the
605 IRQs */
606 if (!s)
607 return -1;
608 if (!(s->spurious_vec & APIC_SV_ENABLE))
609 return -1;
ths3b46e622007-09-17 08:09:54 +0000610
Gleb Natapov0fbfbb52011-02-07 16:14:44 +0200611 intno = apic_irq_pending(s);
612
613 if (intno == 0) {
bellard574bbf72005-01-03 23:27:31 +0000614 return -1;
Gleb Natapov0fbfbb52011-02-07 16:14:44 +0200615 } else if (intno < 0) {
bellardd592d302005-07-23 19:05:37 +0000616 return s->spurious_vec & 0xff;
Gleb Natapov0fbfbb52011-02-07 16:14:44 +0200617 }
bellardb4511722006-10-08 18:20:51 +0000618 reset_bit(s->irr, intno);
bellard574bbf72005-01-03 23:27:31 +0000619 set_bit(s->isr, intno);
620 apic_update_irq(s);
621 return intno;
622}
623
Blue Swirl92a16d72010-06-19 07:47:42 +0000624int apic_accept_pic_intr(DeviceState *d)
ths0e21e122007-10-09 03:08:56 +0000625{
Blue Swirl92a16d72010-06-19 07:47:42 +0000626 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
ths0e21e122007-10-09 03:08:56 +0000627 uint32_t lvt0;
628
629 if (!s)
630 return -1;
631
632 lvt0 = s->lvt[APIC_LVT_LINT0];
633
aurel32a5b38b52008-04-13 16:08:30 +0000634 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
635 (lvt0 & APIC_LVT_MASKED) == 0)
ths0e21e122007-10-09 03:08:56 +0000636 return 1;
637
638 return 0;
639}
640
bellard574bbf72005-01-03 23:27:31 +0000641static uint32_t apic_get_current_count(APICState *s)
642{
643 int64_t d;
644 uint32_t val;
Paolo Bonzini74475452011-03-11 16:47:48 +0100645 d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
bellard574bbf72005-01-03 23:27:31 +0000646 s->count_shift;
647 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
648 /* periodic */
bellardd592d302005-07-23 19:05:37 +0000649 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
bellard574bbf72005-01-03 23:27:31 +0000650 } else {
651 if (d >= s->initial_count)
652 val = 0;
653 else
654 val = s->initial_count - d;
655 }
656 return val;
657}
658
659static void apic_timer_update(APICState *s, int64_t current_time)
660{
661 int64_t next_time, d;
ths3b46e622007-09-17 08:09:54 +0000662
bellard574bbf72005-01-03 23:27:31 +0000663 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
ths5fafdf22007-09-16 21:08:06 +0000664 d = (current_time - s->initial_count_load_time) >>
bellard574bbf72005-01-03 23:27:31 +0000665 s->count_shift;
666 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
aliguori681f8c22008-08-18 14:19:42 +0000667 if (!s->initial_count)
668 goto no_timer;
bellardd592d302005-07-23 19:05:37 +0000669 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
bellard574bbf72005-01-03 23:27:31 +0000670 } else {
671 if (d >= s->initial_count)
672 goto no_timer;
bellardd592d302005-07-23 19:05:37 +0000673 d = (uint64_t)s->initial_count + 1;
bellard574bbf72005-01-03 23:27:31 +0000674 }
675 next_time = s->initial_count_load_time + (d << s->count_shift);
676 qemu_mod_timer(s->timer, next_time);
677 s->next_time = next_time;
678 } else {
679 no_timer:
680 qemu_del_timer(s->timer);
681 }
682}
683
684static void apic_timer(void *opaque)
685{
686 APICState *s = opaque;
687
Blue Swirlcf6d64b2010-06-19 10:42:08 +0300688 apic_local_deliver(s, APIC_LVT_TIMER);
bellard574bbf72005-01-03 23:27:31 +0000689 apic_timer_update(s, s->next_time);
690}
691
Anthony Liguoric227f092009-10-01 16:12:16 -0500692static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
bellard574bbf72005-01-03 23:27:31 +0000693{
694 return 0;
695}
696
Anthony Liguoric227f092009-10-01 16:12:16 -0500697static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
bellard574bbf72005-01-03 23:27:31 +0000698{
699 return 0;
700}
701
Anthony Liguoric227f092009-10-01 16:12:16 -0500702static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard574bbf72005-01-03 23:27:31 +0000703{
704}
705
Anthony Liguoric227f092009-10-01 16:12:16 -0500706static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard574bbf72005-01-03 23:27:31 +0000707{
708}
709
Anthony Liguoric227f092009-10-01 16:12:16 -0500710static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
bellard574bbf72005-01-03 23:27:31 +0000711{
Blue Swirl92a16d72010-06-19 07:47:42 +0000712 DeviceState *d;
bellard574bbf72005-01-03 23:27:31 +0000713 APICState *s;
714 uint32_t val;
715 int index;
716
Blue Swirl92a16d72010-06-19 07:47:42 +0000717 d = cpu_get_current_apic();
718 if (!d) {
bellard574bbf72005-01-03 23:27:31 +0000719 return 0;
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300720 }
Blue Swirl92a16d72010-06-19 07:47:42 +0000721 s = DO_UPCAST(APICState, busdev.qdev, d);
bellard574bbf72005-01-03 23:27:31 +0000722
723 index = (addr >> 4) & 0xff;
724 switch(index) {
725 case 0x02: /* id */
726 val = s->id << 24;
727 break;
728 case 0x03: /* version */
729 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
730 break;
731 case 0x08:
732 val = s->tpr;
733 break;
bellardd592d302005-07-23 19:05:37 +0000734 case 0x09:
735 val = apic_get_arb_pri(s);
736 break;
bellard574bbf72005-01-03 23:27:31 +0000737 case 0x0a:
738 /* ppr */
739 val = apic_get_ppr(s);
740 break;
aurel32b237db32008-03-28 22:31:36 +0000741 case 0x0b:
742 val = 0;
743 break;
bellardd592d302005-07-23 19:05:37 +0000744 case 0x0d:
745 val = s->log_dest << 24;
746 break;
747 case 0x0e:
748 val = s->dest_mode << 28;
749 break;
bellard574bbf72005-01-03 23:27:31 +0000750 case 0x0f:
751 val = s->spurious_vec;
752 break;
753 case 0x10 ... 0x17:
754 val = s->isr[index & 7];
755 break;
756 case 0x18 ... 0x1f:
757 val = s->tmr[index & 7];
758 break;
759 case 0x20 ... 0x27:
760 val = s->irr[index & 7];
761 break;
762 case 0x28:
763 val = s->esr;
764 break;
bellard574bbf72005-01-03 23:27:31 +0000765 case 0x30:
766 case 0x31:
767 val = s->icr[index & 1];
768 break;
bellarde0fd8782005-11-21 23:26:26 +0000769 case 0x32 ... 0x37:
770 val = s->lvt[index - 0x32];
771 break;
bellard574bbf72005-01-03 23:27:31 +0000772 case 0x38:
773 val = s->initial_count;
774 break;
775 case 0x39:
776 val = apic_get_current_count(s);
777 break;
778 case 0x3e:
779 val = s->divide_conf;
780 break;
781 default:
782 s->esr |= ESR_ILLEGAL_ADDRESS;
783 val = 0;
784 break;
785 }
Blue Swirld8023f32010-10-20 16:41:28 +0000786 trace_apic_mem_readl(addr, val);
bellard574bbf72005-01-03 23:27:31 +0000787 return val;
788}
789
Andreas Färberf5095c62010-12-19 17:22:39 +0100790static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
Michael S. Tsirkin54c96da2009-06-21 19:50:03 +0300791{
792 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
793 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
794 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
795 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
796 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
797 /* XXX: Ignore redirection hint. */
798 apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
799}
800
Anthony Liguoric227f092009-10-01 16:12:16 -0500801static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard574bbf72005-01-03 23:27:31 +0000802{
Blue Swirl92a16d72010-06-19 07:47:42 +0000803 DeviceState *d;
bellard574bbf72005-01-03 23:27:31 +0000804 APICState *s;
Michael S. Tsirkin54c96da2009-06-21 19:50:03 +0300805 int index = (addr >> 4) & 0xff;
806 if (addr > 0xfff || !index) {
807 /* MSI and MMIO APIC are at the same memory location,
808 * but actually not on the global bus: MSI is on PCI bus
809 * APIC is connected directly to the CPU.
810 * Mapping them on the global bus happens to work because
811 * MSI registers are reserved in APIC MMIO and vice versa. */
812 apic_send_msi(addr, val);
813 return;
814 }
bellard574bbf72005-01-03 23:27:31 +0000815
Blue Swirl92a16d72010-06-19 07:47:42 +0000816 d = cpu_get_current_apic();
817 if (!d) {
bellard574bbf72005-01-03 23:27:31 +0000818 return;
Blue Swirl0e26b7b2010-06-19 10:42:34 +0300819 }
Blue Swirl92a16d72010-06-19 07:47:42 +0000820 s = DO_UPCAST(APICState, busdev.qdev, d);
bellard574bbf72005-01-03 23:27:31 +0000821
Blue Swirld8023f32010-10-20 16:41:28 +0000822 trace_apic_mem_writel(addr, val);
bellard574bbf72005-01-03 23:27:31 +0000823
bellard574bbf72005-01-03 23:27:31 +0000824 switch(index) {
825 case 0x02:
826 s->id = (val >> 24);
827 break;
bellarde0fd8782005-11-21 23:26:26 +0000828 case 0x03:
829 break;
bellard574bbf72005-01-03 23:27:31 +0000830 case 0x08:
831 s->tpr = val;
bellardd592d302005-07-23 19:05:37 +0000832 apic_update_irq(s);
bellard574bbf72005-01-03 23:27:31 +0000833 break;
bellarde0fd8782005-11-21 23:26:26 +0000834 case 0x09:
835 case 0x0a:
836 break;
bellard574bbf72005-01-03 23:27:31 +0000837 case 0x0b: /* EOI */
838 apic_eoi(s);
839 break;
bellardd592d302005-07-23 19:05:37 +0000840 case 0x0d:
841 s->log_dest = val >> 24;
842 break;
843 case 0x0e:
844 s->dest_mode = val >> 28;
845 break;
bellard574bbf72005-01-03 23:27:31 +0000846 case 0x0f:
847 s->spurious_vec = val & 0x1ff;
bellardd592d302005-07-23 19:05:37 +0000848 apic_update_irq(s);
bellard574bbf72005-01-03 23:27:31 +0000849 break;
bellarde0fd8782005-11-21 23:26:26 +0000850 case 0x10 ... 0x17:
851 case 0x18 ... 0x1f:
852 case 0x20 ... 0x27:
853 case 0x28:
854 break;
bellard574bbf72005-01-03 23:27:31 +0000855 case 0x30:
bellardd592d302005-07-23 19:05:37 +0000856 s->icr[0] = val;
Blue Swirl92a16d72010-06-19 07:47:42 +0000857 apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
bellardd592d302005-07-23 19:05:37 +0000858 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
859 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
860 break;
bellard574bbf72005-01-03 23:27:31 +0000861 case 0x31:
bellardd592d302005-07-23 19:05:37 +0000862 s->icr[1] = val;
bellard574bbf72005-01-03 23:27:31 +0000863 break;
864 case 0x32 ... 0x37:
865 {
866 int n = index - 0x32;
867 s->lvt[n] = val;
868 if (n == APIC_LVT_TIMER)
Paolo Bonzini74475452011-03-11 16:47:48 +0100869 apic_timer_update(s, qemu_get_clock_ns(vm_clock));
bellard574bbf72005-01-03 23:27:31 +0000870 }
871 break;
872 case 0x38:
873 s->initial_count = val;
Paolo Bonzini74475452011-03-11 16:47:48 +0100874 s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
bellard574bbf72005-01-03 23:27:31 +0000875 apic_timer_update(s, s->initial_count_load_time);
876 break;
bellarde0fd8782005-11-21 23:26:26 +0000877 case 0x39:
878 break;
bellard574bbf72005-01-03 23:27:31 +0000879 case 0x3e:
880 {
881 int v;
882 s->divide_conf = val & 0xb;
883 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
884 s->count_shift = (v + 1) & 7;
885 }
886 break;
887 default:
888 s->esr |= ESR_ILLEGAL_ADDRESS;
889 break;
890 }
891}
892
Juan Quintela695dcf72009-08-20 19:42:28 +0200893/* This function is only used for old state version 1 and 2 */
894static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
bellardd592d302005-07-23 19:05:37 +0000895{
896 APICState *s = opaque;
897 int i;
898
bellarde6cf6a82006-08-17 10:48:06 +0000899 if (version_id > 2)
bellardd592d302005-07-23 19:05:37 +0000900 return -EINVAL;
901
902 /* XXX: what if the base changes? (registered memory regions) */
903 qemu_get_be32s(f, &s->apicbase);
904 qemu_get_8s(f, &s->id);
905 qemu_get_8s(f, &s->arb_id);
906 qemu_get_8s(f, &s->tpr);
907 qemu_get_be32s(f, &s->spurious_vec);
908 qemu_get_8s(f, &s->log_dest);
909 qemu_get_8s(f, &s->dest_mode);
910 for (i = 0; i < 8; i++) {
911 qemu_get_be32s(f, &s->isr[i]);
912 qemu_get_be32s(f, &s->tmr[i]);
913 qemu_get_be32s(f, &s->irr[i]);
914 }
915 for (i = 0; i < APIC_LVT_NB; i++) {
916 qemu_get_be32s(f, &s->lvt[i]);
917 }
918 qemu_get_be32s(f, &s->esr);
919 qemu_get_be32s(f, &s->icr[0]);
920 qemu_get_be32s(f, &s->icr[1]);
921 qemu_get_be32s(f, &s->divide_conf);
thsbee8d682007-12-16 23:41:11 +0000922 s->count_shift=qemu_get_be32(f);
bellardd592d302005-07-23 19:05:37 +0000923 qemu_get_be32s(f, &s->initial_count);
thsbee8d682007-12-16 23:41:11 +0000924 s->initial_count_load_time=qemu_get_be64(f);
925 s->next_time=qemu_get_be64(f);
bellarde6cf6a82006-08-17 10:48:06 +0000926
927 if (version_id >= 2)
928 qemu_get_timer(f, s->timer);
bellardd592d302005-07-23 19:05:37 +0000929 return 0;
930}
931
Juan Quintela695dcf72009-08-20 19:42:28 +0200932static const VMStateDescription vmstate_apic = {
933 .name = "apic",
934 .version_id = 3,
935 .minimum_version_id = 3,
936 .minimum_version_id_old = 1,
937 .load_state_old = apic_load_old,
938 .fields = (VMStateField []) {
939 VMSTATE_UINT32(apicbase, APICState),
940 VMSTATE_UINT8(id, APICState),
941 VMSTATE_UINT8(arb_id, APICState),
942 VMSTATE_UINT8(tpr, APICState),
943 VMSTATE_UINT32(spurious_vec, APICState),
944 VMSTATE_UINT8(log_dest, APICState),
945 VMSTATE_UINT8(dest_mode, APICState),
946 VMSTATE_UINT32_ARRAY(isr, APICState, 8),
947 VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
948 VMSTATE_UINT32_ARRAY(irr, APICState, 8),
949 VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
950 VMSTATE_UINT32(esr, APICState),
951 VMSTATE_UINT32_ARRAY(icr, APICState, 2),
952 VMSTATE_UINT32(divide_conf, APICState),
953 VMSTATE_INT32(count_shift, APICState),
954 VMSTATE_UINT32(initial_count, APICState),
955 VMSTATE_INT64(initial_count_load_time, APICState),
956 VMSTATE_INT64(next_time, APICState),
957 VMSTATE_TIMER(timer, APICState),
958 VMSTATE_END_OF_LIST()
959 }
960};
961
Blue Swirl8546b092010-06-19 07:44:07 +0000962static void apic_reset(DeviceState *d)
bellardd592d302005-07-23 19:05:37 +0000963{
Blue Swirl8546b092010-06-19 07:44:07 +0000964 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
Avi Kivity4c0960c2009-08-17 23:19:53 +0300965 int bsp;
aurel32fec5fa02008-09-02 00:09:08 +0000966
Avi Kivity4c0960c2009-08-17 23:19:53 +0300967 bsp = cpu_is_bsp(s->cpu_env);
aurel32fec5fa02008-09-02 00:09:08 +0000968 s->apicbase = 0xfee00000 |
Gleb Natapov678e12c2009-06-10 15:40:48 +0300969 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
aurel32fec5fa02008-09-02 00:09:08 +0000970
Blue Swirl92a16d72010-06-19 07:47:42 +0000971 apic_init_reset(d);
ths0e21e122007-10-09 03:08:56 +0000972
Gleb Natapov678e12c2009-06-10 15:40:48 +0300973 if (bsp) {
aurel32a5b38b52008-04-13 16:08:30 +0000974 /*
975 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
976 * time typically by BIOS, so PIC interrupt can be delivered to the
977 * processor when local APIC is enabled.
978 */
979 s->lvt[APIC_LVT_LINT0] = 0x700;
980 }
bellardd592d302005-07-23 19:05:37 +0000981}
bellard574bbf72005-01-03 23:27:31 +0000982
Avi Kivity312b4232011-08-15 17:17:16 +0300983static const MemoryRegionOps apic_io_ops = {
984 .old_mmio = {
985 .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
986 .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
987 },
988 .endianness = DEVICE_NATIVE_ENDIAN,
bellard574bbf72005-01-03 23:27:31 +0000989};
990
Blue Swirl8546b092010-06-19 07:44:07 +0000991static int apic_init1(SysBusDevice *dev)
992{
993 APICState *s = FROM_SYSBUS(APICState, dev);
Blue Swirl8546b092010-06-19 07:44:07 +0000994 static int last_apic_idx;
995
996 if (last_apic_idx >= MAX_APICS) {
997 return -1;
998 }
Avi Kivity312b4232011-08-15 17:17:16 +0300999 memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
1000 MSI_ADDR_SIZE);
1001 sysbus_init_mmio_region(dev, &s->io_memory);
Blue Swirl8546b092010-06-19 07:44:07 +00001002
Paolo Bonzini74475452011-03-11 16:47:48 +01001003 s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
Blue Swirl8546b092010-06-19 07:44:07 +00001004 s->idx = last_apic_idx++;
1005 local_apics[s->idx] = s;
1006 return 0;
1007}
1008
1009static SysBusDeviceInfo apic_info = {
1010 .init = apic_init1,
1011 .qdev.name = "apic",
1012 .qdev.size = sizeof(APICState),
1013 .qdev.vmsd = &vmstate_apic,
1014 .qdev.reset = apic_reset,
1015 .qdev.no_user = 1,
1016 .qdev.props = (Property[]) {
1017 DEFINE_PROP_UINT8("id", APICState, id, -1),
1018 DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1019 DEFINE_PROP_END_OF_LIST(),
1020 }
1021};
1022
1023static void apic_register_devices(void)
1024{
1025 sysbus_register_withprop(&apic_info);
1026}
1027
1028device_init(apic_register_devices)