Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 1 | PROVIDE ( Cache_Read_Disable = 0x400047f0 ); |
| 2 | PROVIDE ( Cache_Read_Enable = 0x40004678 ); |
| 3 | PROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 ); |
| 4 | PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c ); |
| 5 | PROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 ); |
| 6 | PROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 ); |
| 7 | PROVIDE ( GetUartDevice = 0x40003f4c ); |
| 8 | PROVIDE ( MD5Final = 0x40009900 ); |
| 9 | PROVIDE ( MD5Init = 0x40009818 ); |
| 10 | PROVIDE ( MD5Update = 0x40009834 ); |
| 11 | PROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 ); |
| 12 | PROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c ); |
| 13 | PROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 ); |
| 14 | PROVIDE ( RcvMsg = 0x40003eac ); |
| 15 | PROVIDE ( SHA1Final = 0x4000b648 ); |
| 16 | PROVIDE ( SHA1Init = 0x4000b584 ); |
| 17 | PROVIDE ( SHA1Transform = 0x4000a364 ); |
| 18 | PROVIDE ( SHA1Update = 0x4000b5a8 ); |
Paul Sokolovsky | eca9a93 | 2015-01-31 00:36:25 +0200 | [diff] [blame] | 19 | PROVIDE ( SPI_read_status = 0x400043c8 ); |
| 20 | PROVIDE ( SPI_write_status = 0x40004400 ); |
| 21 | PROVIDE ( SPI_write_enable = 0x4000443c ); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 22 | PROVIDE ( Wait_SPI_Idle = 0x4000448c ); |
Paul Sokolovsky | 88d3cd5 | 2016-08-01 00:01:49 +0300 | [diff] [blame] | 23 | PROVIDE ( Enable_QMode = 0x400044c0 ); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 24 | PROVIDE ( SPIEraseArea = 0x40004b44 ); |
| 25 | PROVIDE ( SPIEraseBlock = 0x400049b4 ); |
| 26 | PROVIDE ( SPIEraseChip = 0x40004984 ); |
| 27 | PROVIDE ( SPIEraseSector = 0x40004a00 ); |
| 28 | PROVIDE ( SPILock = 0x400048a8 ); |
| 29 | PROVIDE ( SPIParamCfg = 0x40004c2c ); |
| 30 | PROVIDE ( SPIRead = 0x40004b1c ); |
| 31 | PROVIDE ( SPIReadModeCnfig = 0x400048ec ); |
| 32 | PROVIDE ( SPIUnlock = 0x40004878 ); |
| 33 | PROVIDE ( SPIWrite = 0x40004a4c ); |
| 34 | PROVIDE ( SelectSpiFunction = 0x40003f58 ); |
| 35 | PROVIDE ( SendMsg = 0x40003cf4 ); |
| 36 | PROVIDE ( UartConnCheck = 0x40003230 ); |
| 37 | PROVIDE ( UartConnectProc = 0x400037a0 ); |
| 38 | PROVIDE ( UartDwnLdProc = 0x40003368 ); |
| 39 | PROVIDE ( UartGetCmdLn = 0x40003ef4 ); |
| 40 | PROVIDE ( UartRegReadProc = 0x4000381c ); |
| 41 | PROVIDE ( UartRegWriteProc = 0x400037ac ); |
| 42 | PROVIDE ( UartRxString = 0x40003c30 ); |
| 43 | PROVIDE ( Uart_Init = 0x40003a14 ); |
| 44 | PROVIDE ( _DebugExceptionVector = 0x40000010 ); |
| 45 | PROVIDE ( _DoubleExceptionVector = 0x40000070 ); |
| 46 | PROVIDE ( _KernelExceptionVector = 0x40000030 ); |
| 47 | PROVIDE ( _NMIExceptionVector = 0x40000020 ); |
| 48 | PROVIDE ( _ResetHandler = 0x400000a4 ); |
| 49 | PROVIDE ( _ResetVector = 0x40000080 ); |
| 50 | PROVIDE ( _UserExceptionVector = 0x40000050 ); |
Paul Sokolovsky | 9f8b788 | 2016-06-12 18:44:14 +0300 | [diff] [blame] | 51 | __adddf3 = 0x4000c538; |
| 52 | __addsf3 = 0x4000c180; |
| 53 | __divdf3 = 0x4000cb94; |
Paul Sokolovsky | 0a400a6 | 2016-04-14 14:24:25 +0300 | [diff] [blame] | 54 | __divdi3 = 0x4000ce60; |
| 55 | __divsi3 = 0x4000dc88; |
Paul Sokolovsky | 9f8b788 | 2016-06-12 18:44:14 +0300 | [diff] [blame] | 56 | __extendsfdf2 = 0x4000cdfc; |
| 57 | __fixdfsi = 0x4000ccb8; |
| 58 | __fixunsdfsi = 0x4000cd00; |
| 59 | __fixunssfsi = 0x4000c4c4; |
| 60 | __floatsidf = 0x4000e2f0; |
| 61 | __floatsisf = 0x4000e2ac; |
| 62 | __floatunsidf = 0x4000e2e8; |
| 63 | __floatunsisf = 0x4000e2a4; |
| 64 | __muldf3 = 0x4000c8f0; |
Paul Sokolovsky | 0a400a6 | 2016-04-14 14:24:25 +0300 | [diff] [blame] | 65 | __muldi3 = 0x40000650; |
Paul Sokolovsky | 9f8b788 | 2016-06-12 18:44:14 +0300 | [diff] [blame] | 66 | __mulsf3 = 0x4000c3dc; |
| 67 | __subdf3 = 0x4000c688; |
| 68 | __subsf3 = 0x4000c268; |
| 69 | __truncdfsf2 = 0x4000cd5c; |
Paul Sokolovsky | 0a400a6 | 2016-04-14 14:24:25 +0300 | [diff] [blame] | 70 | __udivdi3 = 0x4000d310; |
| 71 | __udivsi3 = 0x4000e21c; |
| 72 | __umoddi3 = 0x4000d770; |
| 73 | __umodsi3 = 0x4000e268; |
| 74 | __umulsidi3 = 0x4000dcf0; |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 75 | PROVIDE ( _rom_store = 0x4000e388 ); |
| 76 | PROVIDE ( _rom_store_table = 0x4000e328 ); |
| 77 | PROVIDE ( _start = 0x4000042c ); |
| 78 | PROVIDE ( _xtos_alloca_handler = 0x4000dbe0 ); |
| 79 | PROVIDE ( _xtos_c_wrapper_handler = 0x40000598 ); |
| 80 | PROVIDE ( _xtos_cause3_handler = 0x40000590 ); |
| 81 | PROVIDE ( _xtos_ints_off = 0x4000bda4 ); |
| 82 | PROVIDE ( _xtos_ints_on = 0x4000bd84 ); |
| 83 | PROVIDE ( _xtos_l1int_handler = 0x4000048c ); |
| 84 | PROVIDE ( _xtos_p_none = 0x4000dbf8 ); |
| 85 | PROVIDE ( _xtos_restore_intlevel = 0x4000056c ); |
| 86 | PROVIDE ( _xtos_return_from_exc = 0x4000dc54 ); |
| 87 | PROVIDE ( _xtos_set_exception_handler = 0x40000454 ); |
| 88 | PROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 ); |
| 89 | PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 ); |
| 90 | PROVIDE ( _xtos_set_intlevel = 0x4000dbfc ); |
| 91 | PROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 ); |
| 92 | PROVIDE ( _xtos_set_vpri = 0x40000574 ); |
| 93 | PROVIDE ( _xtos_syscall_handler = 0x4000dbe4 ); |
| 94 | PROVIDE ( _xtos_unhandled_exception = 0x4000dc44 ); |
| 95 | PROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c ); |
| 96 | PROVIDE ( aes_decrypt = 0x400092d4 ); |
| 97 | PROVIDE ( aes_decrypt_deinit = 0x400092e4 ); |
| 98 | PROVIDE ( aes_decrypt_init = 0x40008ea4 ); |
| 99 | PROVIDE ( aes_unwrap = 0x40009410 ); |
| 100 | PROVIDE ( base64_decode = 0x40009648 ); |
| 101 | PROVIDE ( base64_encode = 0x400094fc ); |
| 102 | PROVIDE ( bzero = 0x4000de84 ); |
| 103 | PROVIDE ( cmd_parse = 0x40000814 ); |
| 104 | PROVIDE ( conv_str_decimal = 0x40000b24 ); |
| 105 | PROVIDE ( conv_str_hex = 0x40000cb8 ); |
| 106 | PROVIDE ( convert_para_str = 0x40000a60 ); |
| 107 | PROVIDE ( dtm_get_intr_mask = 0x400026d0 ); |
| 108 | PROVIDE ( dtm_params_init = 0x4000269c ); |
| 109 | PROVIDE ( dtm_set_intr_mask = 0x400026c8 ); |
| 110 | PROVIDE ( dtm_set_params = 0x400026dc ); |
| 111 | PROVIDE ( eprintf = 0x40001d14 ); |
| 112 | PROVIDE ( eprintf_init_buf = 0x40001cb8 ); |
| 113 | PROVIDE ( eprintf_to_host = 0x40001d48 ); |
| 114 | PROVIDE ( est_get_printf_buf_remain_len = 0x40002494 ); |
| 115 | PROVIDE ( est_reset_printf_buf_len = 0x4000249c ); |
| 116 | PROVIDE ( ets_bzero = 0x40002ae8 ); |
| 117 | PROVIDE ( ets_char2xdigit = 0x40002b74 ); |
| 118 | PROVIDE ( ets_delay_us = 0x40002ecc ); |
| 119 | PROVIDE ( ets_enter_sleep = 0x400027b8 ); |
| 120 | PROVIDE ( ets_external_printf = 0x40002578 ); |
| 121 | PROVIDE ( ets_get_cpu_frequency = 0x40002f0c ); |
| 122 | PROVIDE ( ets_getc = 0x40002bcc ); |
| 123 | PROVIDE ( ets_install_external_printf = 0x40002450 ); |
| 124 | PROVIDE ( ets_install_putc1 = 0x4000242c ); |
| 125 | PROVIDE ( ets_install_putc2 = 0x4000248c ); |
| 126 | PROVIDE ( ets_install_uart_printf = 0x40002438 ); |
| 127 | PROVIDE ( ets_intr_lock = 0x40000f74 ); |
| 128 | PROVIDE ( ets_intr_unlock = 0x40000f80 ); |
| 129 | PROVIDE ( ets_isr_attach = 0x40000f88 ); |
| 130 | PROVIDE ( ets_isr_mask = 0x40000f98 ); |
| 131 | PROVIDE ( ets_isr_unmask = 0x40000fa8 ); |
| 132 | PROVIDE ( ets_memcmp = 0x400018d4 ); |
| 133 | PROVIDE ( ets_memcpy = 0x400018b4 ); |
| 134 | PROVIDE ( ets_memmove = 0x400018c4 ); |
| 135 | PROVIDE ( ets_memset = 0x400018a4 ); |
Paul Sokolovsky | 97c2628 | 2015-12-21 23:04:11 +0200 | [diff] [blame] | 136 | PROVIDE ( _ets_post = 0x40000e24 ); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 137 | PROVIDE ( ets_printf = 0x400024cc ); |
| 138 | PROVIDE ( ets_putc = 0x40002be8 ); |
| 139 | PROVIDE ( ets_rtc_int_register = 0x40002a40 ); |
Paul Sokolovsky | 97c2628 | 2015-12-21 23:04:11 +0200 | [diff] [blame] | 140 | PROVIDE ( _ets_run = 0x40000e04 ); |
| 141 | PROVIDE ( _ets_set_idle_cb = 0x40000dc0 ); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 142 | PROVIDE ( ets_set_user_start = 0x40000fbc ); |
| 143 | PROVIDE ( ets_str2macaddr = 0x40002af8 ); |
| 144 | PROVIDE ( ets_strcmp = 0x40002aa8 ); |
| 145 | PROVIDE ( ets_strcpy = 0x40002a88 ); |
| 146 | PROVIDE ( ets_strlen = 0x40002ac8 ); |
| 147 | PROVIDE ( ets_strncmp = 0x40002ab8 ); |
| 148 | PROVIDE ( ets_strncpy = 0x40002a98 ); |
| 149 | PROVIDE ( ets_strstr = 0x40002ad8 ); |
Paul Sokolovsky | 97c2628 | 2015-12-21 23:04:11 +0200 | [diff] [blame] | 150 | PROVIDE ( _ets_task = 0x40000dd0 ); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 151 | PROVIDE ( ets_timer_arm = 0x40002cc4 ); |
| 152 | PROVIDE ( ets_timer_disarm = 0x40002d40 ); |
| 153 | PROVIDE ( ets_timer_done = 0x40002d80 ); |
| 154 | PROVIDE ( ets_timer_handler_isr = 0x40002da8 ); |
Paul Sokolovsky | 97c2628 | 2015-12-21 23:04:11 +0200 | [diff] [blame] | 155 | PROVIDE ( _ets_timer_init = 0x40002e68 ); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 156 | PROVIDE ( ets_timer_setfn = 0x40002c48 ); |
| 157 | PROVIDE ( ets_uart_printf = 0x40002544 ); |
| 158 | PROVIDE ( ets_update_cpu_frequency = 0x40002f04 ); |
| 159 | PROVIDE ( ets_vprintf = 0x40001f00 ); |
| 160 | PROVIDE ( ets_wdt_disable = 0x400030f0 ); |
| 161 | PROVIDE ( ets_wdt_enable = 0x40002fa0 ); |
| 162 | PROVIDE ( ets_wdt_get_mode = 0x40002f34 ); |
| 163 | PROVIDE ( ets_wdt_init = 0x40003170 ); |
| 164 | PROVIDE ( ets_wdt_restore = 0x40003158 ); |
| 165 | PROVIDE ( ets_write_char = 0x40001da0 ); |
| 166 | PROVIDE ( get_first_seg = 0x4000091c ); |
| 167 | PROVIDE ( gpio_init = 0x40004c50 ); |
| 168 | PROVIDE ( gpio_input_get = 0x40004cf0 ); |
| 169 | PROVIDE ( gpio_intr_ack = 0x40004dcc ); |
| 170 | PROVIDE ( gpio_intr_handler_register = 0x40004e28 ); |
| 171 | PROVIDE ( gpio_intr_pending = 0x40004d88 ); |
| 172 | PROVIDE ( gpio_intr_test = 0x40004efc ); |
| 173 | PROVIDE ( gpio_output_set = 0x40004cd0 ); |
| 174 | PROVIDE ( gpio_pin_intr_state_set = 0x40004d90 ); |
| 175 | PROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 ); |
| 176 | PROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 ); |
| 177 | PROVIDE ( gpio_register_get = 0x40004d5c ); |
| 178 | PROVIDE ( gpio_register_set = 0x40004d04 ); |
| 179 | PROVIDE ( hmac_md5 = 0x4000a2cc ); |
| 180 | PROVIDE ( hmac_md5_vector = 0x4000a160 ); |
| 181 | PROVIDE ( hmac_sha1 = 0x4000ba28 ); |
| 182 | PROVIDE ( hmac_sha1_vector = 0x4000b8b4 ); |
| 183 | PROVIDE ( lldesc_build_chain = 0x40004f40 ); |
| 184 | PROVIDE ( lldesc_num2link = 0x40005050 ); |
| 185 | PROVIDE ( lldesc_set_owner = 0x4000507c ); |
| 186 | PROVIDE ( main = 0x40000fec ); |
| 187 | PROVIDE ( md5_vector = 0x400097ac ); |
| 188 | PROVIDE ( mem_calloc = 0x40001c2c ); |
| 189 | PROVIDE ( mem_free = 0x400019e0 ); |
| 190 | PROVIDE ( mem_init = 0x40001998 ); |
| 191 | PROVIDE ( mem_malloc = 0x40001b40 ); |
| 192 | PROVIDE ( mem_realloc = 0x40001c6c ); |
| 193 | PROVIDE ( mem_trim = 0x40001a14 ); |
| 194 | PROVIDE ( mem_zalloc = 0x40001c58 ); |
| 195 | PROVIDE ( memcmp = 0x4000dea8 ); |
| 196 | PROVIDE ( memcpy = 0x4000df48 ); |
| 197 | PROVIDE ( memmove = 0x4000e04c ); |
| 198 | PROVIDE ( memset = 0x4000e190 ); |
| 199 | PROVIDE ( multofup = 0x400031c0 ); |
| 200 | PROVIDE ( pbkdf2_sha1 = 0x4000b840 ); |
| 201 | PROVIDE ( phy_get_romfuncs = 0x40006b08 ); |
| 202 | PROVIDE ( rand = 0x40000600 ); |
| 203 | PROVIDE ( rc4_skip = 0x4000dd68 ); |
| 204 | PROVIDE ( recv_packet = 0x40003d08 ); |
| 205 | PROVIDE ( remove_head_space = 0x40000a04 ); |
| 206 | PROVIDE ( rijndaelKeySetupDec = 0x40008dd0 ); |
| 207 | PROVIDE ( rijndaelKeySetupEnc = 0x40009300 ); |
| 208 | PROVIDE ( rom_abs_temp = 0x400060c0 ); |
| 209 | PROVIDE ( rom_ana_inf_gating_en = 0x40006b10 ); |
| 210 | PROVIDE ( rom_cal_tos_v50 = 0x40007a28 ); |
| 211 | PROVIDE ( rom_chip_50_set_channel = 0x40006f84 ); |
| 212 | PROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 ); |
| 213 | PROVIDE ( rom_chip_v5_enable_cca = 0x400060ec ); |
| 214 | PROVIDE ( rom_chip_v5_rx_init = 0x4000711c ); |
| 215 | PROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c ); |
| 216 | PROVIDE ( rom_chip_v5_tx_init = 0x4000718c ); |
| 217 | PROVIDE ( rom_dc_iq_est = 0x4000615c ); |
| 218 | PROVIDE ( rom_en_pwdet = 0x400061b8 ); |
| 219 | PROVIDE ( rom_get_bb_atten = 0x40006238 ); |
| 220 | PROVIDE ( rom_get_corr_power = 0x40006260 ); |
| 221 | PROVIDE ( rom_get_fm_sar_dout = 0x400062dc ); |
| 222 | PROVIDE ( rom_get_noisefloor = 0x40006394 ); |
| 223 | PROVIDE ( rom_get_power_db = 0x400063b0 ); |
| 224 | PROVIDE ( rom_i2c_readReg = 0x40007268 ); |
| 225 | PROVIDE ( rom_i2c_readReg_Mask = 0x4000729c ); |
| 226 | PROVIDE ( rom_i2c_writeReg = 0x400072d8 ); |
| 227 | PROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c ); |
| 228 | PROVIDE ( rom_iq_est_disable = 0x40006400 ); |
| 229 | PROVIDE ( rom_iq_est_enable = 0x40006430 ); |
| 230 | PROVIDE ( rom_linear_to_db = 0x40006484 ); |
| 231 | PROVIDE ( rom_mhz2ieee = 0x400065a4 ); |
| 232 | PROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 ); |
| 233 | PROVIDE ( rom_pbus_debugmode = 0x4000737c ); |
| 234 | PROVIDE ( rom_pbus_enter_debugmode = 0x40007410 ); |
| 235 | PROVIDE ( rom_pbus_exit_debugmode = 0x40007448 ); |
| 236 | PROVIDE ( rom_pbus_force_test = 0x4000747c ); |
| 237 | PROVIDE ( rom_pbus_rd = 0x400074d8 ); |
| 238 | PROVIDE ( rom_pbus_set_rxgain = 0x4000754c ); |
| 239 | PROVIDE ( rom_pbus_set_txgain = 0x40007610 ); |
| 240 | PROVIDE ( rom_pbus_workmode = 0x40007648 ); |
| 241 | PROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 ); |
| 242 | PROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc ); |
| 243 | PROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc ); |
| 244 | PROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 ); |
| 245 | PROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 ); |
| 246 | PROVIDE ( rom_phy_reset_req = 0x40007804 ); |
| 247 | PROVIDE ( rom_restart_cal = 0x4000781c ); |
| 248 | PROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 ); |
| 249 | PROVIDE ( rom_rfcal_rxiq = 0x4000804c ); |
| 250 | PROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 ); |
| 251 | PROVIDE ( rom_rfcal_txcap = 0x40008388 ); |
| 252 | PROVIDE ( rom_rfcal_txiq = 0x40008610 ); |
| 253 | PROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 ); |
| 254 | PROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 ); |
| 255 | PROVIDE ( rom_rfpll_reset = 0x40007868 ); |
| 256 | PROVIDE ( rom_rfpll_set_freq = 0x40007968 ); |
| 257 | PROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c ); |
| 258 | PROVIDE ( rom_rxiq_get_mis = 0x40006628 ); |
| 259 | PROVIDE ( rom_sar_init = 0x40006738 ); |
| 260 | PROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c ); |
| 261 | PROVIDE ( rom_set_channel_freq = 0x40006c50 ); |
| 262 | PROVIDE ( rom_set_loopback_gain = 0x400067c8 ); |
| 263 | PROVIDE ( rom_set_noise_floor = 0x40006830 ); |
| 264 | PROVIDE ( rom_set_rxclk_en = 0x40006550 ); |
| 265 | PROVIDE ( rom_set_txbb_atten = 0x40008c6c ); |
| 266 | PROVIDE ( rom_set_txclk_en = 0x4000650c ); |
| 267 | PROVIDE ( rom_set_txiq_cal = 0x40008d34 ); |
| 268 | PROVIDE ( rom_start_noisefloor = 0x40006874 ); |
| 269 | PROVIDE ( rom_start_tx_tone = 0x400068b4 ); |
| 270 | PROVIDE ( rom_stop_tx_tone = 0x4000698c ); |
| 271 | PROVIDE ( rom_tx_mac_disable = 0x40006a98 ); |
| 272 | PROVIDE ( rom_tx_mac_enable = 0x40006ad4 ); |
| 273 | PROVIDE ( rom_txtone_linear_pwr = 0x40006a1c ); |
| 274 | PROVIDE ( rom_write_rfpll_sdm = 0x400078dc ); |
| 275 | PROVIDE ( roundup2 = 0x400031b4 ); |
| 276 | PROVIDE ( rtc_enter_sleep = 0x40002870 ); |
| 277 | PROVIDE ( rtc_get_reset_reason = 0x400025e0 ); |
| 278 | PROVIDE ( rtc_intr_handler = 0x400029ec ); |
| 279 | PROVIDE ( rtc_set_sleep_mode = 0x40002668 ); |
| 280 | PROVIDE ( save_rxbcn_mactime = 0x400027a4 ); |
| 281 | PROVIDE ( save_tsf_us = 0x400027ac ); |
| 282 | PROVIDE ( send_packet = 0x40003c80 ); |
| 283 | PROVIDE ( sha1_prf = 0x4000ba48 ); |
| 284 | PROVIDE ( sha1_vector = 0x4000a2ec ); |
| 285 | PROVIDE ( sip_alloc_to_host_evt = 0x40005180 ); |
| 286 | PROVIDE ( sip_get_ptr = 0x400058a8 ); |
| 287 | PROVIDE ( sip_get_state = 0x40005668 ); |
| 288 | PROVIDE ( sip_init_attach = 0x4000567c ); |
| 289 | PROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c ); |
| 290 | PROVIDE ( sip_install_rx_data_cb = 0x4000545c ); |
| 291 | PROVIDE ( sip_post = 0x400050fc ); |
| 292 | PROVIDE ( sip_post_init = 0x400056c4 ); |
| 293 | PROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c ); |
| 294 | PROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 ); |
| 295 | PROVIDE ( sip_send = 0x40005808 ); |
| 296 | PROVIDE ( sip_to_host_chain_append = 0x40005864 ); |
| 297 | PROVIDE ( sip_to_host_evt_send_done = 0x40005234 ); |
| 298 | PROVIDE ( slc_add_credits = 0x400060ac ); |
| 299 | PROVIDE ( slc_enable = 0x40005d90 ); |
| 300 | PROVIDE ( slc_from_host_chain_fetch = 0x40005f24 ); |
| 301 | PROVIDE ( slc_from_host_chain_recycle = 0x40005e94 ); |
| 302 | PROVIDE ( slc_init_attach = 0x40005c50 ); |
| 303 | PROVIDE ( slc_init_credit = 0x4000608c ); |
| 304 | PROVIDE ( slc_pause_from_host = 0x40006014 ); |
| 305 | PROVIDE ( slc_reattach = 0x40005c1c ); |
| 306 | PROVIDE ( slc_resume_from_host = 0x4000603c ); |
| 307 | PROVIDE ( slc_select_tohost_gpio = 0x40005dc0 ); |
| 308 | PROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 ); |
| 309 | PROVIDE ( slc_send_to_host_chain = 0x40005de4 ); |
| 310 | PROVIDE ( slc_set_host_io_max_window = 0x40006068 ); |
| 311 | PROVIDE ( slc_to_host_chain_recycle = 0x40005f10 ); |
| 312 | PROVIDE ( software_reset = 0x4000264c ); |
| 313 | PROVIDE ( spi_flash_attach = 0x40004644 ); |
| 314 | PROVIDE ( srand = 0x400005f0 ); |
| 315 | PROVIDE ( strcmp = 0x4000bdc8 ); |
| 316 | PROVIDE ( strcpy = 0x4000bec8 ); |
| 317 | PROVIDE ( strlen = 0x4000bf4c ); |
| 318 | PROVIDE ( strncmp = 0x4000bfa8 ); |
| 319 | PROVIDE ( strncpy = 0x4000c0a0 ); |
| 320 | PROVIDE ( strstr = 0x4000e1e0 ); |
| 321 | PROVIDE ( timer_insert = 0x40002c64 ); |
| 322 | PROVIDE ( uartAttach = 0x4000383c ); |
| 323 | PROVIDE ( uart_baudrate_detect = 0x40003924 ); |
| 324 | PROVIDE ( uart_buff_switch = 0x400038a4 ); |
| 325 | PROVIDE ( uart_div_modify = 0x400039d8 ); |
| 326 | PROVIDE ( uart_rx_intr_handler = 0x40003bbc ); |
| 327 | PROVIDE ( uart_rx_one_char = 0x40003b8c ); |
| 328 | PROVIDE ( uart_rx_one_char_block = 0x40003b64 ); |
| 329 | PROVIDE ( uart_rx_readbuff = 0x40003ec8 ); |
| 330 | PROVIDE ( uart_tx_one_char = 0x40003b30 ); |
| 331 | PROVIDE ( wepkey_128 = 0x4000bc40 ); |
| 332 | PROVIDE ( wepkey_64 = 0x4000bb3c ); |
| 333 | PROVIDE ( xthal_bcopy = 0x40000688 ); |
| 334 | PROVIDE ( xthal_copy123 = 0x4000074c ); |
| 335 | PROVIDE ( xthal_get_ccompare = 0x4000dd4c ); |
| 336 | PROVIDE ( xthal_get_ccount = 0x4000dd38 ); |
| 337 | PROVIDE ( xthal_get_interrupt = 0x4000dd58 ); |
| 338 | PROVIDE ( xthal_get_intread = 0x4000dd58 ); |
| 339 | PROVIDE ( xthal_memcpy = 0x400006c4 ); |
| 340 | PROVIDE ( xthal_set_ccompare = 0x4000dd40 ); |
| 341 | PROVIDE ( xthal_set_intclear = 0x4000dd60 ); |
| 342 | PROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 ); |
| 343 | PROVIDE ( xthal_window_spill = 0x4000e324 ); |
| 344 | PROVIDE ( xthal_window_spill_nw = 0x4000e320 ); |
| 345 | |
| 346 | PROVIDE ( Te0 = 0x3fffccf0 ); |
Paul Sokolovsky | 609a9c6 | 2016-02-14 13:09:42 +0200 | [diff] [blame] | 347 | PROVIDE ( Td0 = 0x3fffd100 ); |
| 348 | PROVIDE ( Td4s = 0x3fffd500); |
| 349 | PROVIDE ( rcons = 0x3fffd0f0); |
Damien George | 075d597 | 2014-11-27 20:30:33 +0000 | [diff] [blame] | 350 | PROVIDE ( UartDev = 0x3fffde10 ); |
| 351 | PROVIDE ( flashchip = 0x3fffc714); |