blob: 30a94609672a2ab7d184125fe79c62a0a7e57b64 [file] [log] [blame]
Christian Königf2ba57b2013-04-08 12:41:29 +02001/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "radeon.h"
37#include "r600d.h"
38
39/* Firmware Names */
40#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
41#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
42#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
43#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
44
45MODULE_FIRMWARE(FIRMWARE_RV710);
46MODULE_FIRMWARE(FIRMWARE_CYPRESS);
47MODULE_FIRMWARE(FIRMWARE_SUMO);
48MODULE_FIRMWARE(FIRMWARE_TAHITI);
49
50int radeon_uvd_init(struct radeon_device *rdev)
51{
52 struct platform_device *pdev;
53 unsigned long bo_size;
54 const char *fw_name;
55 int i, r;
56
57 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0);
58 r = IS_ERR(pdev);
59 if (r) {
60 dev_err(rdev->dev, "radeon_uvd: Failed to register firmware\n");
61 return -EINVAL;
62 }
63
64 switch (rdev->family) {
65 case CHIP_RV710:
66 case CHIP_RV730:
67 case CHIP_RV740:
68 fw_name = FIRMWARE_RV710;
69 break;
70
71 case CHIP_CYPRESS:
72 case CHIP_HEMLOCK:
73 case CHIP_JUNIPER:
74 case CHIP_REDWOOD:
75 case CHIP_CEDAR:
76 fw_name = FIRMWARE_CYPRESS;
77 break;
78
79 case CHIP_SUMO:
80 case CHIP_SUMO2:
81 case CHIP_PALM:
82 case CHIP_CAYMAN:
83 case CHIP_BARTS:
84 case CHIP_TURKS:
85 case CHIP_CAICOS:
86 fw_name = FIRMWARE_SUMO;
87 break;
88
89 case CHIP_TAHITI:
90 case CHIP_VERDE:
91 case CHIP_PITCAIRN:
92 case CHIP_ARUBA:
93 fw_name = FIRMWARE_TAHITI;
94 break;
95
96 default:
97 return -EINVAL;
98 }
99
100 r = request_firmware(&rdev->uvd_fw, fw_name, &pdev->dev);
101 if (r) {
102 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
103 fw_name);
104 platform_device_unregister(pdev);
105 return r;
106 }
107
108 platform_device_unregister(pdev);
109
110 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) +
111 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
112 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
113 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
114 if (r) {
115 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
116 return r;
117 }
118
119 r = radeon_uvd_resume(rdev);
120 if (r)
121 return r;
122
123 memset(rdev->uvd.cpu_addr, 0, bo_size);
124 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
125
126 r = radeon_uvd_suspend(rdev);
127 if (r)
128 return r;
129
130 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
131 atomic_set(&rdev->uvd.handles[i], 0);
132 rdev->uvd.filp[i] = NULL;
133 }
134
135 return 0;
136}
137
138void radeon_uvd_fini(struct radeon_device *rdev)
139{
140 radeon_uvd_suspend(rdev);
141 radeon_bo_unref(&rdev->uvd.vcpu_bo);
142}
143
144int radeon_uvd_suspend(struct radeon_device *rdev)
145{
146 int r;
147
148 if (rdev->uvd.vcpu_bo == NULL)
149 return 0;
150
151 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
152 if (!r) {
153 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
154 radeon_bo_unpin(rdev->uvd.vcpu_bo);
155 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
156 }
157 return r;
158}
159
160int radeon_uvd_resume(struct radeon_device *rdev)
161{
162 int r;
163
164 if (rdev->uvd.vcpu_bo == NULL)
165 return -EINVAL;
166
167 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
168 if (r) {
169 radeon_bo_unref(&rdev->uvd.vcpu_bo);
170 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
171 return r;
172 }
173
174 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
175 &rdev->uvd.gpu_addr);
176 if (r) {
177 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
178 radeon_bo_unref(&rdev->uvd.vcpu_bo);
179 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
180 return r;
181 }
182
183 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
184 if (r) {
185 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
186 return r;
187 }
188
189 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
190
Christian Königec5891f2013-04-08 12:41:36 +0200191 radeon_set_uvd_clocks(rdev, 53300, 40000);
192
Christian Königf2ba57b2013-04-08 12:41:29 +0200193 return 0;
194}
195
196void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
197{
198 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
199 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
200}
201
202void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
203{
204 int i, r;
205 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
206 if (rdev->uvd.filp[i] == filp) {
207 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
208 struct radeon_fence *fence;
209
210 r = radeon_uvd_get_destroy_msg(rdev,
211 R600_RING_TYPE_UVD_INDEX, handle, &fence);
212 if (r) {
213 DRM_ERROR("Error destroying UVD (%d)!\n", r);
214 continue;
215 }
216
217 radeon_fence_wait(fence, false);
218 radeon_fence_unref(&fence);
219
220 rdev->uvd.filp[i] = NULL;
221 atomic_set(&rdev->uvd.handles[i], 0);
222 }
223 }
224}
225
226static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
227{
228 unsigned stream_type = msg[4];
229 unsigned width = msg[6];
230 unsigned height = msg[7];
231 unsigned dpb_size = msg[9];
232 unsigned pitch = msg[28];
233
234 unsigned width_in_mb = width / 16;
235 unsigned height_in_mb = ALIGN(height / 16, 2);
236
237 unsigned image_size, tmp, min_dpb_size;
238
239 image_size = width * height;
240 image_size += image_size / 2;
241 image_size = ALIGN(image_size, 1024);
242
243 switch (stream_type) {
244 case 0: /* H264 */
245
246 /* reference picture buffer */
247 min_dpb_size = image_size * 17;
248
249 /* macroblock context buffer */
250 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
251
252 /* IT surface buffer */
253 min_dpb_size += width_in_mb * height_in_mb * 32;
254 break;
255
256 case 1: /* VC1 */
257
258 /* reference picture buffer */
259 min_dpb_size = image_size * 3;
260
261 /* CONTEXT_BUFFER */
262 min_dpb_size += width_in_mb * height_in_mb * 128;
263
264 /* IT surface buffer */
265 min_dpb_size += width_in_mb * 64;
266
267 /* DB surface buffer */
268 min_dpb_size += width_in_mb * 128;
269
270 /* BP */
271 tmp = max(width_in_mb, height_in_mb);
272 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
273 break;
274
275 case 3: /* MPEG2 */
276
277 /* reference picture buffer */
278 min_dpb_size = image_size * 3;
279 break;
280
281 case 4: /* MPEG4 */
282
283 /* reference picture buffer */
284 min_dpb_size = image_size * 3;
285
286 /* CM */
287 min_dpb_size += width_in_mb * height_in_mb * 64;
288
289 /* IT surface buffer */
290 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
291 break;
292
293 default:
294 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
295 return -EINVAL;
296 }
297
298 if (width > pitch) {
299 DRM_ERROR("Invalid UVD decoding target pitch!\n");
300 return -EINVAL;
301 }
302
303 if (dpb_size < min_dpb_size) {
304 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
305 dpb_size, min_dpb_size);
306 return -EINVAL;
307 }
308
309 buf_sizes[0x1] = dpb_size;
310 buf_sizes[0x2] = image_size;
311 return 0;
312}
313
314static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
315 unsigned offset, unsigned buf_sizes[])
316{
317 int32_t *msg, msg_type, handle;
318 void *ptr;
319
320 int i, r;
321
322 if (offset & 0x3F) {
323 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
324 return -EINVAL;
325 }
326
327 r = radeon_bo_kmap(bo, &ptr);
328 if (r)
329 return r;
330
331 msg = ptr + offset;
332
333 msg_type = msg[1];
334 handle = msg[2];
335
336 if (handle == 0) {
337 DRM_ERROR("Invalid UVD handle!\n");
338 return -EINVAL;
339 }
340
341 if (msg_type == 1) {
342 /* it's a decode msg, calc buffer sizes */
343 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
344 radeon_bo_kunmap(bo);
345 if (r)
346 return r;
347
348 } else if (msg_type == 2) {
349 /* it's a destroy msg, free the handle */
350 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
351 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
352 radeon_bo_kunmap(bo);
353 return 0;
354 } else {
355 /* it's a create msg, no special handling needed */
356 radeon_bo_kunmap(bo);
357 }
358
359 /* create or decode, validate the handle */
360 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
361 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
362 return 0;
363 }
364
365 /* handle not found try to alloc a new one */
366 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
367 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
368 p->rdev->uvd.filp[i] = p->filp;
369 return 0;
370 }
371 }
372
373 DRM_ERROR("No more free UVD handles!\n");
374 return -EINVAL;
375}
376
377static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
378 int data0, int data1,
379 unsigned buf_sizes[])
380{
381 struct radeon_cs_chunk *relocs_chunk;
382 struct radeon_cs_reloc *reloc;
383 unsigned idx, cmd, offset;
384 uint64_t start, end;
385 int r;
386
387 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
388 offset = radeon_get_ib_value(p, data0);
389 idx = radeon_get_ib_value(p, data1);
390 if (idx >= relocs_chunk->length_dw) {
391 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
392 idx, relocs_chunk->length_dw);
393 return -EINVAL;
394 }
395
396 reloc = p->relocs_ptr[(idx / 4)];
397 start = reloc->lobj.gpu_offset;
398 end = start + radeon_bo_size(reloc->robj);
399 start += offset;
400
401 p->ib.ptr[data0] = start & 0xFFFFFFFF;
402 p->ib.ptr[data1] = start >> 32;
403
404 cmd = radeon_get_ib_value(p, p->idx) >> 1;
405
406 if (cmd < 0x4) {
407 if ((end - start) < buf_sizes[cmd]) {
408 DRM_ERROR("buffer to small (%d / %d)!\n",
409 (unsigned)(end - start), buf_sizes[cmd]);
410 return -EINVAL;
411 }
412
413 } else if (cmd != 0x100) {
414 DRM_ERROR("invalid UVD command %X!\n", cmd);
415 return -EINVAL;
416 }
417
418 if (cmd == 0) {
419 if (end & 0xFFFFFFFFF0000000) {
420 DRM_ERROR("msg buffer %LX-%LX out of 256MB segment!\n",
421 start, end);
422 return -EINVAL;
423 }
424
425 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
426 if (r)
427 return r;
428 }
429
430 if ((start & 0xFFFFFFFFF0000000) != (end & 0xFFFFFFFFF0000000)) {
431 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
432 start, end);
433 return -EINVAL;
434 }
435
436 return 0;
437}
438
439static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
440 struct radeon_cs_packet *pkt,
441 int *data0, int *data1,
442 unsigned buf_sizes[])
443{
444 int i, r;
445
446 p->idx++;
447 for (i = 0; i <= pkt->count; ++i) {
448 switch (pkt->reg + i*4) {
449 case UVD_GPCOM_VCPU_DATA0:
450 *data0 = p->idx;
451 break;
452 case UVD_GPCOM_VCPU_DATA1:
453 *data1 = p->idx;
454 break;
455 case UVD_GPCOM_VCPU_CMD:
456 r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
457 if (r)
458 return r;
459 break;
460 case UVD_ENGINE_CNTL:
461 break;
462 default:
463 DRM_ERROR("Invalid reg 0x%X!\n",
464 pkt->reg + i*4);
465 return -EINVAL;
466 }
467 p->idx++;
468 }
469 return 0;
470}
471
472int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
473{
474 struct radeon_cs_packet pkt;
475 int r, data0 = 0, data1 = 0;
476
477 /* minimum buffer sizes */
478 unsigned buf_sizes[] = {
479 [0x00000000] = 2048,
480 [0x00000001] = 32 * 1024 * 1024,
481 [0x00000002] = 2048 * 1152 * 3,
482 [0x00000003] = 2048,
483 };
484
485 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
486 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
487 p->chunks[p->chunk_ib_idx].length_dw);
488 return -EINVAL;
489 }
490
491 if (p->chunk_relocs_idx == -1) {
492 DRM_ERROR("No relocation chunk !\n");
493 return -EINVAL;
494 }
495
496
497 do {
498 r = radeon_cs_packet_parse(p, &pkt, p->idx);
499 if (r)
500 return r;
501 switch (pkt.type) {
502 case RADEON_PACKET_TYPE0:
503 r = radeon_uvd_cs_reg(p, &pkt, &data0,
504 &data1, buf_sizes);
505 if (r)
506 return r;
507 break;
508 case RADEON_PACKET_TYPE2:
509 p->idx += pkt.count + 2;
510 break;
511 default:
512 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
513 return -EINVAL;
514 }
515 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
516 return 0;
517}
518
519static int radeon_uvd_send_msg(struct radeon_device *rdev,
520 int ring, struct radeon_bo *bo,
521 struct radeon_fence **fence)
522{
523 struct ttm_validate_buffer tv;
524 struct list_head head;
525 struct radeon_ib ib;
526 uint64_t addr;
527 int i, r;
528
529 memset(&tv, 0, sizeof(tv));
530 tv.bo = &bo->tbo;
531
532 INIT_LIST_HEAD(&head);
533 list_add(&tv.head, &head);
534
535 r = ttm_eu_reserve_buffers(&head);
536 if (r)
537 return r;
538
539 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
540 radeon_uvd_force_into_uvd_segment(bo);
541
542 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
543 if (r) {
544 ttm_eu_backoff_reservation(&head);
545 return r;
546 }
547
548 r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
549 if (r) {
550 ttm_eu_backoff_reservation(&head);
551 return r;
552 }
553
554 addr = radeon_bo_gpu_offset(bo);
555 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
556 ib.ptr[1] = addr;
557 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
558 ib.ptr[3] = addr >> 32;
559 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
560 ib.ptr[5] = 0;
561 for (i = 6; i < 16; ++i)
562 ib.ptr[i] = PACKET2(0);
563 ib.length_dw = 16;
564
565 r = radeon_ib_schedule(rdev, &ib, NULL);
566 if (r) {
567 ttm_eu_backoff_reservation(&head);
568 return r;
569 }
570 ttm_eu_fence_buffer_objects(&head, ib.fence);
571
572 if (fence)
573 *fence = radeon_fence_ref(ib.fence);
574
575 radeon_ib_free(rdev, &ib);
576 radeon_bo_unref(&bo);
577 return 0;
578}
579
580/* multiple fence commands without any stream commands in between can
581 crash the vcpu so just try to emmit a dummy create/destroy msg to
582 avoid this */
583int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
584 uint32_t handle, struct radeon_fence **fence)
585{
586 struct radeon_bo *bo;
587 uint32_t *msg;
588 int r, i;
589
590 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
591 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
592 if (r)
593 return r;
594
595 r = radeon_bo_reserve(bo, false);
596 if (r) {
597 radeon_bo_unref(&bo);
598 return r;
599 }
600
601 r = radeon_bo_kmap(bo, (void **)&msg);
602 if (r) {
603 radeon_bo_unreserve(bo);
604 radeon_bo_unref(&bo);
605 return r;
606 }
607
608 /* stitch together an UVD create msg */
609 msg[0] = 0x00000de4;
610 msg[1] = 0x00000000;
611 msg[2] = handle;
612 msg[3] = 0x00000000;
613 msg[4] = 0x00000000;
614 msg[5] = 0x00000000;
615 msg[6] = 0x00000000;
616 msg[7] = 0x00000780;
617 msg[8] = 0x00000440;
618 msg[9] = 0x00000000;
619 msg[10] = 0x01b37000;
620 for (i = 11; i < 1024; ++i)
621 msg[i] = 0x0;
622
623 radeon_bo_kunmap(bo);
624 radeon_bo_unreserve(bo);
625
626 return radeon_uvd_send_msg(rdev, ring, bo, fence);
627}
628
629int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
630 uint32_t handle, struct radeon_fence **fence)
631{
632 struct radeon_bo *bo;
633 uint32_t *msg;
634 int r, i;
635
636 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
637 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
638 if (r)
639 return r;
640
641 r = radeon_bo_reserve(bo, false);
642 if (r) {
643 radeon_bo_unref(&bo);
644 return r;
645 }
646
647 r = radeon_bo_kmap(bo, (void **)&msg);
648 if (r) {
649 radeon_bo_unreserve(bo);
650 radeon_bo_unref(&bo);
651 return r;
652 }
653
654 /* stitch together an UVD destroy msg */
655 msg[0] = 0x00000de4;
656 msg[1] = 0x00000002;
657 msg[2] = handle;
658 msg[3] = 0x00000000;
659 for (i = 4; i < 1024; ++i)
660 msg[i] = 0x0;
661
662 radeon_bo_kunmap(bo);
663 radeon_bo_unreserve(bo);
664
665 return radeon_uvd_send_msg(rdev, ring, bo, fence);
666}