blob: 252067bba2d91bbdeb162dd168520f415b59db4c [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090028#include <linux/slab.h>
Jerome Glisse3ce0a232009-09-08 10:10:24 +100029#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040032#include <linux/module.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
34#include <drm/radeon_drm.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000036#include "radeon_asic.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100037#include "radeon_mode.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100038#include "r600d.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100039#include "atom.h"
Jerome Glissed39c3b82009-09-28 18:34:43 +020040#include "avivod.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020041
Jerome Glisse3ce0a232009-09-08 10:10:24 +100042#define PFP_UCODE_SIZE 576
43#define PM4_UCODE_SIZE 1792
Alex Deucherd8f60cf2009-12-01 13:43:46 -050044#define RLC_UCODE_SIZE 768
Jerome Glisse3ce0a232009-09-08 10:10:24 +100045#define R700_PFP_UCODE_SIZE 848
46#define R700_PM4_UCODE_SIZE 1360
Alex Deucherd8f60cf2009-12-01 13:43:46 -050047#define R700_RLC_UCODE_SIZE 1024
Alex Deucherfe251e22010-03-24 13:36:43 -040048#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
Alex Deucher45f9a392010-03-24 13:55:51 -040050#define EVERGREEN_RLC_UCODE_SIZE 768
Alex Deucher12727802011-03-02 20:07:32 -050051#define CAYMAN_RLC_UCODE_SIZE 1024
Alex Deucherc420c742012-03-20 17:18:39 -040052#define ARUBA_RLC_UCODE_SIZE 1536
Jerome Glisse3ce0a232009-09-08 10:10:24 +100053
54/* Firmware Names */
55MODULE_FIRMWARE("radeon/R600_pfp.bin");
56MODULE_FIRMWARE("radeon/R600_me.bin");
57MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58MODULE_FIRMWARE("radeon/RV610_me.bin");
59MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60MODULE_FIRMWARE("radeon/RV630_me.bin");
61MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62MODULE_FIRMWARE("radeon/RV620_me.bin");
63MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64MODULE_FIRMWARE("radeon/RV635_me.bin");
65MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66MODULE_FIRMWARE("radeon/RV670_me.bin");
67MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68MODULE_FIRMWARE("radeon/RS780_me.bin");
69MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70MODULE_FIRMWARE("radeon/RV770_me.bin");
71MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72MODULE_FIRMWARE("radeon/RV730_me.bin");
73MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74MODULE_FIRMWARE("radeon/RV710_me.bin");
Alex Deucherd8f60cf2009-12-01 13:43:46 -050075MODULE_FIRMWARE("radeon/R600_rlc.bin");
76MODULE_FIRMWARE("radeon/R700_rlc.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -040077MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78MODULE_FIRMWARE("radeon/CEDAR_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -040079MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -040080MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -040082MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -040083MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -040085MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
Dave Airliea7433742010-04-09 15:31:09 +100086MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
Alex Deucherfe251e22010-03-24 13:36:43 -040087MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
Alex Deucher45f9a392010-03-24 13:55:51 -040088MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
Alex Deucher439bd6c2010-11-22 17:56:31 -050089MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90MODULE_FIRMWARE("radeon/PALM_me.bin");
91MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
Alex Deucherd5c5a722011-05-31 15:42:48 -040092MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93MODULE_FIRMWARE("radeon/SUMO_me.bin");
94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95MODULE_FIRMWARE("radeon/SUMO2_me.bin");
Jerome Glisse3ce0a232009-09-08 10:10:24 +100096
97int r600_debugfs_mc_info_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098
Jerome Glisse1a029b72009-10-06 19:04:30 +020099/* r600,rv610,rv630,rv620,rv635,rv670 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200100int r600_mc_wait_for_idle(struct radeon_device *rdev);
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400101static void r600_gpu_init(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000102void r600_fini(struct radeon_device *rdev);
Alex Deucher45f9a392010-03-24 13:55:51 -0400103void r600_irq_disable(struct radeon_device *rdev);
Alex Deucher9e46a482011-01-06 18:49:35 -0500104static void r600_pcie_gen2_enable(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200105
Alex Deucher21a81222010-07-02 12:58:16 -0400106/* get temperature in millidegrees */
Alex Deucher20d391d2011-02-01 16:12:34 -0500107int rv6xx_get_temp(struct radeon_device *rdev)
Alex Deucher21a81222010-07-02 12:58:16 -0400108{
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
110 ASIC_T_SHIFT;
Alex Deucher20d391d2011-02-01 16:12:34 -0500111 int actual_temp = temp & 0xff;
Alex Deucher21a81222010-07-02 12:58:16 -0400112
Alex Deucher20d391d2011-02-01 16:12:34 -0500113 if (temp & 0x100)
114 actual_temp -= 256;
115
116 return actual_temp * 1000;
Alex Deucher21a81222010-07-02 12:58:16 -0400117}
118
Alex Deucherce8f5372010-05-07 15:10:16 -0400119void r600_pm_get_dynpm_state(struct radeon_device *rdev)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400120{
121 int i;
122
Alex Deucherce8f5372010-05-07 15:10:16 -0400123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400125
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
129
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
132
Alex Deucherce8f5372010-05-07 15:10:16 -0400133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400137 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400138 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400139 case DYNPM_ACTION_DOWNCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
Alex Deucherce8f5372010-05-07 15:10:16 -0400142 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400143 } else {
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
Alex Deucherd7311172010-05-03 01:13:14 -0400146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400147 continue;
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
151 break;
152 } else {
153 rdev->pm.requested_power_state_index = i;
154 break;
155 }
156 }
Alex Deucher773c3fa2010-06-25 16:21:27 -0400157 } else {
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
161 else
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
164 }
Alex Deuchera48b9b42010-04-22 14:03:55 -0400165 }
166 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherd7311172010-05-03 01:13:14 -0400167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
173 }
Alex Deuchera48b9b42010-04-22 14:03:55 -0400174 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400175 case DYNPM_ACTION_UPCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
Alex Deucherce8f5372010-05-07 15:10:16 -0400178 rdev->pm.dynpm_can_upclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400179 } else {
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
Alex Deucherd7311172010-05-03 01:13:14 -0400182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400183 continue;
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
187 break;
188 } else {
189 rdev->pm.requested_power_state_index = i;
190 break;
191 }
192 }
193 } else
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
196 }
197 rdev->pm.requested_clock_mode_index = 0;
198 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400199 case DYNPM_ACTION_DEFAULT:
Alex Deucher58e21df2010-03-22 13:31:08 -0400200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400202 rdev->pm.dynpm_can_upclock = false;
Alex Deucher58e21df2010-03-22 13:31:08 -0400203 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400204 case DYNPM_ACTION_NONE:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400205 default:
206 DRM_ERROR("Requested mode for not defined action\n");
207 return;
208 }
209 } else {
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
Alex Deucherd7311172010-05-03 01:13:14 -0400217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400218 continue;
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
222 break;
223 }
224 }
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
228 } else
229 rdev->pm.requested_power_state_index = 1;
230
Alex Deucherce8f5372010-05-07 15:10:16 -0400231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400233 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400234 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400235 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400236 case DYNPM_ACTION_DOWNCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400240 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400241 } else
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
244 } else {
245 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400246 rdev->pm.dynpm_can_downclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400247 }
Alex Deucherd7311172010-05-03 01:13:14 -0400248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
254 }
Alex Deuchera48b9b42010-04-22 14:03:55 -0400255 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400256 case DYNPM_ACTION_UPCLOCK:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
Alex Deucherce8f5372010-05-07 15:10:16 -0400261 rdev->pm.dynpm_can_upclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400262 } else
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
265 } else {
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
Alex Deucherce8f5372010-05-07 15:10:16 -0400268 rdev->pm.dynpm_can_upclock = false;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400269 }
270 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400271 case DYNPM_ACTION_DEFAULT:
Alex Deucher58e21df2010-03-22 13:31:08 -0400272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400274 rdev->pm.dynpm_can_upclock = false;
Alex Deucher58e21df2010-03-22 13:31:08 -0400275 break;
Alex Deucherce8f5372010-05-07 15:10:16 -0400276 case DYNPM_ACTION_NONE:
Alex Deuchera48b9b42010-04-22 14:03:55 -0400277 default:
278 DRM_ERROR("Requested mode for not defined action\n");
279 return;
280 }
281 }
282
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
Alex Deucherce8a3eb2010-05-07 16:58:27 -0400284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
289 pcie_lanes);
Alex Deuchera48b9b42010-04-22 14:03:55 -0400290}
291
Alex Deucherce8f5372010-05-07 15:10:16 -0400292void rs780_pm_init_profile(struct radeon_device *rdev)
293{
294 if (rdev->pm.num_power_states == 2) {
295 /* default */
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 /* low sh */
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400305 /* mid sh */
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400310 /* high sh */
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 /* low mh */
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400320 /* mid mh */
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400325 /* high mh */
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
331 /* default */
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
336 /* low sh */
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400341 /* mid sh */
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400346 /* high sh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351 /* low mh */
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400356 /* mid mh */
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400361 /* high mh */
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
366 } else {
367 /* default */
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
372 /* low sh */
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400377 /* mid sh */
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400382 /* high sh */
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
387 /* low mh */
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400392 /* mid mh */
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400397 /* high mh */
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
402 }
403}
404
405void r600_pm_init_profile(struct radeon_device *rdev)
406{
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400407 int idx;
408
Alex Deucherce8f5372010-05-07 15:10:16 -0400409 if (rdev->family == CHIP_R600) {
410 /* XXX */
411 /* default */
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400416 /* low sh */
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400421 /* mid sh */
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400426 /* high sh */
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400431 /* low mh */
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400436 /* mid mh */
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400441 /* high mh */
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
Alex Deucher4bff5172010-05-17 19:41:26 -0400445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherce8f5372010-05-07 15:10:16 -0400446 } else {
447 if (rdev->pm.num_power_states < 4) {
448 /* default */
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
453 /* low sh */
Alex Deucherce8f5372010-05-07 15:10:16 -0400454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
458 /* mid sh */
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
Alex Deucherce8f5372010-05-07 15:10:16 -0400463 /* high sh */
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
468 /* low mh */
Alex Deucher4bff5172010-05-17 19:41:26 -0400469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
Alex Deucherce8f5372010-05-07 15:10:16 -0400471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
473 /* low mh */
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
Alex Deucherce8f5372010-05-07 15:10:16 -0400478 /* high mh */
Alex Deucher4bff5172010-05-17 19:41:26 -0400479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
483 } else {
484 /* default */
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
489 /* low sh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492 else
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400498 /* mid sh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
Alex Deucher4bff5172010-05-17 19:41:26 -0400503 /* high sh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
Alex Deucher4bff5172010-05-17 19:41:26 -0400507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
509 /* low mh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
512 else
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
Alex Deucherc9e75b22010-06-02 17:56:01 -0400518 /* mid mh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
Alex Deucher4bff5172010-05-17 19:41:26 -0400523 /* high mh */
Alex Deucherbbe26ff2011-11-04 10:09:42 -0400524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
Alex Deucherce8f5372010-05-07 15:10:16 -0400527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
529 }
530 }
Alex Deucherbae6b5622010-04-22 13:38:05 -0400531}
532
Alex Deucher49e02b72010-04-23 17:57:27 -0400533void r600_pm_misc(struct radeon_device *rdev)
534{
Rafał Miłeckia081a9d2010-06-07 18:20:25 -0400535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
Alex Deucher7ac9aa52010-05-27 19:25:54 -0400539
Alex Deucher4d601732010-06-07 18:15:18 -0400540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
Alex Deuchera377e182011-06-20 13:00:31 -0400541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
543 return;
Alex Deucher4d601732010-06-07 18:15:18 -0400544 if (voltage->voltage != rdev->pm.current_vddc) {
Alex Deucher8a83ec52011-04-12 14:49:23 -0400545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
Alex Deucher4d601732010-06-07 18:15:18 -0400546 rdev->pm.current_vddc = voltage->voltage;
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
Alex Deucher4d601732010-06-07 18:15:18 -0400548 }
549 }
Alex Deucher49e02b72010-04-23 17:57:27 -0400550}
551
Alex Deucherdef9ba92010-04-22 12:39:58 -0400552bool r600_gui_idle(struct radeon_device *rdev)
553{
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
555 return false;
556 else
557 return true;
558}
559
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500560/* hpd for digital panel detect/disconnect */
561bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562{
563 bool connected = false;
564
565 if (ASIC_IS_DCE3(rdev)) {
566 switch (hpd) {
567 case RADEON_HPD_1:
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
569 connected = true;
570 break;
571 case RADEON_HPD_2:
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
573 connected = true;
574 break;
575 case RADEON_HPD_3:
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
577 connected = true;
578 break;
579 case RADEON_HPD_4:
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
581 connected = true;
582 break;
583 /* DCE 3.2 */
584 case RADEON_HPD_5:
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
586 connected = true;
587 break;
588 case RADEON_HPD_6:
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
590 connected = true;
591 break;
592 default:
593 break;
594 }
595 } else {
596 switch (hpd) {
597 case RADEON_HPD_1:
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
599 connected = true;
600 break;
601 case RADEON_HPD_2:
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
603 connected = true;
604 break;
605 case RADEON_HPD_3:
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
607 connected = true;
608 break;
609 default:
610 break;
611 }
612 }
613 return connected;
614}
615
616void r600_hpd_set_polarity(struct radeon_device *rdev,
Alex Deucher429770b2009-12-04 15:26:55 -0500617 enum radeon_hpd_id hpd)
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500618{
619 u32 tmp;
620 bool connected = r600_hpd_sense(rdev, hpd);
621
622 if (ASIC_IS_DCE3(rdev)) {
623 switch (hpd) {
624 case RADEON_HPD_1:
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
626 if (connected)
627 tmp &= ~DC_HPDx_INT_POLARITY;
628 else
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
631 break;
632 case RADEON_HPD_2:
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
634 if (connected)
635 tmp &= ~DC_HPDx_INT_POLARITY;
636 else
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
639 break;
640 case RADEON_HPD_3:
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
642 if (connected)
643 tmp &= ~DC_HPDx_INT_POLARITY;
644 else
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
647 break;
648 case RADEON_HPD_4:
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
650 if (connected)
651 tmp &= ~DC_HPDx_INT_POLARITY;
652 else
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
655 break;
656 case RADEON_HPD_5:
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
658 if (connected)
659 tmp &= ~DC_HPDx_INT_POLARITY;
660 else
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
663 break;
664 /* DCE 3.2 */
665 case RADEON_HPD_6:
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
667 if (connected)
668 tmp &= ~DC_HPDx_INT_POLARITY;
669 else
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
672 break;
673 default:
674 break;
675 }
676 } else {
677 switch (hpd) {
678 case RADEON_HPD_1:
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
680 if (connected)
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
682 else
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
685 break;
686 case RADEON_HPD_2:
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 else
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
693 break;
694 case RADEON_HPD_3:
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
696 if (connected)
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 else
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
701 break;
702 default:
703 break;
704 }
705 }
706}
707
708void r600_hpd_init(struct radeon_device *rdev)
709{
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
Christian Koenigfb982572012-05-17 01:33:30 +0200712 unsigned enable = 0;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500713
Alex Deucher64912e92011-11-03 11:21:39 -0400714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
715 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500716
Jerome Glisse455c89b2012-05-04 11:06:22 -0400717 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
718 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
719 /* don't try to enable hpd on eDP or LVDS avoid breaking the
720 * aux dp channel on imac and help (but not completely fix)
721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
722 */
723 continue;
724 }
Alex Deucher64912e92011-11-03 11:21:39 -0400725 if (ASIC_IS_DCE3(rdev)) {
726 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
727 if (ASIC_IS_DCE32(rdev))
728 tmp |= DC_HPDx_EN;
729
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500730 switch (radeon_connector->hpd.hpd) {
731 case RADEON_HPD_1:
732 WREG32(DC_HPD1_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500733 break;
734 case RADEON_HPD_2:
735 WREG32(DC_HPD2_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500736 break;
737 case RADEON_HPD_3:
738 WREG32(DC_HPD3_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500739 break;
740 case RADEON_HPD_4:
741 WREG32(DC_HPD4_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500742 break;
743 /* DCE 3.2 */
744 case RADEON_HPD_5:
745 WREG32(DC_HPD5_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500746 break;
747 case RADEON_HPD_6:
748 WREG32(DC_HPD6_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500749 break;
750 default:
751 break;
752 }
Alex Deucher64912e92011-11-03 11:21:39 -0400753 } else {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500754 switch (radeon_connector->hpd.hpd) {
755 case RADEON_HPD_1:
756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500757 break;
758 case RADEON_HPD_2:
759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500760 break;
761 case RADEON_HPD_3:
762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500763 break;
764 default:
765 break;
766 }
767 }
Christian Koenigfb982572012-05-17 01:33:30 +0200768 enable |= 1 << radeon_connector->hpd.hpd;
Alex Deucher64912e92011-11-03 11:21:39 -0400769 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500770 }
Christian Koenigfb982572012-05-17 01:33:30 +0200771 radeon_irq_kms_enable_hpd(rdev, enable);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500772}
773
774void r600_hpd_fini(struct radeon_device *rdev)
775{
776 struct drm_device *dev = rdev->ddev;
777 struct drm_connector *connector;
Christian Koenigfb982572012-05-17 01:33:30 +0200778 unsigned disable = 0;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500779
Christian Koenigfb982572012-05-17 01:33:30 +0200780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
782 if (ASIC_IS_DCE3(rdev)) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500783 switch (radeon_connector->hpd.hpd) {
784 case RADEON_HPD_1:
785 WREG32(DC_HPD1_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500786 break;
787 case RADEON_HPD_2:
788 WREG32(DC_HPD2_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500789 break;
790 case RADEON_HPD_3:
791 WREG32(DC_HPD3_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500792 break;
793 case RADEON_HPD_4:
794 WREG32(DC_HPD4_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500795 break;
796 /* DCE 3.2 */
797 case RADEON_HPD_5:
798 WREG32(DC_HPD5_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500799 break;
800 case RADEON_HPD_6:
801 WREG32(DC_HPD6_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500802 break;
803 default:
804 break;
805 }
Christian Koenigfb982572012-05-17 01:33:30 +0200806 } else {
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500807 switch (radeon_connector->hpd.hpd) {
808 case RADEON_HPD_1:
809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500810 break;
811 case RADEON_HPD_2:
812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500813 break;
814 case RADEON_HPD_3:
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500816 break;
817 default:
818 break;
819 }
820 }
Christian Koenigfb982572012-05-17 01:33:30 +0200821 disable |= 1 << radeon_connector->hpd.hpd;
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500822 }
Christian Koenigfb982572012-05-17 01:33:30 +0200823 radeon_irq_kms_disable_hpd(rdev, disable);
Alex Deuchere0df1ac2009-12-04 15:12:21 -0500824}
825
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200826/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000827 * R600 PCIE GART
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200828 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000829void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200830{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000831 unsigned i;
832 u32 tmp;
833
Dave Airlie2e98f102010-02-15 15:54:45 +1000834 /* flush hdp cache so updates hit vram */
Alex Deucherf3886f82010-12-08 10:05:34 -0500835 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
836 !(rdev->flags & RADEON_IS_AGP)) {
Jerome Glissec9a1be92011-11-03 11:16:49 -0400837 void __iomem *ptr = (void *)rdev->gart.ptr;
Alex Deucher812d0462010-07-26 18:51:53 -0400838 u32 tmp;
839
840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
Alex Deucherf3886f82010-12-08 10:05:34 -0500842 * This seems to cause problems on some AGP cards. Just use the old
843 * method for them.
Alex Deucher812d0462010-07-26 18:51:53 -0400844 */
845 WREG32(HDP_DEBUG1, 0);
846 tmp = readl((void __iomem *)ptr);
847 } else
848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
Dave Airlie2e98f102010-02-15 15:54:45 +1000849
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
853 for (i = 0; i < rdev->usec_timeout; i++) {
854 /* read MC_STATUS */
855 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
856 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
857 if (tmp == 2) {
858 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
859 return;
860 }
861 if (tmp) {
862 return;
863 }
864 udelay(1);
865 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200866}
867
Jerome Glisse4aac0472009-09-14 18:29:49 +0200868int r600_pcie_gart_init(struct radeon_device *rdev)
869{
870 int r;
871
Jerome Glissec9a1be92011-11-03 11:16:49 -0400872 if (rdev->gart.robj) {
Joe Perchesfce7d612010-10-30 21:08:30 +0000873 WARN(1, "R600 PCIE GART already initialized\n");
Jerome Glisse4aac0472009-09-14 18:29:49 +0200874 return 0;
875 }
876 /* Initialize common gart structure */
877 r = radeon_gart_init(rdev);
878 if (r)
879 return r;
880 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
881 return radeon_gart_table_vram_alloc(rdev);
882}
883
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400884static int r600_pcie_gart_enable(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200885{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000886 u32 tmp;
887 int r, i;
888
Jerome Glissec9a1be92011-11-03 11:16:49 -0400889 if (rdev->gart.robj == NULL) {
Jerome Glisse4aac0472009-09-14 18:29:49 +0200890 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
891 return -EINVAL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000892 }
Jerome Glisse4aac0472009-09-14 18:29:49 +0200893 r = radeon_gart_table_vram_pin(rdev);
894 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000895 return r;
Dave Airlie82568562010-02-05 16:00:07 +1000896 radeon_gart_restore(rdev);
Dave Airliebc1a6312009-09-15 11:07:52 +1000897
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000898 /* Setup L2 cache */
899 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
901 EFFECTIVE_L2_QUEUE_SIZE(7));
902 WREG32(VM_L2_CNTL2, 0);
903 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
904 /* Setup TLB control */
905 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
906 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
908 ENABLE_WAIT_L2_QUERY;
909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
926 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
929 (u32)(rdev->dummy_page.addr >> 12));
930 for (i = 1; i < 7; i++)
931 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
932
933 r600_pcie_gart_tlb_flush(rdev);
Tormod Voldenfcf4de52011-08-31 21:54:07 +0000934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
935 (unsigned)(rdev->mc.gtt_size >> 20),
936 (unsigned long long)rdev->gart.table_addr);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000937 rdev->gart.ready = true;
938 return 0;
939}
940
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400941static void r600_pcie_gart_disable(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000942{
943 u32 tmp;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400944 int i;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000945
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000946 /* Disable all tables */
947 for (i = 0; i < 7; i++)
948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
949
950 /* Disable L2 cache */
951 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
952 EFFECTIVE_L2_QUEUE_SIZE(7));
953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup L1 TLB control */
955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
956 ENABLE_WAIT_L2_QUERY;
957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400971 radeon_gart_table_vram_unpin(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200972}
973
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400974static void r600_pcie_gart_fini(struct radeon_device *rdev)
Jerome Glisse4aac0472009-09-14 18:29:49 +0200975{
Jerome Glissef9274562010-03-17 14:44:29 +0000976 radeon_gart_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200977 r600_pcie_gart_disable(rdev);
978 radeon_gart_table_vram_free(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200979}
980
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400981static void r600_agp_enable(struct radeon_device *rdev)
Jerome Glisse1a029b72009-10-06 19:04:30 +0200982{
983 u32 tmp;
984 int i;
985
986 /* Setup L2 cache */
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
989 EFFECTIVE_L2_QUEUE_SIZE(7));
990 WREG32(VM_L2_CNTL2, 0);
991 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
992 /* Setup TLB control */
993 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
994 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
996 ENABLE_WAIT_L2_QUERY;
997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011 for (i = 0; i < 7; i++)
1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1013}
1014
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001015int r600_mc_wait_for_idle(struct radeon_device *rdev)
1016{
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001017 unsigned i;
1018 u32 tmp;
1019
1020 for (i = 0; i < rdev->usec_timeout; i++) {
1021 /* read MC_STATUS */
1022 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1023 if (!tmp)
1024 return 0;
1025 udelay(1);
1026 }
1027 return -1;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001028}
1029
Jerome Glissea3c19452009-10-01 18:02:13 +02001030static void r600_mc_program(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001031{
Jerome Glissea3c19452009-10-01 18:02:13 +02001032 struct rv515_mc_save save;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001033 u32 tmp;
1034 int i, j;
1035
1036 /* Initialize HDP */
1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038 WREG32((0x2c14 + j), 0x00000000);
1039 WREG32((0x2c18 + j), 0x00000000);
1040 WREG32((0x2c1c + j), 0x00000000);
1041 WREG32((0x2c20 + j), 0x00000000);
1042 WREG32((0x2c24 + j), 0x00000000);
1043 }
1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045
Jerome Glissea3c19452009-10-01 18:02:13 +02001046 rv515_mc_stop(rdev, &save);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001047 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +02001048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001049 }
Jerome Glissea3c19452009-10-01 18:02:13 +02001050 /* Lockout access through VGA aperture (doesn't exist before R600) */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001052 /* Update configuration */
Jerome Glisse1a029b72009-10-06 19:04:30 +02001053 if (rdev->flags & RADEON_IS_AGP) {
1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055 /* VRAM before AGP */
1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057 rdev->mc.vram_start >> 12);
1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059 rdev->mc.gtt_end >> 12);
1060 } else {
1061 /* VRAM after AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063 rdev->mc.gtt_start >> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065 rdev->mc.vram_end >> 12);
1066 }
1067 } else {
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070 }
Alex Deucher16cdf042011-10-28 10:30:02 -04001071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
Jerome Glisse1a029b72009-10-06 19:04:30 +02001072 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001073 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074 WREG32(MC_VM_FB_LOCATION, tmp);
1075 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
Jerome Glisse46fcd2b2010-06-03 19:34:48 +02001077 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001078 if (rdev->flags & RADEON_IS_AGP) {
Jerome Glisse1a029b72009-10-06 19:04:30 +02001079 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001081 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082 } else {
1083 WREG32(MC_VM_AGP_BASE, 0);
1084 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001087 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +02001088 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001089 }
Jerome Glissea3c19452009-10-01 18:02:13 +02001090 rv515_mc_resume(rdev, &save);
Dave Airlie698443d2009-09-18 14:16:38 +10001091 /* we need to own VRAM, so turn off the VGA renderer here
1092 * to stop it overwriting our objects */
Jerome Glissed39c3b82009-09-28 18:34:43 +02001093 rv515_vga_render_disable(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001094}
1095
Jerome Glissed594e462010-02-17 21:54:29 +00001096/**
1097 * r600_vram_gtt_location - try to find VRAM & GTT location
1098 * @rdev: radeon device structure holding all necessary informations
1099 * @mc: memory controller structure holding memory informations
1100 *
1101 * Function will place try to place VRAM at same place as in CPU (PCI)
1102 * address space as some GPU seems to have issue when we reprogram at
1103 * different address space.
1104 *
1105 * If there is not enough space to fit the unvisible VRAM after the
1106 * aperture then we limit the VRAM size to the aperture.
1107 *
1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109 * them to be in one from GPU point of view so that we can program GPU to
1110 * catch access outside them (weird GPU policy see ??).
1111 *
1112 * This function will never fails, worst case are limiting VRAM or GTT.
1113 *
1114 * Note: GTT start, end, size should be initialized before calling this
1115 * function on AGP platform.
1116 */
Alex Deucher0ef0c1f2010-11-22 17:56:26 -05001117static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
Jerome Glissed594e462010-02-17 21:54:29 +00001118{
1119 u64 size_bf, size_af;
1120
1121 if (mc->mc_vram_size > 0xE0000000) {
1122 /* leave room for at least 512M GTT */
1123 dev_warn(rdev->dev, "limiting VRAM\n");
1124 mc->real_vram_size = 0xE0000000;
1125 mc->mc_vram_size = 0xE0000000;
1126 }
1127 if (rdev->flags & RADEON_IS_AGP) {
1128 size_bf = mc->gtt_start;
Jerome Glissedfc6ae52012-04-17 16:51:38 -04001129 size_af = 0xFFFFFFFF - mc->gtt_end;
Jerome Glissed594e462010-02-17 21:54:29 +00001130 if (size_bf > size_af) {
1131 if (mc->mc_vram_size > size_bf) {
1132 dev_warn(rdev->dev, "limiting VRAM\n");
1133 mc->real_vram_size = size_bf;
1134 mc->mc_vram_size = size_bf;
1135 }
1136 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137 } else {
1138 if (mc->mc_vram_size > size_af) {
1139 dev_warn(rdev->dev, "limiting VRAM\n");
1140 mc->real_vram_size = size_af;
1141 mc->mc_vram_size = size_af;
1142 }
Jerome Glissedfc6ae52012-04-17 16:51:38 -04001143 mc->vram_start = mc->gtt_end + 1;
Jerome Glissed594e462010-02-17 21:54:29 +00001144 }
1145 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147 mc->mc_vram_size >> 20, mc->vram_start,
1148 mc->vram_end, mc->real_vram_size >> 20);
1149 } else {
1150 u64 base = 0;
Alex Deucher8961d522010-12-03 14:37:22 -05001151 if (rdev->flags & RADEON_IS_IGP) {
1152 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1153 base <<= 24;
1154 }
Jerome Glissed594e462010-02-17 21:54:29 +00001155 radeon_vram_location(rdev, &rdev->mc, base);
Alex Deucher8d369bb2010-07-15 10:51:10 -04001156 rdev->mc.gtt_base_align = 0;
Jerome Glissed594e462010-02-17 21:54:29 +00001157 radeon_gtt_location(rdev, mc);
1158 }
1159}
1160
Lauri Kasanen1109ca02012-08-31 13:43:50 -04001161static int r600_mc_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001162{
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001163 u32 tmp;
Alex Deucher5885b7a2009-10-19 17:23:33 -04001164 int chansize, numchan;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001165
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001166 /* Get VRAM informations */
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001167 rdev->mc.vram_is_ddr = true;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001168 tmp = RREG32(RAMCFG);
1169 if (tmp & CHANSIZE_OVERRIDE) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001170 chansize = 16;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001171 } else if (tmp & CHANSIZE_MASK) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001172 chansize = 64;
1173 } else {
1174 chansize = 32;
1175 }
Alex Deucher5885b7a2009-10-19 17:23:33 -04001176 tmp = RREG32(CHMAP);
1177 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1178 case 0:
1179 default:
1180 numchan = 1;
1181 break;
1182 case 1:
1183 numchan = 2;
1184 break;
1185 case 2:
1186 numchan = 4;
1187 break;
1188 case 3:
1189 numchan = 8;
1190 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001191 }
Alex Deucher5885b7a2009-10-19 17:23:33 -04001192 rdev->mc.vram_width = numchan * chansize;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001193 /* Could aper size report 0 ? */
Jordan Crouse01d73a62010-05-27 13:40:24 -06001194 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001196 /* Setup GPU memory space */
1197 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
Jerome Glisse51e5fcd2010-02-19 14:33:54 +00001199 rdev->mc.visible_vram_size = rdev->mc.aper_size;
Jerome Glissed594e462010-02-17 21:54:29 +00001200 r600_vram_gtt_location(rdev, &rdev->mc);
Alex Deucherf47299c2010-03-16 20:54:38 -04001201
Alex Deucherf8920342010-06-30 12:02:03 -04001202 if (rdev->flags & RADEON_IS_IGP) {
1203 rs690_pm_info(rdev);
Alex Deucher06b64762010-01-05 11:27:29 -05001204 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
Alex Deucherf8920342010-06-30 12:02:03 -04001205 }
Alex Deucherf47299c2010-03-16 20:54:38 -04001206 radeon_update_bandwidth_info(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001207 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001208}
1209
Alex Deucher16cdf042011-10-28 10:30:02 -04001210int r600_vram_scratch_init(struct radeon_device *rdev)
1211{
1212 int r;
1213
1214 if (rdev->vram_scratch.robj == NULL) {
1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
Alex Deucher40f5cf92012-05-10 18:33:13 -04001217 NULL, &rdev->vram_scratch.robj);
Alex Deucher16cdf042011-10-28 10:30:02 -04001218 if (r) {
1219 return r;
1220 }
1221 }
1222
1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224 if (unlikely(r != 0))
1225 return r;
1226 r = radeon_bo_pin(rdev->vram_scratch.robj,
1227 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1228 if (r) {
1229 radeon_bo_unreserve(rdev->vram_scratch.robj);
1230 return r;
1231 }
1232 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233 (void **)&rdev->vram_scratch.ptr);
1234 if (r)
1235 radeon_bo_unpin(rdev->vram_scratch.robj);
1236 radeon_bo_unreserve(rdev->vram_scratch.robj);
1237
1238 return r;
1239}
1240
1241void r600_vram_scratch_fini(struct radeon_device *rdev)
1242{
1243 int r;
1244
1245 if (rdev->vram_scratch.robj == NULL) {
1246 return;
1247 }
1248 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249 if (likely(r == 0)) {
1250 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251 radeon_bo_unpin(rdev->vram_scratch.robj);
1252 radeon_bo_unreserve(rdev->vram_scratch.robj);
1253 }
1254 radeon_bo_unref(&rdev->vram_scratch.robj);
1255}
1256
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001257/* We doesn't check that the GPU really needs a reset we simply do the
1258 * reset, it's up to the caller to determine if the GPU needs one. We
1259 * might add an helper function to check that.
1260 */
Lauri Kasanen1109ca02012-08-31 13:43:50 -04001261static int r600_gpu_soft_reset(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001262{
Jerome Glissea3c19452009-10-01 18:02:13 +02001263 struct rv515_mc_save save;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001264 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1265 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1266 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1267 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1268 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1269 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1270 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1271 S_008010_GUI_ACTIVE(1);
1272 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1273 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1274 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1275 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1276 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1277 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1278 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1279 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
Jerome Glissea3c19452009-10-01 18:02:13 +02001280 u32 tmp;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001281
Alex Deucher8d96fe92011-01-21 15:38:22 +00001282 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1283 return 0;
1284
Jerome Glisse1a029b72009-10-06 19:04:30 +02001285 dev_info(rdev->dev, "GPU softreset \n");
1286 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1287 RREG32(R_008010_GRBM_STATUS));
1288 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
Jerome Glissea3c19452009-10-01 18:02:13 +02001289 RREG32(R_008014_GRBM_STATUS2));
Jerome Glisse1a029b72009-10-06 19:04:30 +02001290 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1291 RREG32(R_000E50_SRBM_STATUS));
Jerome Glisse440a7cd2012-06-27 12:25:01 -04001292 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1293 RREG32(CP_STALLED_STAT1));
1294 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1295 RREG32(CP_STALLED_STAT2));
1296 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1297 RREG32(CP_BUSY_STAT));
1298 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1299 RREG32(CP_STAT));
Jerome Glisseeaaa6982013-01-02 15:12:15 -05001300 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1301 RREG32(DMA_STATUS_REG));
Jerome Glissea3c19452009-10-01 18:02:13 +02001302 rv515_mc_stop(rdev, &save);
1303 if (r600_mc_wait_for_idle(rdev)) {
1304 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1305 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001306 /* Disable CP parsing/prefetching */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001307 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001308 /* Check if any of the rendering block is busy and reset it */
1309 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1310 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
Jerome Glissea3c19452009-10-01 18:02:13 +02001311 tmp = S_008020_SOFT_RESET_CR(1) |
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001312 S_008020_SOFT_RESET_DB(1) |
1313 S_008020_SOFT_RESET_CB(1) |
1314 S_008020_SOFT_RESET_PA(1) |
1315 S_008020_SOFT_RESET_SC(1) |
1316 S_008020_SOFT_RESET_SMX(1) |
1317 S_008020_SOFT_RESET_SPI(1) |
1318 S_008020_SOFT_RESET_SX(1) |
1319 S_008020_SOFT_RESET_SH(1) |
1320 S_008020_SOFT_RESET_TC(1) |
1321 S_008020_SOFT_RESET_TA(1) |
1322 S_008020_SOFT_RESET_VC(1) |
Jerome Glissea3c19452009-10-01 18:02:13 +02001323 S_008020_SOFT_RESET_VGT(1);
Jerome Glisse1a029b72009-10-06 19:04:30 +02001324 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
Jerome Glissea3c19452009-10-01 18:02:13 +02001325 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001326 RREG32(R_008020_GRBM_SOFT_RESET);
1327 mdelay(15);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001328 WREG32(R_008020_GRBM_SOFT_RESET, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001329 }
1330 /* Reset CP (we always reset CP) */
Jerome Glissea3c19452009-10-01 18:02:13 +02001331 tmp = S_008020_SOFT_RESET_CP(1);
1332 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1333 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001334 RREG32(R_008020_GRBM_SOFT_RESET);
1335 mdelay(15);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001336 WREG32(R_008020_GRBM_SOFT_RESET, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001337 /* Wait a little for things to settle down */
Jerome Glisse225758d2010-03-09 14:45:10 +00001338 mdelay(1);
Jerome Glisse1a029b72009-10-06 19:04:30 +02001339 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1340 RREG32(R_008010_GRBM_STATUS));
1341 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1342 RREG32(R_008014_GRBM_STATUS2));
1343 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1344 RREG32(R_000E50_SRBM_STATUS));
Jerome Glisse440a7cd2012-06-27 12:25:01 -04001345 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1346 RREG32(CP_STALLED_STAT1));
1347 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1348 RREG32(CP_STALLED_STAT2));
1349 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1350 RREG32(CP_BUSY_STAT));
1351 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1352 RREG32(CP_STAT));
Jerome Glisseeaaa6982013-01-02 15:12:15 -05001353 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1354 RREG32(DMA_STATUS_REG));
Jerome Glissea3c19452009-10-01 18:02:13 +02001355 rv515_mc_resume(rdev, &save);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001356 return 0;
1357}
1358
Christian Könige32eb502011-10-23 12:56:27 +02001359bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
Jerome Glisse225758d2010-03-09 14:45:10 +00001360{
1361 u32 srbm_status;
1362 u32 grbm_status;
1363 u32 grbm_status2;
Jerome Glisse225758d2010-03-09 14:45:10 +00001364
1365 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1366 grbm_status = RREG32(R_008010_GRBM_STATUS);
1367 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1368 if (!G_008010_GUI_ACTIVE(grbm_status)) {
Christian König069211e2012-05-02 15:11:20 +02001369 radeon_ring_lockup_update(ring);
Jerome Glisse225758d2010-03-09 14:45:10 +00001370 return false;
1371 }
1372 /* force CP activities */
Christian König7b9ef162012-05-02 15:11:23 +02001373 radeon_ring_force_activity(rdev, ring);
Christian König069211e2012-05-02 15:11:20 +02001374 return radeon_ring_test_lockup(rdev, ring);
Jerome Glisse225758d2010-03-09 14:45:10 +00001375}
1376
Alex Deucher4d756582012-09-27 15:08:35 -04001377/**
1378 * r600_dma_is_lockup - Check if the DMA engine is locked up
1379 *
1380 * @rdev: radeon_device pointer
1381 * @ring: radeon_ring structure holding ring information
1382 *
1383 * Check if the async DMA engine is locked up (r6xx-evergreen).
1384 * Returns true if the engine appears to be locked up, false if not.
1385 */
1386bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1387{
1388 u32 dma_status_reg;
1389
1390 dma_status_reg = RREG32(DMA_STATUS_REG);
1391 if (dma_status_reg & DMA_IDLE) {
1392 radeon_ring_lockup_update(ring);
1393 return false;
1394 }
1395 /* force ring activities */
1396 radeon_ring_force_activity(rdev, ring);
1397 return radeon_ring_test_lockup(rdev, ring);
1398}
1399
Jerome Glissea2d07b72010-03-09 14:45:11 +00001400int r600_asic_reset(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001401{
1402 return r600_gpu_soft_reset(rdev);
1403}
1404
Alex Deucher416a2bd2012-05-31 19:00:25 -04001405u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1406 u32 tiling_pipe_num,
1407 u32 max_rb_num,
1408 u32 total_max_rb_num,
1409 u32 disabled_rb_mask)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001410{
Alex Deucher416a2bd2012-05-31 19:00:25 -04001411 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1412 u32 pipe_rb_ratio, pipe_rb_remain;
1413 u32 data = 0, mask = 1 << (max_rb_num - 1);
1414 unsigned i, j;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001415
Alex Deucher416a2bd2012-05-31 19:00:25 -04001416 /* mask out the RBs that don't exist on that asic */
1417 disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001418
Alex Deucher416a2bd2012-05-31 19:00:25 -04001419 rendering_pipe_num = 1 << tiling_pipe_num;
1420 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1421 BUG_ON(rendering_pipe_num < req_rb_num);
1422
1423 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1424 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1425
1426 if (rdev->family <= CHIP_RV740) {
1427 /* r6xx/r7xx */
1428 rb_num_width = 2;
1429 } else {
1430 /* eg+ */
1431 rb_num_width = 4;
1432 }
1433
1434 for (i = 0; i < max_rb_num; i++) {
1435 if (!(mask & disabled_rb_mask)) {
1436 for (j = 0; j < pipe_rb_ratio; j++) {
1437 data <<= rb_num_width;
1438 data |= max_rb_num - i - 1;
1439 }
1440 if (pipe_rb_remain) {
1441 data <<= rb_num_width;
1442 data |= max_rb_num - i - 1;
1443 pipe_rb_remain--;
1444 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001445 }
Alex Deucher416a2bd2012-05-31 19:00:25 -04001446 mask >>= 1;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001447 }
1448
Alex Deucher416a2bd2012-05-31 19:00:25 -04001449 return data;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001450}
1451
1452int r600_count_pipe_bits(uint32_t val)
1453{
Akinobu Mitaef8cf3a2012-11-09 12:10:41 +00001454 return hweight32(val);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001455}
1456
Lauri Kasanen1109ca02012-08-31 13:43:50 -04001457static void r600_gpu_init(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001458{
1459 u32 tiling_config;
1460 u32 ramcfg;
Alex Deucherd03f5d52010-02-19 16:22:31 -05001461 u32 cc_rb_backend_disable;
1462 u32 cc_gc_shader_pipe_config;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001463 u32 tmp;
1464 int i, j;
1465 u32 sq_config;
1466 u32 sq_gpr_resource_mgmt_1 = 0;
1467 u32 sq_gpr_resource_mgmt_2 = 0;
1468 u32 sq_thread_resource_mgmt = 0;
1469 u32 sq_stack_resource_mgmt_1 = 0;
1470 u32 sq_stack_resource_mgmt_2 = 0;
Alex Deucher416a2bd2012-05-31 19:00:25 -04001471 u32 disabled_rb_mask;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001472
Alex Deucher416a2bd2012-05-31 19:00:25 -04001473 rdev->config.r600.tiling_group_size = 256;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001474 switch (rdev->family) {
1475 case CHIP_R600:
1476 rdev->config.r600.max_pipes = 4;
1477 rdev->config.r600.max_tile_pipes = 8;
1478 rdev->config.r600.max_simds = 4;
1479 rdev->config.r600.max_backends = 4;
1480 rdev->config.r600.max_gprs = 256;
1481 rdev->config.r600.max_threads = 192;
1482 rdev->config.r600.max_stack_entries = 256;
1483 rdev->config.r600.max_hw_contexts = 8;
1484 rdev->config.r600.max_gs_threads = 16;
1485 rdev->config.r600.sx_max_export_size = 128;
1486 rdev->config.r600.sx_max_export_pos_size = 16;
1487 rdev->config.r600.sx_max_export_smx_size = 128;
1488 rdev->config.r600.sq_num_cf_insts = 2;
1489 break;
1490 case CHIP_RV630:
1491 case CHIP_RV635:
1492 rdev->config.r600.max_pipes = 2;
1493 rdev->config.r600.max_tile_pipes = 2;
1494 rdev->config.r600.max_simds = 3;
1495 rdev->config.r600.max_backends = 1;
1496 rdev->config.r600.max_gprs = 128;
1497 rdev->config.r600.max_threads = 192;
1498 rdev->config.r600.max_stack_entries = 128;
1499 rdev->config.r600.max_hw_contexts = 8;
1500 rdev->config.r600.max_gs_threads = 4;
1501 rdev->config.r600.sx_max_export_size = 128;
1502 rdev->config.r600.sx_max_export_pos_size = 16;
1503 rdev->config.r600.sx_max_export_smx_size = 128;
1504 rdev->config.r600.sq_num_cf_insts = 2;
1505 break;
1506 case CHIP_RV610:
1507 case CHIP_RV620:
1508 case CHIP_RS780:
1509 case CHIP_RS880:
1510 rdev->config.r600.max_pipes = 1;
1511 rdev->config.r600.max_tile_pipes = 1;
1512 rdev->config.r600.max_simds = 2;
1513 rdev->config.r600.max_backends = 1;
1514 rdev->config.r600.max_gprs = 128;
1515 rdev->config.r600.max_threads = 192;
1516 rdev->config.r600.max_stack_entries = 128;
1517 rdev->config.r600.max_hw_contexts = 4;
1518 rdev->config.r600.max_gs_threads = 4;
1519 rdev->config.r600.sx_max_export_size = 128;
1520 rdev->config.r600.sx_max_export_pos_size = 16;
1521 rdev->config.r600.sx_max_export_smx_size = 128;
1522 rdev->config.r600.sq_num_cf_insts = 1;
1523 break;
1524 case CHIP_RV670:
1525 rdev->config.r600.max_pipes = 4;
1526 rdev->config.r600.max_tile_pipes = 4;
1527 rdev->config.r600.max_simds = 4;
1528 rdev->config.r600.max_backends = 4;
1529 rdev->config.r600.max_gprs = 192;
1530 rdev->config.r600.max_threads = 192;
1531 rdev->config.r600.max_stack_entries = 256;
1532 rdev->config.r600.max_hw_contexts = 8;
1533 rdev->config.r600.max_gs_threads = 16;
1534 rdev->config.r600.sx_max_export_size = 128;
1535 rdev->config.r600.sx_max_export_pos_size = 16;
1536 rdev->config.r600.sx_max_export_smx_size = 128;
1537 rdev->config.r600.sq_num_cf_insts = 2;
1538 break;
1539 default:
1540 break;
1541 }
1542
1543 /* Initialize HDP */
1544 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1545 WREG32((0x2c14 + j), 0x00000000);
1546 WREG32((0x2c18 + j), 0x00000000);
1547 WREG32((0x2c1c + j), 0x00000000);
1548 WREG32((0x2c20 + j), 0x00000000);
1549 WREG32((0x2c24 + j), 0x00000000);
1550 }
1551
1552 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1553
1554 /* Setup tiling */
1555 tiling_config = 0;
1556 ramcfg = RREG32(RAMCFG);
1557 switch (rdev->config.r600.max_tile_pipes) {
1558 case 1:
1559 tiling_config |= PIPE_TILING(0);
1560 break;
1561 case 2:
1562 tiling_config |= PIPE_TILING(1);
1563 break;
1564 case 4:
1565 tiling_config |= PIPE_TILING(2);
1566 break;
1567 case 8:
1568 tiling_config |= PIPE_TILING(3);
1569 break;
1570 default:
1571 break;
1572 }
Alex Deucherd03f5d52010-02-19 16:22:31 -05001573 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
Jerome Glisse961fb592010-02-10 22:30:05 +00001574 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001575 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Alex Deucher881fe6c2010-10-18 23:54:56 -04001576 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
Alex Deucher416a2bd2012-05-31 19:00:25 -04001577
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001578 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1579 if (tmp > 3) {
1580 tiling_config |= ROW_TILING(3);
1581 tiling_config |= SAMPLE_SPLIT(3);
1582 } else {
1583 tiling_config |= ROW_TILING(tmp);
1584 tiling_config |= SAMPLE_SPLIT(tmp);
1585 }
1586 tiling_config |= BANK_SWAPS(1);
Alex Deucherd03f5d52010-02-19 16:22:31 -05001587
1588 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
Alex Deucher416a2bd2012-05-31 19:00:25 -04001589 tmp = R6XX_MAX_BACKENDS -
1590 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1591 if (tmp < rdev->config.r600.max_backends) {
1592 rdev->config.r600.max_backends = tmp;
1593 }
Alex Deucherd03f5d52010-02-19 16:22:31 -05001594
Alex Deucher416a2bd2012-05-31 19:00:25 -04001595 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1596 tmp = R6XX_MAX_PIPES -
1597 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1598 if (tmp < rdev->config.r600.max_pipes) {
1599 rdev->config.r600.max_pipes = tmp;
1600 }
1601 tmp = R6XX_MAX_SIMDS -
1602 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1603 if (tmp < rdev->config.r600.max_simds) {
1604 rdev->config.r600.max_simds = tmp;
1605 }
Alex Deucherd03f5d52010-02-19 16:22:31 -05001606
Alex Deucher416a2bd2012-05-31 19:00:25 -04001607 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1608 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1609 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1610 R6XX_MAX_BACKENDS, disabled_rb_mask);
1611 tiling_config |= tmp << 16;
1612 rdev->config.r600.backend_map = tmp;
1613
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001614 rdev->config.r600.tile_config = tiling_config;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001615 WREG32(GB_TILING_CONFIG, tiling_config);
1616 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1617 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
Alex Deucher4d756582012-09-27 15:08:35 -04001618 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001619
Alex Deucherd03f5d52010-02-19 16:22:31 -05001620 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001621 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1622 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1623
1624 /* Setup some CP states */
1625 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1626 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1627
1628 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1629 SYNC_WALKER | SYNC_ALIGNER));
1630 /* Setup various GPU states */
1631 if (rdev->family == CHIP_RV670)
1632 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1633
1634 tmp = RREG32(SX_DEBUG_1);
1635 tmp |= SMX_EVENT_RELEASE;
1636 if ((rdev->family > CHIP_R600))
1637 tmp |= ENABLE_NEW_SMX_ADDRESS;
1638 WREG32(SX_DEBUG_1, tmp);
1639
1640 if (((rdev->family) == CHIP_R600) ||
1641 ((rdev->family) == CHIP_RV630) ||
1642 ((rdev->family) == CHIP_RV610) ||
1643 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -05001644 ((rdev->family) == CHIP_RS780) ||
1645 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001646 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1647 } else {
1648 WREG32(DB_DEBUG, 0);
1649 }
1650 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1651 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1652
1653 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1654 WREG32(VGT_NUM_INSTANCES, 0);
1655
1656 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1657 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1658
1659 tmp = RREG32(SQ_MS_FIFO_SIZES);
1660 if (((rdev->family) == CHIP_RV610) ||
1661 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -05001662 ((rdev->family) == CHIP_RS780) ||
1663 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001664 tmp = (CACHE_FIFO_SIZE(0xa) |
1665 FETCH_FIFO_HIWATER(0xa) |
1666 DONE_FIFO_HIWATER(0xe0) |
1667 ALU_UPDATE_FIFO_HIWATER(0x8));
1668 } else if (((rdev->family) == CHIP_R600) ||
1669 ((rdev->family) == CHIP_RV630)) {
1670 tmp &= ~DONE_FIFO_HIWATER(0xff);
1671 tmp |= DONE_FIFO_HIWATER(0x4);
1672 }
1673 WREG32(SQ_MS_FIFO_SIZES, tmp);
1674
1675 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1676 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1677 */
1678 sq_config = RREG32(SQ_CONFIG);
1679 sq_config &= ~(PS_PRIO(3) |
1680 VS_PRIO(3) |
1681 GS_PRIO(3) |
1682 ES_PRIO(3));
1683 sq_config |= (DX9_CONSTS |
1684 VC_ENABLE |
1685 PS_PRIO(0) |
1686 VS_PRIO(1) |
1687 GS_PRIO(2) |
1688 ES_PRIO(3));
1689
1690 if ((rdev->family) == CHIP_R600) {
1691 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1692 NUM_VS_GPRS(124) |
1693 NUM_CLAUSE_TEMP_GPRS(4));
1694 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1695 NUM_ES_GPRS(0));
1696 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1697 NUM_VS_THREADS(48) |
1698 NUM_GS_THREADS(4) |
1699 NUM_ES_THREADS(4));
1700 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1701 NUM_VS_STACK_ENTRIES(128));
1702 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1703 NUM_ES_STACK_ENTRIES(0));
1704 } else if (((rdev->family) == CHIP_RV610) ||
1705 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -05001706 ((rdev->family) == CHIP_RS780) ||
1707 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001708 /* no vertex cache */
1709 sq_config &= ~VC_ENABLE;
1710
1711 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1712 NUM_VS_GPRS(44) |
1713 NUM_CLAUSE_TEMP_GPRS(2));
1714 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1715 NUM_ES_GPRS(17));
1716 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1717 NUM_VS_THREADS(78) |
1718 NUM_GS_THREADS(4) |
1719 NUM_ES_THREADS(31));
1720 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1721 NUM_VS_STACK_ENTRIES(40));
1722 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1723 NUM_ES_STACK_ENTRIES(16));
1724 } else if (((rdev->family) == CHIP_RV630) ||
1725 ((rdev->family) == CHIP_RV635)) {
1726 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1727 NUM_VS_GPRS(44) |
1728 NUM_CLAUSE_TEMP_GPRS(2));
1729 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1730 NUM_ES_GPRS(18));
1731 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1732 NUM_VS_THREADS(78) |
1733 NUM_GS_THREADS(4) |
1734 NUM_ES_THREADS(31));
1735 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1736 NUM_VS_STACK_ENTRIES(40));
1737 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1738 NUM_ES_STACK_ENTRIES(16));
1739 } else if ((rdev->family) == CHIP_RV670) {
1740 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1741 NUM_VS_GPRS(44) |
1742 NUM_CLAUSE_TEMP_GPRS(2));
1743 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1744 NUM_ES_GPRS(17));
1745 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1746 NUM_VS_THREADS(78) |
1747 NUM_GS_THREADS(4) |
1748 NUM_ES_THREADS(31));
1749 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1750 NUM_VS_STACK_ENTRIES(64));
1751 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1752 NUM_ES_STACK_ENTRIES(64));
1753 }
1754
1755 WREG32(SQ_CONFIG, sq_config);
1756 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1757 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1758 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1759 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1760 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1761
1762 if (((rdev->family) == CHIP_RV610) ||
1763 ((rdev->family) == CHIP_RV620) ||
Alex Deucheree59f2b2009-11-05 13:11:46 -05001764 ((rdev->family) == CHIP_RS780) ||
1765 ((rdev->family) == CHIP_RS880)) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001766 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1767 } else {
1768 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1769 }
1770
1771 /* More default values. 2D/3D driver should adjust as needed */
1772 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1773 S1_X(0x4) | S1_Y(0xc)));
1774 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1775 S1_X(0x2) | S1_Y(0x2) |
1776 S2_X(0xa) | S2_Y(0x6) |
1777 S3_X(0x6) | S3_Y(0xa)));
1778 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1779 S1_X(0x4) | S1_Y(0xc) |
1780 S2_X(0x1) | S2_Y(0x6) |
1781 S3_X(0xa) | S3_Y(0xe)));
1782 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1783 S5_X(0x0) | S5_Y(0x0) |
1784 S6_X(0xb) | S6_Y(0x4) |
1785 S7_X(0x7) | S7_Y(0x8)));
1786
1787 WREG32(VGT_STRMOUT_EN, 0);
1788 tmp = rdev->config.r600.max_pipes * 16;
1789 switch (rdev->family) {
1790 case CHIP_RV610:
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001791 case CHIP_RV620:
Alex Deucheree59f2b2009-11-05 13:11:46 -05001792 case CHIP_RS780:
1793 case CHIP_RS880:
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001794 tmp += 32;
1795 break;
1796 case CHIP_RV670:
1797 tmp += 128;
1798 break;
1799 default:
1800 break;
1801 }
1802 if (tmp > 256) {
1803 tmp = 256;
1804 }
1805 WREG32(VGT_ES_PER_GS, 128);
1806 WREG32(VGT_GS_PER_ES, tmp);
1807 WREG32(VGT_GS_PER_VS, 2);
1808 WREG32(VGT_GS_VERTEX_REUSE, 16);
1809
1810 /* more default values. 2D/3D driver should adjust as needed */
1811 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1812 WREG32(VGT_STRMOUT_EN, 0);
1813 WREG32(SX_MISC, 0);
1814 WREG32(PA_SC_MODE_CNTL, 0);
1815 WREG32(PA_SC_AA_CONFIG, 0);
1816 WREG32(PA_SC_LINE_STIPPLE, 0);
1817 WREG32(SPI_INPUT_Z, 0);
1818 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1819 WREG32(CB_COLOR7_FRAG, 0);
1820
1821 /* Clear render buffer base addresses */
1822 WREG32(CB_COLOR0_BASE, 0);
1823 WREG32(CB_COLOR1_BASE, 0);
1824 WREG32(CB_COLOR2_BASE, 0);
1825 WREG32(CB_COLOR3_BASE, 0);
1826 WREG32(CB_COLOR4_BASE, 0);
1827 WREG32(CB_COLOR5_BASE, 0);
1828 WREG32(CB_COLOR6_BASE, 0);
1829 WREG32(CB_COLOR7_BASE, 0);
1830 WREG32(CB_COLOR7_FRAG, 0);
1831
1832 switch (rdev->family) {
1833 case CHIP_RV610:
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001834 case CHIP_RV620:
Alex Deucheree59f2b2009-11-05 13:11:46 -05001835 case CHIP_RS780:
1836 case CHIP_RS880:
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001837 tmp = TC_L2_SIZE(8);
1838 break;
1839 case CHIP_RV630:
1840 case CHIP_RV635:
1841 tmp = TC_L2_SIZE(4);
1842 break;
1843 case CHIP_R600:
1844 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1845 break;
1846 default:
1847 tmp = TC_L2_SIZE(0);
1848 break;
1849 }
1850 WREG32(TC_CNTL, tmp);
1851
1852 tmp = RREG32(HDP_HOST_PATH_CNTL);
1853 WREG32(HDP_HOST_PATH_CNTL, tmp);
1854
1855 tmp = RREG32(ARB_POP);
1856 tmp |= ENABLE_TC128;
1857 WREG32(ARB_POP, tmp);
1858
1859 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1860 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1861 NUM_CLIP_SEQ(3)));
1862 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
Alex Deucherb866d132012-06-14 22:06:36 +02001863 WREG32(VC_ENHANCE, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001864}
1865
1866
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001867/*
1868 * Indirect registers accessor
1869 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001870u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001871{
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001872 u32 r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001873
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001874 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1875 (void)RREG32(PCIE_PORT_INDEX);
1876 r = RREG32(PCIE_PORT_DATA);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001877 return r;
1878}
1879
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001880void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001881{
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001882 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1883 (void)RREG32(PCIE_PORT_INDEX);
1884 WREG32(PCIE_PORT_DATA, (v));
1885 (void)RREG32(PCIE_PORT_DATA);
1886}
1887
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001888/*
1889 * CP & Ring
1890 */
1891void r600_cp_stop(struct radeon_device *rdev)
1892{
Dave Airlie53595332011-03-14 09:47:24 +10001893 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001894 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
Alex Deucher724c80e2010-08-27 18:25:25 -04001895 WREG32(SCRATCH_UMSK, 0);
Alex Deucher4d756582012-09-27 15:08:35 -04001896 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001897}
1898
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001899int r600_init_microcode(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001900{
1901 struct platform_device *pdev;
1902 const char *chip_name;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001903 const char *rlc_chip_name;
1904 size_t pfp_req_size, me_req_size, rlc_req_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001905 char fw_name[30];
1906 int err;
1907
1908 DRM_DEBUG("\n");
1909
1910 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1911 err = IS_ERR(pdev);
1912 if (err) {
1913 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1914 return -EINVAL;
1915 }
1916
1917 switch (rdev->family) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001918 case CHIP_R600:
1919 chip_name = "R600";
1920 rlc_chip_name = "R600";
1921 break;
1922 case CHIP_RV610:
1923 chip_name = "RV610";
1924 rlc_chip_name = "R600";
1925 break;
1926 case CHIP_RV630:
1927 chip_name = "RV630";
1928 rlc_chip_name = "R600";
1929 break;
1930 case CHIP_RV620:
1931 chip_name = "RV620";
1932 rlc_chip_name = "R600";
1933 break;
1934 case CHIP_RV635:
1935 chip_name = "RV635";
1936 rlc_chip_name = "R600";
1937 break;
1938 case CHIP_RV670:
1939 chip_name = "RV670";
1940 rlc_chip_name = "R600";
1941 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001942 case CHIP_RS780:
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001943 case CHIP_RS880:
1944 chip_name = "RS780";
1945 rlc_chip_name = "R600";
1946 break;
1947 case CHIP_RV770:
1948 chip_name = "RV770";
1949 rlc_chip_name = "R700";
1950 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001951 case CHIP_RV730:
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001952 case CHIP_RV740:
1953 chip_name = "RV730";
1954 rlc_chip_name = "R700";
1955 break;
1956 case CHIP_RV710:
1957 chip_name = "RV710";
1958 rlc_chip_name = "R700";
1959 break;
Alex Deucherfe251e22010-03-24 13:36:43 -04001960 case CHIP_CEDAR:
1961 chip_name = "CEDAR";
Alex Deucher45f9a392010-03-24 13:55:51 -04001962 rlc_chip_name = "CEDAR";
Alex Deucherfe251e22010-03-24 13:36:43 -04001963 break;
1964 case CHIP_REDWOOD:
1965 chip_name = "REDWOOD";
Alex Deucher45f9a392010-03-24 13:55:51 -04001966 rlc_chip_name = "REDWOOD";
Alex Deucherfe251e22010-03-24 13:36:43 -04001967 break;
1968 case CHIP_JUNIPER:
1969 chip_name = "JUNIPER";
Alex Deucher45f9a392010-03-24 13:55:51 -04001970 rlc_chip_name = "JUNIPER";
Alex Deucherfe251e22010-03-24 13:36:43 -04001971 break;
1972 case CHIP_CYPRESS:
1973 case CHIP_HEMLOCK:
1974 chip_name = "CYPRESS";
Alex Deucher45f9a392010-03-24 13:55:51 -04001975 rlc_chip_name = "CYPRESS";
Alex Deucherfe251e22010-03-24 13:36:43 -04001976 break;
Alex Deucher439bd6c2010-11-22 17:56:31 -05001977 case CHIP_PALM:
1978 chip_name = "PALM";
1979 rlc_chip_name = "SUMO";
1980 break;
Alex Deucherd5c5a722011-05-31 15:42:48 -04001981 case CHIP_SUMO:
1982 chip_name = "SUMO";
1983 rlc_chip_name = "SUMO";
1984 break;
1985 case CHIP_SUMO2:
1986 chip_name = "SUMO2";
1987 rlc_chip_name = "SUMO";
1988 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001989 default: BUG();
1990 }
1991
Alex Deucherfe251e22010-03-24 13:36:43 -04001992 if (rdev->family >= CHIP_CEDAR) {
1993 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1994 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
Alex Deucher45f9a392010-03-24 13:55:51 -04001995 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
Alex Deucherfe251e22010-03-24 13:36:43 -04001996 } else if (rdev->family >= CHIP_RV770) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001997 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1998 me_req_size = R700_PM4_UCODE_SIZE * 4;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001999 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002000 } else {
2001 pfp_req_size = PFP_UCODE_SIZE * 4;
2002 me_req_size = PM4_UCODE_SIZE * 12;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002003 rlc_req_size = RLC_UCODE_SIZE * 4;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002004 }
2005
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002006 DRM_INFO("Loading %s Microcode\n", chip_name);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002007
2008 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2009 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2010 if (err)
2011 goto out;
2012 if (rdev->pfp_fw->size != pfp_req_size) {
2013 printk(KERN_ERR
2014 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2015 rdev->pfp_fw->size, fw_name);
2016 err = -EINVAL;
2017 goto out;
2018 }
2019
2020 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2021 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2022 if (err)
2023 goto out;
2024 if (rdev->me_fw->size != me_req_size) {
2025 printk(KERN_ERR
2026 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2027 rdev->me_fw->size, fw_name);
2028 err = -EINVAL;
2029 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002030
2031 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2032 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2033 if (err)
2034 goto out;
2035 if (rdev->rlc_fw->size != rlc_req_size) {
2036 printk(KERN_ERR
2037 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2038 rdev->rlc_fw->size, fw_name);
2039 err = -EINVAL;
2040 }
2041
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002042out:
2043 platform_device_unregister(pdev);
2044
2045 if (err) {
2046 if (err != -EINVAL)
2047 printk(KERN_ERR
2048 "r600_cp: Failed to load firmware \"%s\"\n",
2049 fw_name);
2050 release_firmware(rdev->pfp_fw);
2051 rdev->pfp_fw = NULL;
2052 release_firmware(rdev->me_fw);
2053 rdev->me_fw = NULL;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002054 release_firmware(rdev->rlc_fw);
2055 rdev->rlc_fw = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002056 }
2057 return err;
2058}
2059
2060static int r600_cp_load_microcode(struct radeon_device *rdev)
2061{
2062 const __be32 *fw_data;
2063 int i;
2064
2065 if (!rdev->me_fw || !rdev->pfp_fw)
2066 return -EINVAL;
2067
2068 r600_cp_stop(rdev);
2069
Cédric Cano4eace7f2011-02-11 19:45:38 -05002070 WREG32(CP_RB_CNTL,
2071#ifdef __BIG_ENDIAN
2072 BUF_SWAP_32BIT |
2073#endif
2074 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002075
2076 /* Reset cp */
2077 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2078 RREG32(GRBM_SOFT_RESET);
2079 mdelay(15);
2080 WREG32(GRBM_SOFT_RESET, 0);
2081
2082 WREG32(CP_ME_RAM_WADDR, 0);
2083
2084 fw_data = (const __be32 *)rdev->me_fw->data;
2085 WREG32(CP_ME_RAM_WADDR, 0);
2086 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2087 WREG32(CP_ME_RAM_DATA,
2088 be32_to_cpup(fw_data++));
2089
2090 fw_data = (const __be32 *)rdev->pfp_fw->data;
2091 WREG32(CP_PFP_UCODE_ADDR, 0);
2092 for (i = 0; i < PFP_UCODE_SIZE; i++)
2093 WREG32(CP_PFP_UCODE_DATA,
2094 be32_to_cpup(fw_data++));
2095
2096 WREG32(CP_PFP_UCODE_ADDR, 0);
2097 WREG32(CP_ME_RAM_WADDR, 0);
2098 WREG32(CP_ME_RAM_RADDR, 0);
2099 return 0;
2100}
2101
2102int r600_cp_start(struct radeon_device *rdev)
2103{
Christian Könige32eb502011-10-23 12:56:27 +02002104 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002105 int r;
2106 uint32_t cp_me;
2107
Christian Könige32eb502011-10-23 12:56:27 +02002108 r = radeon_ring_lock(rdev, ring, 7);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002109 if (r) {
2110 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2111 return r;
2112 }
Christian Könige32eb502011-10-23 12:56:27 +02002113 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2114 radeon_ring_write(ring, 0x1);
Alex Deucher7e7b41d2010-09-02 21:32:32 -04002115 if (rdev->family >= CHIP_RV770) {
Christian Könige32eb502011-10-23 12:56:27 +02002116 radeon_ring_write(ring, 0x0);
2117 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
Alex Deucherfe251e22010-03-24 13:36:43 -04002118 } else {
Christian Könige32eb502011-10-23 12:56:27 +02002119 radeon_ring_write(ring, 0x3);
2120 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002121 }
Christian Könige32eb502011-10-23 12:56:27 +02002122 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2123 radeon_ring_write(ring, 0);
2124 radeon_ring_write(ring, 0);
2125 radeon_ring_unlock_commit(rdev, ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002126
2127 cp_me = 0xff;
2128 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2129 return 0;
2130}
2131
2132int r600_cp_resume(struct radeon_device *rdev)
2133{
Christian Könige32eb502011-10-23 12:56:27 +02002134 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002135 u32 tmp;
2136 u32 rb_bufsz;
2137 int r;
2138
2139 /* Reset cp */
2140 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2141 RREG32(GRBM_SOFT_RESET);
2142 mdelay(15);
2143 WREG32(GRBM_SOFT_RESET, 0);
2144
2145 /* Set ring buffer size */
Christian Könige32eb502011-10-23 12:56:27 +02002146 rb_bufsz = drm_order(ring->ring_size / 8);
Alex Deucher724c80e2010-08-27 18:25:25 -04002147 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002148#ifdef __BIG_ENDIAN
Alex Deucherd6f28932009-11-02 16:01:27 -05002149 tmp |= BUF_SWAP_32BIT;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002150#endif
Alex Deucherd6f28932009-11-02 16:01:27 -05002151 WREG32(CP_RB_CNTL, tmp);
Christian König15d33322011-09-15 19:02:22 +02002152 WREG32(CP_SEM_WAIT_TIMER, 0x0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002153
2154 /* Set the write pointer delay */
2155 WREG32(CP_RB_WPTR_DELAY, 0);
2156
2157 /* Initialize the ring buffer's read and write pointers */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002158 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2159 WREG32(CP_RB_RPTR_WR, 0);
Christian Könige32eb502011-10-23 12:56:27 +02002160 ring->wptr = 0;
2161 WREG32(CP_RB_WPTR, ring->wptr);
Alex Deucher724c80e2010-08-27 18:25:25 -04002162
2163 /* set the wb address whether it's enabled or not */
Cédric Cano4eace7f2011-02-11 19:45:38 -05002164 WREG32(CP_RB_RPTR_ADDR,
Cédric Cano4eace7f2011-02-11 19:45:38 -05002165 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
Alex Deucher724c80e2010-08-27 18:25:25 -04002166 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2167 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2168
2169 if (rdev->wb.enabled)
2170 WREG32(SCRATCH_UMSK, 0xff);
2171 else {
2172 tmp |= RB_NO_UPDATE;
2173 WREG32(SCRATCH_UMSK, 0);
2174 }
2175
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002176 mdelay(1);
2177 WREG32(CP_RB_CNTL, tmp);
2178
Christian Könige32eb502011-10-23 12:56:27 +02002179 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002180 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2181
Christian Könige32eb502011-10-23 12:56:27 +02002182 ring->rptr = RREG32(CP_RB_RPTR);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002183
2184 r600_cp_start(rdev);
Christian Könige32eb502011-10-23 12:56:27 +02002185 ring->ready = true;
Alex Deucherf7128122012-02-23 17:53:45 -05002186 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002187 if (r) {
Christian Könige32eb502011-10-23 12:56:27 +02002188 ring->ready = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002189 return r;
2190 }
2191 return 0;
2192}
2193
Christian Könige32eb502011-10-23 12:56:27 +02002194void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002195{
2196 u32 rb_bufsz;
Christian König45df6802012-07-06 16:22:55 +02002197 int r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002198
2199 /* Align ring size */
2200 rb_bufsz = drm_order(ring_size / 8);
2201 ring_size = (1 << (rb_bufsz + 1)) * 4;
Christian Könige32eb502011-10-23 12:56:27 +02002202 ring->ring_size = ring_size;
2203 ring->align_mask = 16 - 1;
Christian König45df6802012-07-06 16:22:55 +02002204
Alex Deucher89d35802012-07-17 14:02:31 -04002205 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2206 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2207 if (r) {
2208 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2209 ring->rptr_save_reg = 0;
2210 }
Christian König45df6802012-07-06 16:22:55 +02002211 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002212}
2213
Jerome Glisse655efd32010-02-02 11:51:45 +01002214void r600_cp_fini(struct radeon_device *rdev)
2215{
Christian König45df6802012-07-06 16:22:55 +02002216 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Jerome Glisse655efd32010-02-02 11:51:45 +01002217 r600_cp_stop(rdev);
Christian König45df6802012-07-06 16:22:55 +02002218 radeon_ring_fini(rdev, ring);
2219 radeon_scratch_free(rdev, ring->rptr_save_reg);
Jerome Glisse655efd32010-02-02 11:51:45 +01002220}
2221
Alex Deucher4d756582012-09-27 15:08:35 -04002222/*
2223 * DMA
2224 * Starting with R600, the GPU has an asynchronous
2225 * DMA engine. The programming model is very similar
2226 * to the 3D engine (ring buffer, IBs, etc.), but the
2227 * DMA controller has it's own packet format that is
2228 * different form the PM4 format used by the 3D engine.
2229 * It supports copying data, writing embedded data,
2230 * solid fills, and a number of other things. It also
2231 * has support for tiling/detiling of buffers.
2232 */
2233/**
2234 * r600_dma_stop - stop the async dma engine
2235 *
2236 * @rdev: radeon_device pointer
2237 *
2238 * Stop the async dma engine (r6xx-evergreen).
2239 */
2240void r600_dma_stop(struct radeon_device *rdev)
2241{
2242 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2243
2244 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2245
2246 rb_cntl &= ~DMA_RB_ENABLE;
2247 WREG32(DMA_RB_CNTL, rb_cntl);
2248
2249 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2250}
2251
2252/**
2253 * r600_dma_resume - setup and start the async dma engine
2254 *
2255 * @rdev: radeon_device pointer
2256 *
2257 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2258 * Returns 0 for success, error for failure.
2259 */
2260int r600_dma_resume(struct radeon_device *rdev)
2261{
2262 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2263 u32 rb_cntl, dma_cntl;
2264 u32 rb_bufsz;
2265 int r;
2266
2267 /* Reset dma */
2268 if (rdev->family >= CHIP_RV770)
2269 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2270 else
2271 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2272 RREG32(SRBM_SOFT_RESET);
2273 udelay(50);
2274 WREG32(SRBM_SOFT_RESET, 0);
2275
2276 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2277 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2278
2279 /* Set ring buffer size in dwords */
2280 rb_bufsz = drm_order(ring->ring_size / 4);
2281 rb_cntl = rb_bufsz << 1;
2282#ifdef __BIG_ENDIAN
2283 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2284#endif
2285 WREG32(DMA_RB_CNTL, rb_cntl);
2286
2287 /* Initialize the ring buffer's read and write pointers */
2288 WREG32(DMA_RB_RPTR, 0);
2289 WREG32(DMA_RB_WPTR, 0);
2290
2291 /* set the wb address whether it's enabled or not */
2292 WREG32(DMA_RB_RPTR_ADDR_HI,
2293 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2294 WREG32(DMA_RB_RPTR_ADDR_LO,
2295 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2296
2297 if (rdev->wb.enabled)
2298 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2299
2300 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2301
2302 /* enable DMA IBs */
2303 WREG32(DMA_IB_CNTL, DMA_IB_ENABLE);
2304
2305 dma_cntl = RREG32(DMA_CNTL);
2306 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2307 WREG32(DMA_CNTL, dma_cntl);
2308
2309 if (rdev->family >= CHIP_RV770)
2310 WREG32(DMA_MODE, 1);
2311
2312 ring->wptr = 0;
2313 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2314
2315 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2316
2317 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2318
2319 ring->ready = true;
2320
2321 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2322 if (r) {
2323 ring->ready = false;
2324 return r;
2325 }
2326
2327 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2328
2329 return 0;
2330}
2331
2332/**
2333 * r600_dma_fini - tear down the async dma engine
2334 *
2335 * @rdev: radeon_device pointer
2336 *
2337 * Stop the async dma engine and free the ring (r6xx-evergreen).
2338 */
2339void r600_dma_fini(struct radeon_device *rdev)
2340{
2341 r600_dma_stop(rdev);
2342 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2343}
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002344
2345/*
2346 * GPU scratch registers helpers function.
2347 */
2348void r600_scratch_init(struct radeon_device *rdev)
2349{
2350 int i;
2351
2352 rdev->scratch.num_reg = 7;
Alex Deucher724c80e2010-08-27 18:25:25 -04002353 rdev->scratch.reg_base = SCRATCH_REG0;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002354 for (i = 0; i < rdev->scratch.num_reg; i++) {
2355 rdev->scratch.free[i] = true;
Alex Deucher724c80e2010-08-27 18:25:25 -04002356 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002357 }
2358}
2359
Christian Könige32eb502011-10-23 12:56:27 +02002360int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002361{
2362 uint32_t scratch;
2363 uint32_t tmp = 0;
Alex Deucher8b25ed32012-07-17 14:02:30 -04002364 unsigned i;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002365 int r;
2366
2367 r = radeon_scratch_get(rdev, &scratch);
2368 if (r) {
2369 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2370 return r;
2371 }
2372 WREG32(scratch, 0xCAFEDEAD);
Christian Könige32eb502011-10-23 12:56:27 +02002373 r = radeon_ring_lock(rdev, ring, 3);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002374 if (r) {
Alex Deucher8b25ed32012-07-17 14:02:30 -04002375 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002376 radeon_scratch_free(rdev, scratch);
2377 return r;
2378 }
Christian Könige32eb502011-10-23 12:56:27 +02002379 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2380 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2381 radeon_ring_write(ring, 0xDEADBEEF);
2382 radeon_ring_unlock_commit(rdev, ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002383 for (i = 0; i < rdev->usec_timeout; i++) {
2384 tmp = RREG32(scratch);
2385 if (tmp == 0xDEADBEEF)
2386 break;
2387 DRM_UDELAY(1);
2388 }
2389 if (i < rdev->usec_timeout) {
Alex Deucher8b25ed32012-07-17 14:02:30 -04002390 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002391 } else {
Christian Königbf852792011-10-13 13:19:22 +02002392 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
Alex Deucher8b25ed32012-07-17 14:02:30 -04002393 ring->idx, scratch, tmp);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002394 r = -EINVAL;
2395 }
2396 radeon_scratch_free(rdev, scratch);
2397 return r;
2398}
2399
Alex Deucher4d756582012-09-27 15:08:35 -04002400/**
2401 * r600_dma_ring_test - simple async dma engine test
2402 *
2403 * @rdev: radeon_device pointer
2404 * @ring: radeon_ring structure holding ring information
2405 *
2406 * Test the DMA engine by writing using it to write an
2407 * value to memory. (r6xx-SI).
2408 * Returns 0 for success, error for failure.
2409 */
2410int r600_dma_ring_test(struct radeon_device *rdev,
2411 struct radeon_ring *ring)
2412{
2413 unsigned i;
2414 int r;
2415 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2416 u32 tmp;
2417
2418 if (!ptr) {
2419 DRM_ERROR("invalid vram scratch pointer\n");
2420 return -EINVAL;
2421 }
2422
2423 tmp = 0xCAFEDEAD;
2424 writel(tmp, ptr);
2425
2426 r = radeon_ring_lock(rdev, ring, 4);
2427 if (r) {
2428 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2429 return r;
2430 }
2431 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2432 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2433 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2434 radeon_ring_write(ring, 0xDEADBEEF);
2435 radeon_ring_unlock_commit(rdev, ring);
2436
2437 for (i = 0; i < rdev->usec_timeout; i++) {
2438 tmp = readl(ptr);
2439 if (tmp == 0xDEADBEEF)
2440 break;
2441 DRM_UDELAY(1);
2442 }
2443
2444 if (i < rdev->usec_timeout) {
2445 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2446 } else {
2447 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2448 ring->idx, tmp);
2449 r = -EINVAL;
2450 }
2451 return r;
2452}
2453
2454/*
2455 * CP fences/semaphores
2456 */
2457
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002458void r600_fence_ring_emit(struct radeon_device *rdev,
2459 struct radeon_fence *fence)
2460{
Christian Könige32eb502011-10-23 12:56:27 +02002461 struct radeon_ring *ring = &rdev->ring[fence->ring];
Christian König7b1f2482011-09-23 15:11:23 +02002462
Alex Deucherd0f8a852010-09-04 05:04:34 -04002463 if (rdev->wb.use_event) {
Jerome Glisse30eb77f2011-11-20 20:45:34 +00002464 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
Jerome Glisse77b1bad2011-10-26 11:41:22 -04002465 /* flush read cache over gart */
Christian Könige32eb502011-10-23 12:56:27 +02002466 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2467 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2468 PACKET3_VC_ACTION_ENA |
2469 PACKET3_SH_ACTION_ENA);
2470 radeon_ring_write(ring, 0xFFFFFFFF);
2471 radeon_ring_write(ring, 0);
2472 radeon_ring_write(ring, 10); /* poll interval */
Alex Deucherd0f8a852010-09-04 05:04:34 -04002473 /* EVENT_WRITE_EOP - flush caches, send int */
Christian Könige32eb502011-10-23 12:56:27 +02002474 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2475 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2476 radeon_ring_write(ring, addr & 0xffffffff);
2477 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2478 radeon_ring_write(ring, fence->seq);
2479 radeon_ring_write(ring, 0);
Alex Deucherd0f8a852010-09-04 05:04:34 -04002480 } else {
Jerome Glisse77b1bad2011-10-26 11:41:22 -04002481 /* flush read cache over gart */
Christian Könige32eb502011-10-23 12:56:27 +02002482 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2483 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2484 PACKET3_VC_ACTION_ENA |
2485 PACKET3_SH_ACTION_ENA);
2486 radeon_ring_write(ring, 0xFFFFFFFF);
2487 radeon_ring_write(ring, 0);
2488 radeon_ring_write(ring, 10); /* poll interval */
2489 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2490 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
Alex Deucherd0f8a852010-09-04 05:04:34 -04002491 /* wait for 3D idle clean */
Christian Könige32eb502011-10-23 12:56:27 +02002492 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2493 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2494 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
Alex Deucherd0f8a852010-09-04 05:04:34 -04002495 /* Emit fence sequence & fire IRQ */
Christian Könige32eb502011-10-23 12:56:27 +02002496 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2497 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2498 radeon_ring_write(ring, fence->seq);
Alex Deucherd0f8a852010-09-04 05:04:34 -04002499 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
Christian Könige32eb502011-10-23 12:56:27 +02002500 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2501 radeon_ring_write(ring, RB_INT_STAT);
Alex Deucherd0f8a852010-09-04 05:04:34 -04002502 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002503}
2504
Christian König15d33322011-09-15 19:02:22 +02002505void r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +02002506 struct radeon_ring *ring,
Christian König15d33322011-09-15 19:02:22 +02002507 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +02002508 bool emit_wait)
Christian König15d33322011-09-15 19:02:22 +02002509{
2510 uint64_t addr = semaphore->gpu_addr;
2511 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2512
Christian König0be70432012-03-07 11:28:57 +01002513 if (rdev->family < CHIP_CAYMAN)
2514 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2515
Christian Könige32eb502011-10-23 12:56:27 +02002516 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2517 radeon_ring_write(ring, addr & 0xffffffff);
2518 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
Christian König15d33322011-09-15 19:02:22 +02002519}
2520
Alex Deucher4d756582012-09-27 15:08:35 -04002521/*
2522 * DMA fences/semaphores
2523 */
2524
2525/**
2526 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2527 *
2528 * @rdev: radeon_device pointer
2529 * @fence: radeon fence object
2530 *
2531 * Add a DMA fence packet to the ring to write
2532 * the fence seq number and DMA trap packet to generate
2533 * an interrupt if needed (r6xx-r7xx).
2534 */
2535void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2536 struct radeon_fence *fence)
2537{
2538 struct radeon_ring *ring = &rdev->ring[fence->ring];
2539 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
Jerome Glisse86a18812012-12-12 16:43:15 -05002540
Alex Deucher4d756582012-09-27 15:08:35 -04002541 /* write the fence */
2542 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2543 radeon_ring_write(ring, addr & 0xfffffffc);
2544 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
Jerome Glisse86a18812012-12-12 16:43:15 -05002545 radeon_ring_write(ring, lower_32_bits(fence->seq));
Alex Deucher4d756582012-09-27 15:08:35 -04002546 /* generate an interrupt */
2547 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2548}
2549
2550/**
2551 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2552 *
2553 * @rdev: radeon_device pointer
2554 * @ring: radeon_ring structure holding ring information
2555 * @semaphore: radeon semaphore object
2556 * @emit_wait: wait or signal semaphore
2557 *
2558 * Add a DMA semaphore packet to the ring wait on or signal
2559 * other rings (r6xx-SI).
2560 */
2561void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2562 struct radeon_ring *ring,
2563 struct radeon_semaphore *semaphore,
2564 bool emit_wait)
2565{
2566 u64 addr = semaphore->gpu_addr;
2567 u32 s = emit_wait ? 0 : 1;
2568
2569 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2570 radeon_ring_write(ring, addr & 0xfffffffc);
2571 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2572}
2573
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002574int r600_copy_blit(struct radeon_device *rdev,
Alex Deucher003cefe2011-09-16 12:04:08 -04002575 uint64_t src_offset,
2576 uint64_t dst_offset,
2577 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02002578 struct radeon_fence **fence)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002579{
Christian König220907d2012-05-10 16:46:43 +02002580 struct radeon_semaphore *sem = NULL;
Christian Königf2377502012-05-09 15:35:01 +02002581 struct radeon_sa_bo *vb = NULL;
Jerome Glisseff82f052010-01-22 15:19:00 +01002582 int r;
2583
Christian König220907d2012-05-10 16:46:43 +02002584 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
Jerome Glisseff82f052010-01-22 15:19:00 +01002585 if (r) {
Jerome Glisseff82f052010-01-22 15:19:00 +01002586 return r;
2587 }
Christian Königf2377502012-05-09 15:35:01 +02002588 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
Christian König220907d2012-05-10 16:46:43 +02002589 r600_blit_done_copy(rdev, fence, vb, sem);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002590 return 0;
2591}
2592
Alex Deucher4d756582012-09-27 15:08:35 -04002593/**
2594 * r600_copy_dma - copy pages using the DMA engine
2595 *
2596 * @rdev: radeon_device pointer
2597 * @src_offset: src GPU address
2598 * @dst_offset: dst GPU address
2599 * @num_gpu_pages: number of GPU pages to xfer
2600 * @fence: radeon fence object
2601 *
2602 * Copy GPU paging using the DMA engine (r6xx-r7xx).
2603 * Used by the radeon ttm implementation to move pages if
2604 * registered as the asic copy callback.
2605 */
2606int r600_copy_dma(struct radeon_device *rdev,
2607 uint64_t src_offset, uint64_t dst_offset,
2608 unsigned num_gpu_pages,
2609 struct radeon_fence **fence)
2610{
2611 struct radeon_semaphore *sem = NULL;
2612 int ring_index = rdev->asic->copy.dma_ring_index;
2613 struct radeon_ring *ring = &rdev->ring[ring_index];
2614 u32 size_in_dw, cur_size_in_dw;
2615 int i, num_loops;
2616 int r = 0;
2617
2618 r = radeon_semaphore_create(rdev, &sem);
2619 if (r) {
2620 DRM_ERROR("radeon: moving bo (%d).\n", r);
2621 return r;
2622 }
2623
2624 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2625 num_loops = DIV_ROUND_UP(size_in_dw, 0xffff);
2626 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
2627 if (r) {
2628 DRM_ERROR("radeon: moving bo (%d).\n", r);
2629 radeon_semaphore_free(rdev, &sem, NULL);
2630 return r;
2631 }
2632
2633 if (radeon_fence_need_sync(*fence, ring->idx)) {
2634 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2635 ring->idx);
2636 radeon_fence_note_sync(*fence, ring->idx);
2637 } else {
2638 radeon_semaphore_free(rdev, &sem, NULL);
2639 }
2640
2641 for (i = 0; i < num_loops; i++) {
2642 cur_size_in_dw = size_in_dw;
Alex Deucher909d9eb2013-01-02 18:30:21 -05002643 if (cur_size_in_dw > 0xFFFE)
2644 cur_size_in_dw = 0xFFFE;
Alex Deucher4d756582012-09-27 15:08:35 -04002645 size_in_dw -= cur_size_in_dw;
2646 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2647 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2648 radeon_ring_write(ring, src_offset & 0xfffffffc);
2649 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2650 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
2651 src_offset += cur_size_in_dw * 4;
2652 dst_offset += cur_size_in_dw * 4;
2653 }
2654
2655 r = radeon_fence_emit(rdev, fence, ring->idx);
2656 if (r) {
2657 radeon_ring_unlock_undo(rdev, ring);
2658 return r;
2659 }
2660
2661 radeon_ring_unlock_commit(rdev, ring);
2662 radeon_semaphore_free(rdev, &sem, *fence);
2663
2664 return r;
2665}
2666
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002667int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2668 uint32_t tiling_flags, uint32_t pitch,
2669 uint32_t offset, uint32_t obj_size)
2670{
2671 /* FIXME: implement */
2672 return 0;
2673}
2674
2675void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2676{
2677 /* FIXME: implement */
2678}
2679
Lauri Kasanen1109ca02012-08-31 13:43:50 -04002680static int r600_startup(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002681{
Alex Deucher4d756582012-09-27 15:08:35 -04002682 struct radeon_ring *ring;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002683 int r;
2684
Alex Deucher9e46a482011-01-06 18:49:35 -05002685 /* enable pcie gen2 link */
2686 r600_pcie_gen2_enable(rdev);
2687
Alex Deucher779720a2009-12-09 19:31:44 -05002688 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2689 r = r600_init_microcode(rdev);
2690 if (r) {
2691 DRM_ERROR("Failed to load firmware!\n");
2692 return r;
2693 }
2694 }
2695
Alex Deucher16cdf042011-10-28 10:30:02 -04002696 r = r600_vram_scratch_init(rdev);
2697 if (r)
2698 return r;
2699
Jerome Glissea3c19452009-10-01 18:02:13 +02002700 r600_mc_program(rdev);
Jerome Glisse1a029b72009-10-06 19:04:30 +02002701 if (rdev->flags & RADEON_IS_AGP) {
2702 r600_agp_enable(rdev);
2703 } else {
2704 r = r600_pcie_gart_enable(rdev);
2705 if (r)
2706 return r;
2707 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002708 r600_gpu_init(rdev);
Jerome Glissec38c7b62010-02-04 17:27:27 +01002709 r = r600_blit_init(rdev);
2710 if (r) {
2711 r600_blit_fini(rdev);
Alex Deucher27cd7762012-02-23 17:53:42 -05002712 rdev->asic->copy.copy = NULL;
Jerome Glissec38c7b62010-02-04 17:27:27 +01002713 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2714 }
Alex Deucherb70d6bb2010-08-06 21:36:58 -04002715
Alex Deucher724c80e2010-08-27 18:25:25 -04002716 /* allocate wb buffer */
2717 r = radeon_wb_init(rdev);
2718 if (r)
2719 return r;
2720
Jerome Glisse30eb77f2011-11-20 20:45:34 +00002721 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2722 if (r) {
2723 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2724 return r;
2725 }
2726
Alex Deucher4d756582012-09-27 15:08:35 -04002727 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2728 if (r) {
2729 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2730 return r;
2731 }
2732
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002733 /* Enable IRQ */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002734 r = r600_irq_init(rdev);
2735 if (r) {
2736 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2737 radeon_irq_kms_fini(rdev);
2738 return r;
2739 }
2740 r600_irq_set(rdev);
2741
Alex Deucher4d756582012-09-27 15:08:35 -04002742 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Christian Könige32eb502011-10-23 12:56:27 +02002743 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
Alex Deucher78c55602011-11-17 14:25:56 -05002744 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2745 0, 0xfffff, RADEON_CP_PACKET2);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002746 if (r)
2747 return r;
Alex Deucher4d756582012-09-27 15:08:35 -04002748
2749 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2750 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2751 DMA_RB_RPTR, DMA_RB_WPTR,
2752 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2753 if (r)
2754 return r;
2755
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002756 r = r600_cp_load_microcode(rdev);
2757 if (r)
2758 return r;
2759 r = r600_cp_resume(rdev);
2760 if (r)
2761 return r;
Alex Deucher724c80e2010-08-27 18:25:25 -04002762
Alex Deucher4d756582012-09-27 15:08:35 -04002763 r = r600_dma_resume(rdev);
2764 if (r)
2765 return r;
2766
Christian König2898c342012-07-05 11:55:34 +02002767 r = radeon_ib_pool_init(rdev);
2768 if (r) {
2769 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisseb15ba512011-11-15 11:48:34 -05002770 return r;
Christian König2898c342012-07-05 11:55:34 +02002771 }
Jerome Glisseb15ba512011-11-15 11:48:34 -05002772
Alex Deucherd4e30ef2012-06-04 17:18:51 -04002773 r = r600_audio_init(rdev);
2774 if (r) {
2775 DRM_ERROR("radeon: audio init failed\n");
2776 return r;
2777 }
2778
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002779 return 0;
2780}
2781
Dave Airlie28d52042009-09-21 14:33:58 +10002782void r600_vga_set_state(struct radeon_device *rdev, bool state)
2783{
2784 uint32_t temp;
2785
2786 temp = RREG32(CONFIG_CNTL);
2787 if (state == false) {
2788 temp &= ~(1<<0);
2789 temp |= (1<<1);
2790 } else {
2791 temp &= ~(1<<1);
2792 }
2793 WREG32(CONFIG_CNTL, temp);
2794}
2795
Dave Airliefc30b8e2009-09-18 15:19:37 +10002796int r600_resume(struct radeon_device *rdev)
2797{
2798 int r;
2799
Jerome Glisse1a029b72009-10-06 19:04:30 +02002800 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2801 * posting will perform necessary task to bring back GPU into good
2802 * shape.
2803 */
Dave Airliefc30b8e2009-09-18 15:19:37 +10002804 /* post card */
Jerome Glissee7d40b92009-10-01 18:02:15 +02002805 atom_asic_init(rdev->mode_info.atom_context);
Dave Airliefc30b8e2009-09-18 15:19:37 +10002806
Jerome Glisseb15ba512011-11-15 11:48:34 -05002807 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +10002808 r = r600_startup(rdev);
2809 if (r) {
2810 DRM_ERROR("r600 startup failed on resume\n");
Jerome Glisse6b7746e2012-02-20 17:57:20 -05002811 rdev->accel_working = false;
Dave Airliefc30b8e2009-09-18 15:19:37 +10002812 return r;
2813 }
2814
Dave Airliefc30b8e2009-09-18 15:19:37 +10002815 return r;
2816}
2817
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002818int r600_suspend(struct radeon_device *rdev)
2819{
Rafał Miłecki38fd2c62010-01-28 18:16:30 +01002820 r600_audio_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002821 r600_cp_stop(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -04002822 r600_dma_stop(rdev);
Jerome Glisse0c452492010-01-15 14:44:37 +01002823 r600_irq_suspend(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04002824 radeon_wb_disable(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02002825 r600_pcie_gart_disable(rdev);
Alex Deucher6ddddfe2011-10-14 10:51:22 -04002826
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002827 return 0;
2828}
2829
2830/* Plan is to move initialization in that function and use
2831 * helper function so that radeon_device_init pretty much
2832 * do nothing more than calling asic specific function. This
2833 * should also allow to remove a bunch of callback function
2834 * like vram_info.
2835 */
2836int r600_init(struct radeon_device *rdev)
2837{
2838 int r;
2839
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002840 if (r600_debugfs_mc_info_init(rdev)) {
2841 DRM_ERROR("Failed to register debugfs file for mc !\n");
2842 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002843 /* Read BIOS */
2844 if (!radeon_get_bios(rdev)) {
2845 if (ASIC_IS_AVIVO(rdev))
2846 return -EINVAL;
2847 }
2848 /* Must be an ATOMBIOS */
Jerome Glissee7d40b92009-10-01 18:02:15 +02002849 if (!rdev->is_atom_bios) {
2850 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002851 return -EINVAL;
Jerome Glissee7d40b92009-10-01 18:02:15 +02002852 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002853 r = radeon_atombios_init(rdev);
2854 if (r)
2855 return r;
2856 /* Post card if necessary */
Alex Deucherfd909c32011-01-11 18:08:59 -05002857 if (!radeon_card_posted(rdev)) {
Dave Airlie72542d72009-12-01 14:06:31 +10002858 if (!rdev->bios) {
2859 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2860 return -EINVAL;
2861 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002862 DRM_INFO("GPU not posted. posting now...\n");
2863 atom_asic_init(rdev->mode_info.atom_context);
2864 }
2865 /* Initialize scratch registers */
2866 r600_scratch_init(rdev);
2867 /* Initialize surface registers */
2868 radeon_surface_init(rdev);
Rafał Miłecki74338742009-11-03 00:53:02 +01002869 /* Initialize clocks */
Michel Dänzer5e6dde72009-09-17 09:42:28 +02002870 radeon_get_clock_info(rdev->ddev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002871 /* Fence driver */
Jerome Glisse30eb77f2011-11-20 20:45:34 +00002872 r = radeon_fence_driver_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002873 if (r)
2874 return r;
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002875 if (rdev->flags & RADEON_IS_AGP) {
2876 r = radeon_agp_init(rdev);
2877 if (r)
2878 radeon_agp_disable(rdev);
2879 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002880 r = r600_mc_init(rdev);
Jerome Glisseb574f252009-10-06 19:04:29 +02002881 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002882 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002883 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +01002884 r = radeon_bo_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002885 if (r)
2886 return r;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002887
2888 r = radeon_irq_kms_init(rdev);
2889 if (r)
2890 return r;
2891
Christian Könige32eb502011-10-23 12:56:27 +02002892 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2893 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002894
Alex Deucher4d756582012-09-27 15:08:35 -04002895 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2896 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2897
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002898 rdev->ih.ring_obj = NULL;
2899 r600_ih_ring_init(rdev, 64 * 1024);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002900
Jerome Glisse4aac0472009-09-14 18:29:49 +02002901 r = r600_pcie_gart_init(rdev);
2902 if (r)
2903 return r;
2904
Alex Deucher779720a2009-12-09 19:31:44 -05002905 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +10002906 r = r600_startup(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002907 if (r) {
Jerome Glisse655efd32010-02-02 11:51:45 +01002908 dev_err(rdev->dev, "disabling GPU acceleration\n");
2909 r600_cp_fini(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -04002910 r600_dma_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01002911 r600_irq_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04002912 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +02002913 radeon_ib_pool_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01002914 radeon_irq_kms_fini(rdev);
Jerome Glisse75c81292009-10-01 18:02:14 +02002915 r600_pcie_gart_fini(rdev);
Jerome Glisse733289c2009-09-16 15:24:21 +02002916 rdev->accel_working = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002917 }
Christian Koenigdafc3bd2009-10-11 23:49:13 +02002918
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002919 return 0;
2920}
2921
2922void r600_fini(struct radeon_device *rdev)
2923{
Christian Koenigdafc3bd2009-10-11 23:49:13 +02002924 r600_audio_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002925 r600_blit_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01002926 r600_cp_fini(rdev);
Alex Deucher4d756582012-09-27 15:08:35 -04002927 r600_dma_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002928 r600_irq_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04002929 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +02002930 radeon_ib_pool_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002931 radeon_irq_kms_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02002932 r600_pcie_gart_fini(rdev);
Alex Deucher16cdf042011-10-28 10:30:02 -04002933 r600_vram_scratch_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01002934 radeon_agp_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002935 radeon_gem_fini(rdev);
2936 radeon_fence_driver_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +01002937 radeon_bo_fini(rdev);
Jerome Glissee7d40b92009-10-01 18:02:15 +02002938 radeon_atombios_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002939 kfree(rdev->bios);
2940 rdev->bios = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002941}
2942
2943
2944/*
2945 * CS stuff
2946 */
2947void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2948{
Christian König876dc9f2012-05-08 14:24:01 +02002949 struct radeon_ring *ring = &rdev->ring[ib->ring];
Alex Deucher89d35802012-07-17 14:02:31 -04002950 u32 next_rptr;
Christian König7b1f2482011-09-23 15:11:23 +02002951
Christian König45df6802012-07-06 16:22:55 +02002952 if (ring->rptr_save_reg) {
Alex Deucher89d35802012-07-17 14:02:31 -04002953 next_rptr = ring->wptr + 3 + 4;
Christian König45df6802012-07-06 16:22:55 +02002954 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2955 radeon_ring_write(ring, ((ring->rptr_save_reg -
2956 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2957 radeon_ring_write(ring, next_rptr);
Alex Deucher89d35802012-07-17 14:02:31 -04002958 } else if (rdev->wb.enabled) {
2959 next_rptr = ring->wptr + 5 + 4;
2960 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2961 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2962 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2963 radeon_ring_write(ring, next_rptr);
2964 radeon_ring_write(ring, 0);
Christian König45df6802012-07-06 16:22:55 +02002965 }
2966
Christian Könige32eb502011-10-23 12:56:27 +02002967 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2968 radeon_ring_write(ring,
Cédric Cano4eace7f2011-02-11 19:45:38 -05002969#ifdef __BIG_ENDIAN
2970 (2 << 0) |
2971#endif
2972 (ib->gpu_addr & 0xFFFFFFFC));
Christian Könige32eb502011-10-23 12:56:27 +02002973 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2974 radeon_ring_write(ring, ib->length_dw);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002975}
2976
Alex Deucherf7128122012-02-23 17:53:45 -05002977int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002978{
Jerome Glissef2e39222012-05-09 15:35:02 +02002979 struct radeon_ib ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002980 uint32_t scratch;
2981 uint32_t tmp = 0;
2982 unsigned i;
2983 int r;
2984
2985 r = radeon_scratch_get(rdev, &scratch);
2986 if (r) {
2987 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2988 return r;
2989 }
2990 WREG32(scratch, 0xCAFEDEAD);
Christian König4bf3dd92012-08-06 18:57:44 +02002991 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002992 if (r) {
2993 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
Michel Dänzeraf026c52012-09-20 10:31:10 +02002994 goto free_scratch;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002995 }
Jerome Glissef2e39222012-05-09 15:35:02 +02002996 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2997 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2998 ib.ptr[2] = 0xDEADBEEF;
2999 ib.length_dw = 3;
Christian König4ef72562012-07-13 13:06:00 +02003000 r = radeon_ib_schedule(rdev, &ib, NULL);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003001 if (r) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003002 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
Michel Dänzeraf026c52012-09-20 10:31:10 +02003003 goto free_ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003004 }
Jerome Glissef2e39222012-05-09 15:35:02 +02003005 r = radeon_fence_wait(ib.fence, false);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003006 if (r) {
3007 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
Michel Dänzeraf026c52012-09-20 10:31:10 +02003008 goto free_ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003009 }
3010 for (i = 0; i < rdev->usec_timeout; i++) {
3011 tmp = RREG32(scratch);
3012 if (tmp == 0xDEADBEEF)
3013 break;
3014 DRM_UDELAY(1);
3015 }
3016 if (i < rdev->usec_timeout) {
Jerome Glissef2e39222012-05-09 15:35:02 +02003017 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003018 } else {
Daniel J Blueman4417d7f2010-09-22 17:57:19 +01003019 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003020 scratch, tmp);
3021 r = -EINVAL;
3022 }
Michel Dänzeraf026c52012-09-20 10:31:10 +02003023free_ib:
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003024 radeon_ib_free(rdev, &ib);
Michel Dänzeraf026c52012-09-20 10:31:10 +02003025free_scratch:
3026 radeon_scratch_free(rdev, scratch);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003027 return r;
3028}
3029
Alex Deucher4d756582012-09-27 15:08:35 -04003030/**
3031 * r600_dma_ib_test - test an IB on the DMA engine
3032 *
3033 * @rdev: radeon_device pointer
3034 * @ring: radeon_ring structure holding ring information
3035 *
3036 * Test a simple IB in the DMA ring (r6xx-SI).
3037 * Returns 0 on success, error on failure.
3038 */
3039int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3040{
3041 struct radeon_ib ib;
3042 unsigned i;
3043 int r;
3044 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3045 u32 tmp = 0;
3046
3047 if (!ptr) {
3048 DRM_ERROR("invalid vram scratch pointer\n");
3049 return -EINVAL;
3050 }
3051
3052 tmp = 0xCAFEDEAD;
3053 writel(tmp, ptr);
3054
3055 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3056 if (r) {
3057 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3058 return r;
3059 }
3060
3061 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3062 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3063 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3064 ib.ptr[3] = 0xDEADBEEF;
3065 ib.length_dw = 4;
3066
3067 r = radeon_ib_schedule(rdev, &ib, NULL);
3068 if (r) {
3069 radeon_ib_free(rdev, &ib);
3070 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3071 return r;
3072 }
3073 r = radeon_fence_wait(ib.fence, false);
3074 if (r) {
3075 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3076 return r;
3077 }
3078 for (i = 0; i < rdev->usec_timeout; i++) {
3079 tmp = readl(ptr);
3080 if (tmp == 0xDEADBEEF)
3081 break;
3082 DRM_UDELAY(1);
3083 }
3084 if (i < rdev->usec_timeout) {
3085 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3086 } else {
3087 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3088 r = -EINVAL;
3089 }
3090 radeon_ib_free(rdev, &ib);
3091 return r;
3092}
3093
3094/**
3095 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3096 *
3097 * @rdev: radeon_device pointer
3098 * @ib: IB object to schedule
3099 *
3100 * Schedule an IB in the DMA ring (r6xx-r7xx).
3101 */
3102void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3103{
3104 struct radeon_ring *ring = &rdev->ring[ib->ring];
3105
3106 if (rdev->wb.enabled) {
3107 u32 next_rptr = ring->wptr + 4;
3108 while ((next_rptr & 7) != 5)
3109 next_rptr++;
3110 next_rptr += 3;
3111 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3112 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3113 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3114 radeon_ring_write(ring, next_rptr);
3115 }
3116
3117 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3118 * Pad as necessary with NOPs.
3119 */
3120 while ((ring->wptr & 7) != 5)
3121 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3122 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3123 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3124 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3125
3126}
3127
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003128/*
3129 * Interrupts
3130 *
3131 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3132 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3133 * writing to the ring and the GPU consuming, the GPU writes to the ring
3134 * and host consumes. As the host irq handler processes interrupts, it
3135 * increments the rptr. When the rptr catches up with the wptr, all the
3136 * current interrupts have been processed.
3137 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003138
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003139void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3140{
3141 u32 rb_bufsz;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003142
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003143 /* Align ring size */
3144 rb_bufsz = drm_order(ring_size / 4);
3145 ring_size = (1 << rb_bufsz) * 4;
3146 rdev->ih.ring_size = ring_size;
Jerome Glisse0c452492010-01-15 14:44:37 +01003147 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3148 rdev->ih.rptr = 0;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003149}
3150
Alex Deucher25a857f2012-03-20 17:18:22 -04003151int r600_ih_ring_alloc(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003152{
3153 int r;
3154
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003155 /* Allocate ring buffer */
3156 if (rdev->ih.ring_obj == NULL) {
Daniel Vetter441921d2011-02-18 17:59:16 +01003157 r = radeon_bo_create(rdev, rdev->ih.ring_size,
Alex Deucher268b2512010-11-17 19:00:26 -05003158 PAGE_SIZE, true,
Jerome Glisse4c788672009-11-20 14:29:23 +01003159 RADEON_GEM_DOMAIN_GTT,
Alex Deucher40f5cf92012-05-10 18:33:13 -04003160 NULL, &rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003161 if (r) {
3162 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3163 return r;
3164 }
Jerome Glisse4c788672009-11-20 14:29:23 +01003165 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3166 if (unlikely(r != 0))
3167 return r;
3168 r = radeon_bo_pin(rdev->ih.ring_obj,
3169 RADEON_GEM_DOMAIN_GTT,
3170 &rdev->ih.gpu_addr);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003171 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +01003172 radeon_bo_unreserve(rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003173 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3174 return r;
3175 }
Jerome Glisse4c788672009-11-20 14:29:23 +01003176 r = radeon_bo_kmap(rdev->ih.ring_obj,
3177 (void **)&rdev->ih.ring);
3178 radeon_bo_unreserve(rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003179 if (r) {
3180 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3181 return r;
3182 }
3183 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003184 return 0;
3185}
3186
Alex Deucher25a857f2012-03-20 17:18:22 -04003187void r600_ih_ring_fini(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003188{
Jerome Glisse4c788672009-11-20 14:29:23 +01003189 int r;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003190 if (rdev->ih.ring_obj) {
Jerome Glisse4c788672009-11-20 14:29:23 +01003191 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3192 if (likely(r == 0)) {
3193 radeon_bo_kunmap(rdev->ih.ring_obj);
3194 radeon_bo_unpin(rdev->ih.ring_obj);
3195 radeon_bo_unreserve(rdev->ih.ring_obj);
3196 }
3197 radeon_bo_unref(&rdev->ih.ring_obj);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003198 rdev->ih.ring = NULL;
3199 rdev->ih.ring_obj = NULL;
3200 }
3201}
3202
Alex Deucher45f9a392010-03-24 13:55:51 -04003203void r600_rlc_stop(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003204{
3205
Alex Deucher45f9a392010-03-24 13:55:51 -04003206 if ((rdev->family >= CHIP_RV770) &&
3207 (rdev->family <= CHIP_RV740)) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003208 /* r7xx asics need to soft reset RLC before halting */
3209 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3210 RREG32(SRBM_SOFT_RESET);
Arnd Bergmann4de833c2012-04-05 12:58:22 -06003211 mdelay(15);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003212 WREG32(SRBM_SOFT_RESET, 0);
3213 RREG32(SRBM_SOFT_RESET);
3214 }
3215
3216 WREG32(RLC_CNTL, 0);
3217}
3218
3219static void r600_rlc_start(struct radeon_device *rdev)
3220{
3221 WREG32(RLC_CNTL, RLC_ENABLE);
3222}
3223
3224static int r600_rlc_init(struct radeon_device *rdev)
3225{
3226 u32 i;
3227 const __be32 *fw_data;
3228
3229 if (!rdev->rlc_fw)
3230 return -EINVAL;
3231
3232 r600_rlc_stop(rdev);
3233
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003234 WREG32(RLC_HB_CNTL, 0);
Alex Deucherc420c742012-03-20 17:18:39 -04003235
3236 if (rdev->family == CHIP_ARUBA) {
3237 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3238 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3239 }
3240 if (rdev->family <= CHIP_CAYMAN) {
3241 WREG32(RLC_HB_BASE, 0);
3242 WREG32(RLC_HB_RPTR, 0);
3243 WREG32(RLC_HB_WPTR, 0);
3244 }
Alex Deucher12727802011-03-02 20:07:32 -05003245 if (rdev->family <= CHIP_CAICOS) {
3246 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3247 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3248 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003249 WREG32(RLC_MC_CNTL, 0);
3250 WREG32(RLC_UCODE_CNTL, 0);
3251
3252 fw_data = (const __be32 *)rdev->rlc_fw->data;
Alex Deucherc420c742012-03-20 17:18:39 -04003253 if (rdev->family >= CHIP_ARUBA) {
3254 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3255 WREG32(RLC_UCODE_ADDR, i);
3256 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3257 }
3258 } else if (rdev->family >= CHIP_CAYMAN) {
Alex Deucher12727802011-03-02 20:07:32 -05003259 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3260 WREG32(RLC_UCODE_ADDR, i);
3261 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3262 }
3263 } else if (rdev->family >= CHIP_CEDAR) {
Alex Deucher45f9a392010-03-24 13:55:51 -04003264 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3265 WREG32(RLC_UCODE_ADDR, i);
3266 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3267 }
3268 } else if (rdev->family >= CHIP_RV770) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003269 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3270 WREG32(RLC_UCODE_ADDR, i);
3271 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3272 }
3273 } else {
3274 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3275 WREG32(RLC_UCODE_ADDR, i);
3276 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3277 }
3278 }
3279 WREG32(RLC_UCODE_ADDR, 0);
3280
3281 r600_rlc_start(rdev);
3282
3283 return 0;
3284}
3285
3286static void r600_enable_interrupts(struct radeon_device *rdev)
3287{
3288 u32 ih_cntl = RREG32(IH_CNTL);
3289 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3290
3291 ih_cntl |= ENABLE_INTR;
3292 ih_rb_cntl |= IH_RB_ENABLE;
3293 WREG32(IH_CNTL, ih_cntl);
3294 WREG32(IH_RB_CNTL, ih_rb_cntl);
3295 rdev->ih.enabled = true;
3296}
3297
Alex Deucher45f9a392010-03-24 13:55:51 -04003298void r600_disable_interrupts(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003299{
3300 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3301 u32 ih_cntl = RREG32(IH_CNTL);
3302
3303 ih_rb_cntl &= ~IH_RB_ENABLE;
3304 ih_cntl &= ~ENABLE_INTR;
3305 WREG32(IH_RB_CNTL, ih_rb_cntl);
3306 WREG32(IH_CNTL, ih_cntl);
3307 /* set rptr, wptr to 0 */
3308 WREG32(IH_RB_RPTR, 0);
3309 WREG32(IH_RB_WPTR, 0);
3310 rdev->ih.enabled = false;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003311 rdev->ih.rptr = 0;
3312}
3313
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003314static void r600_disable_interrupt_state(struct radeon_device *rdev)
3315{
3316 u32 tmp;
3317
Alex Deucher3555e532010-10-08 12:09:12 -04003318 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
Alex Deucher4d756582012-09-27 15:08:35 -04003319 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3320 WREG32(DMA_CNTL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003321 WREG32(GRBM_INT_CNTL, 0);
3322 WREG32(DxMODE_INT_MASK, 0);
Alex Deucher6f34be52010-11-21 10:59:01 -05003323 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3324 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003325 if (ASIC_IS_DCE3(rdev)) {
3326 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3327 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3328 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3329 WREG32(DC_HPD1_INT_CONTROL, tmp);
3330 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3331 WREG32(DC_HPD2_INT_CONTROL, tmp);
3332 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3333 WREG32(DC_HPD3_INT_CONTROL, tmp);
3334 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3335 WREG32(DC_HPD4_INT_CONTROL, tmp);
3336 if (ASIC_IS_DCE32(rdev)) {
3337 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -04003338 WREG32(DC_HPD5_INT_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003339 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -04003340 WREG32(DC_HPD6_INT_CONTROL, tmp);
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003341 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3342 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3343 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3344 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
Alex Deucherf122c612012-03-30 08:59:57 -04003345 } else {
3346 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3347 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3348 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3349 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003350 }
3351 } else {
3352 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3353 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3354 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -04003355 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003356 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -04003357 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003358 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
Alex Deucher5898b1f2010-03-24 13:57:29 -04003359 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
Alex Deucherf122c612012-03-30 08:59:57 -04003360 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3361 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3362 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3363 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003364 }
3365}
3366
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003367int r600_irq_init(struct radeon_device *rdev)
3368{
3369 int ret = 0;
3370 int rb_bufsz;
3371 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3372
3373 /* allocate ring */
Jerome Glisse0c452492010-01-15 14:44:37 +01003374 ret = r600_ih_ring_alloc(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003375 if (ret)
3376 return ret;
3377
3378 /* disable irqs */
3379 r600_disable_interrupts(rdev);
3380
3381 /* init rlc */
3382 ret = r600_rlc_init(rdev);
3383 if (ret) {
3384 r600_ih_ring_fini(rdev);
3385 return ret;
3386 }
3387
3388 /* setup interrupt control */
3389 /* set dummy read address to ring address */
3390 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3391 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3392 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3393 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3394 */
3395 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3396 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3397 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3398 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3399
3400 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3401 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3402
3403 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3404 IH_WPTR_OVERFLOW_CLEAR |
3405 (rb_bufsz << 1));
Alex Deucher724c80e2010-08-27 18:25:25 -04003406
3407 if (rdev->wb.enabled)
3408 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3409
3410 /* set the writeback address whether it's enabled or not */
3411 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3412 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003413
3414 WREG32(IH_RB_CNTL, ih_rb_cntl);
3415
3416 /* set rptr, wptr to 0 */
3417 WREG32(IH_RB_RPTR, 0);
3418 WREG32(IH_RB_WPTR, 0);
3419
3420 /* Default settings for IH_CNTL (disabled at first) */
3421 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3422 /* RPTR_REARM only works if msi's are enabled */
3423 if (rdev->msi_enabled)
3424 ih_cntl |= RPTR_REARM;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003425 WREG32(IH_CNTL, ih_cntl);
3426
3427 /* force the active interrupt state to all disabled */
Alex Deucher45f9a392010-03-24 13:55:51 -04003428 if (rdev->family >= CHIP_CEDAR)
3429 evergreen_disable_interrupt_state(rdev);
3430 else
3431 r600_disable_interrupt_state(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003432
Dave Airlie20998102012-04-03 11:53:05 +01003433 /* at this point everything should be setup correctly to enable master */
3434 pci_set_master(rdev->pdev);
3435
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003436 /* enable irqs */
3437 r600_enable_interrupts(rdev);
3438
3439 return ret;
3440}
3441
Jerome Glisse0c452492010-01-15 14:44:37 +01003442void r600_irq_suspend(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003443{
Alex Deucher45f9a392010-03-24 13:55:51 -04003444 r600_irq_disable(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003445 r600_rlc_stop(rdev);
Jerome Glisse0c452492010-01-15 14:44:37 +01003446}
3447
3448void r600_irq_fini(struct radeon_device *rdev)
3449{
3450 r600_irq_suspend(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003451 r600_ih_ring_fini(rdev);
3452}
3453
3454int r600_irq_set(struct radeon_device *rdev)
3455{
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003456 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3457 u32 mode_int = 0;
3458 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
Alex Deucher2031f772010-04-22 12:52:11 -04003459 u32 grbm_int_cntl = 0;
Alex Deucherf122c612012-03-30 08:59:57 -04003460 u32 hdmi0, hdmi1;
Alex Deucher6f34be52010-11-21 10:59:01 -05003461 u32 d1grph = 0, d2grph = 0;
Alex Deucher4d756582012-09-27 15:08:35 -04003462 u32 dma_cntl;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003463
Jerome Glisse003e69f2010-01-07 15:39:14 +01003464 if (!rdev->irq.installed) {
Joe Perchesfce7d612010-10-30 21:08:30 +00003465 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
Jerome Glisse003e69f2010-01-07 15:39:14 +01003466 return -EINVAL;
3467 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003468 /* don't enable anything if the ih is disabled */
Jerome Glisse79c2bbc2010-01-15 14:44:38 +01003469 if (!rdev->ih.enabled) {
3470 r600_disable_interrupts(rdev);
3471 /* force the active interrupt state to all disabled */
3472 r600_disable_interrupt_state(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003473 return 0;
Jerome Glisse79c2bbc2010-01-15 14:44:38 +01003474 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003475
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003476 if (ASIC_IS_DCE3(rdev)) {
3477 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3478 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3479 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3480 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3481 if (ASIC_IS_DCE32(rdev)) {
3482 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3483 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003484 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3485 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
Alex Deucherf122c612012-03-30 08:59:57 -04003486 } else {
3487 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3488 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003489 }
3490 } else {
3491 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3492 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3493 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
Alex Deucherf122c612012-03-30 08:59:57 -04003494 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3495 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003496 }
Alex Deucher4d756582012-09-27 15:08:35 -04003497 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003498
Christian Koenig736fc372012-05-17 19:52:00 +02003499 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003500 DRM_DEBUG("r600_irq_set: sw int\n");
3501 cp_int_cntl |= RB_INT_ENABLE;
Alex Deucherd0f8a852010-09-04 05:04:34 -04003502 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003503 }
Alex Deucher4d756582012-09-27 15:08:35 -04003504
3505 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3506 DRM_DEBUG("r600_irq_set: sw int dma\n");
3507 dma_cntl |= TRAP_ENABLE;
3508 }
3509
Alex Deucher6f34be52010-11-21 10:59:01 -05003510 if (rdev->irq.crtc_vblank_int[0] ||
Christian Koenig736fc372012-05-17 19:52:00 +02003511 atomic_read(&rdev->irq.pflip[0])) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003512 DRM_DEBUG("r600_irq_set: vblank 0\n");
3513 mode_int |= D1MODE_VBLANK_INT_MASK;
3514 }
Alex Deucher6f34be52010-11-21 10:59:01 -05003515 if (rdev->irq.crtc_vblank_int[1] ||
Christian Koenig736fc372012-05-17 19:52:00 +02003516 atomic_read(&rdev->irq.pflip[1])) {
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003517 DRM_DEBUG("r600_irq_set: vblank 1\n");
3518 mode_int |= D2MODE_VBLANK_INT_MASK;
3519 }
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003520 if (rdev->irq.hpd[0]) {
3521 DRM_DEBUG("r600_irq_set: hpd 1\n");
3522 hpd1 |= DC_HPDx_INT_EN;
3523 }
3524 if (rdev->irq.hpd[1]) {
3525 DRM_DEBUG("r600_irq_set: hpd 2\n");
3526 hpd2 |= DC_HPDx_INT_EN;
3527 }
3528 if (rdev->irq.hpd[2]) {
3529 DRM_DEBUG("r600_irq_set: hpd 3\n");
3530 hpd3 |= DC_HPDx_INT_EN;
3531 }
3532 if (rdev->irq.hpd[3]) {
3533 DRM_DEBUG("r600_irq_set: hpd 4\n");
3534 hpd4 |= DC_HPDx_INT_EN;
3535 }
3536 if (rdev->irq.hpd[4]) {
3537 DRM_DEBUG("r600_irq_set: hpd 5\n");
3538 hpd5 |= DC_HPDx_INT_EN;
3539 }
3540 if (rdev->irq.hpd[5]) {
3541 DRM_DEBUG("r600_irq_set: hpd 6\n");
3542 hpd6 |= DC_HPDx_INT_EN;
3543 }
Alex Deucherf122c612012-03-30 08:59:57 -04003544 if (rdev->irq.afmt[0]) {
3545 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3546 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
Christian Koenigf2594932010-04-10 03:13:16 +02003547 }
Alex Deucherf122c612012-03-30 08:59:57 -04003548 if (rdev->irq.afmt[1]) {
3549 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3550 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
Christian Koenigf2594932010-04-10 03:13:16 +02003551 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003552
3553 WREG32(CP_INT_CNTL, cp_int_cntl);
Alex Deucher4d756582012-09-27 15:08:35 -04003554 WREG32(DMA_CNTL, dma_cntl);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003555 WREG32(DxMODE_INT_MASK, mode_int);
Alex Deucher6f34be52010-11-21 10:59:01 -05003556 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3557 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
Alex Deucher2031f772010-04-22 12:52:11 -04003558 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003559 if (ASIC_IS_DCE3(rdev)) {
3560 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3561 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3562 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3563 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3564 if (ASIC_IS_DCE32(rdev)) {
3565 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3566 WREG32(DC_HPD6_INT_CONTROL, hpd6);
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003567 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3568 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
Alex Deucherf122c612012-03-30 08:59:57 -04003569 } else {
3570 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3571 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003572 }
3573 } else {
3574 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3575 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3576 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
Alex Deucherf122c612012-03-30 08:59:57 -04003577 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3578 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003579 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003580
3581 return 0;
3582}
3583
Andi Kleence580fa2011-10-13 16:08:47 -07003584static void r600_irq_ack(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003585{
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003586 u32 tmp;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003587
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003588 if (ASIC_IS_DCE3(rdev)) {
Alex Deucher6f34be52010-11-21 10:59:01 -05003589 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3590 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3591 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
Alex Deucherf122c612012-03-30 08:59:57 -04003592 if (ASIC_IS_DCE32(rdev)) {
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003593 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3594 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
Alex Deucherf122c612012-03-30 08:59:57 -04003595 } else {
3596 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3597 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3598 }
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003599 } else {
Alex Deucher6f34be52010-11-21 10:59:01 -05003600 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3601 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3602 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
Alex Deucherf122c612012-03-30 08:59:57 -04003603 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3604 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003605 }
Alex Deucher6f34be52010-11-21 10:59:01 -05003606 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3607 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003608
Alex Deucher6f34be52010-11-21 10:59:01 -05003609 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3610 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3611 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3612 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3613 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003614 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -05003615 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003616 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -05003617 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003618 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -05003619 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003620 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
Alex Deucher6f34be52010-11-21 10:59:01 -05003621 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003622 if (ASIC_IS_DCE3(rdev)) {
3623 tmp = RREG32(DC_HPD1_INT_CONTROL);
3624 tmp |= DC_HPDx_INT_ACK;
3625 WREG32(DC_HPD1_INT_CONTROL, tmp);
3626 } else {
3627 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3628 tmp |= DC_HPDx_INT_ACK;
3629 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3630 }
3631 }
Alex Deucher6f34be52010-11-21 10:59:01 -05003632 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003633 if (ASIC_IS_DCE3(rdev)) {
3634 tmp = RREG32(DC_HPD2_INT_CONTROL);
3635 tmp |= DC_HPDx_INT_ACK;
3636 WREG32(DC_HPD2_INT_CONTROL, tmp);
3637 } else {
3638 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3639 tmp |= DC_HPDx_INT_ACK;
3640 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3641 }
3642 }
Alex Deucher6f34be52010-11-21 10:59:01 -05003643 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003644 if (ASIC_IS_DCE3(rdev)) {
3645 tmp = RREG32(DC_HPD3_INT_CONTROL);
3646 tmp |= DC_HPDx_INT_ACK;
3647 WREG32(DC_HPD3_INT_CONTROL, tmp);
3648 } else {
3649 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3650 tmp |= DC_HPDx_INT_ACK;
3651 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3652 }
3653 }
Alex Deucher6f34be52010-11-21 10:59:01 -05003654 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003655 tmp = RREG32(DC_HPD4_INT_CONTROL);
3656 tmp |= DC_HPDx_INT_ACK;
3657 WREG32(DC_HPD4_INT_CONTROL, tmp);
3658 }
3659 if (ASIC_IS_DCE32(rdev)) {
Alex Deucher6f34be52010-11-21 10:59:01 -05003660 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003661 tmp = RREG32(DC_HPD5_INT_CONTROL);
3662 tmp |= DC_HPDx_INT_ACK;
3663 WREG32(DC_HPD5_INT_CONTROL, tmp);
3664 }
Alex Deucher6f34be52010-11-21 10:59:01 -05003665 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003666 tmp = RREG32(DC_HPD5_INT_CONTROL);
3667 tmp |= DC_HPDx_INT_ACK;
3668 WREG32(DC_HPD6_INT_CONTROL, tmp);
3669 }
Alex Deucherf122c612012-03-30 08:59:57 -04003670 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003671 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
Alex Deucherf122c612012-03-30 08:59:57 -04003672 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003673 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
Alex Deucherf122c612012-03-30 08:59:57 -04003674 }
3675 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003676 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
Alex Deucherf122c612012-03-30 08:59:57 -04003677 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
Rafał Miłeckic6543a62012-04-28 23:35:24 +02003678 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
Christian Koenigf2594932010-04-10 03:13:16 +02003679 }
3680 } else {
Alex Deucherf122c612012-03-30 08:59:57 -04003681 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3682 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3683 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3684 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3685 }
3686 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3687 if (ASIC_IS_DCE3(rdev)) {
3688 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3689 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3690 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3691 } else {
3692 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3693 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3694 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3695 }
Christian Koenigf2594932010-04-10 03:13:16 +02003696 }
3697 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003698}
3699
3700void r600_irq_disable(struct radeon_device *rdev)
3701{
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003702 r600_disable_interrupts(rdev);
3703 /* Wait and acknowledge irq */
3704 mdelay(1);
Alex Deucher6f34be52010-11-21 10:59:01 -05003705 r600_irq_ack(rdev);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003706 r600_disable_interrupt_state(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003707}
3708
Andi Kleence580fa2011-10-13 16:08:47 -07003709static u32 r600_get_ih_wptr(struct radeon_device *rdev)
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003710{
3711 u32 wptr, tmp;
3712
Alex Deucher724c80e2010-08-27 18:25:25 -04003713 if (rdev->wb.enabled)
Cédric Cano204ae242011-04-19 11:07:13 -04003714 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
Alex Deucher724c80e2010-08-27 18:25:25 -04003715 else
3716 wptr = RREG32(IH_RB_WPTR);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003717
3718 if (wptr & RB_OVERFLOW) {
Jerome Glisse7924e5e2010-01-15 14:44:39 +01003719 /* When a ring buffer overflow happen start parsing interrupt
3720 * from the last not overwritten vector (wptr + 16). Hopefully
3721 * this should allow us to catchup.
3722 */
3723 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3724 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3725 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003726 tmp = RREG32(IH_RB_CNTL);
3727 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3728 WREG32(IH_RB_CNTL, tmp);
3729 }
Jerome Glisse0c452492010-01-15 14:44:37 +01003730 return (wptr & rdev->ih.ptr_mask);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003731}
3732
3733/* r600 IV Ring
3734 * Each IV ring entry is 128 bits:
3735 * [7:0] - interrupt source id
3736 * [31:8] - reserved
3737 * [59:32] - interrupt source data
3738 * [127:60] - reserved
3739 *
3740 * The basic interrupt vector entries
3741 * are decoded as follows:
3742 * src_id src_data description
3743 * 1 0 D1 Vblank
3744 * 1 1 D1 Vline
3745 * 5 0 D2 Vblank
3746 * 5 1 D2 Vline
3747 * 19 0 FP Hot plug detection A
3748 * 19 1 FP Hot plug detection B
3749 * 19 2 DAC A auto-detection
3750 * 19 3 DAC B auto-detection
Christian Koenigf2594932010-04-10 03:13:16 +02003751 * 21 4 HDMI block A
3752 * 21 5 HDMI block B
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003753 * 176 - CP_INT RB
3754 * 177 - CP_INT IB1
3755 * 178 - CP_INT IB2
3756 * 181 - EOP Interrupt
3757 * 233 - GUI Idle
3758 *
3759 * Note, these are based on r600 and may need to be
3760 * adjusted or added to on newer asics
3761 */
3762
3763int r600_irq_process(struct radeon_device *rdev)
3764{
Dave Airlie682f1a52011-06-18 03:59:51 +00003765 u32 wptr;
3766 u32 rptr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003767 u32 src_id, src_data;
Alex Deucher6f34be52010-11-21 10:59:01 -05003768 u32 ring_index;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003769 bool queue_hotplug = false;
Alex Deucherf122c612012-03-30 08:59:57 -04003770 bool queue_hdmi = false;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003771
Dave Airlie682f1a52011-06-18 03:59:51 +00003772 if (!rdev->ih.enabled || rdev->shutdown)
Jerome Glisse79c2bbc2010-01-15 14:44:38 +01003773 return IRQ_NONE;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003774
Benjamin Herrenschmidtf6a56932011-07-13 06:28:22 +00003775 /* No MSIs, need a dummy read to flush PCI DMAs */
3776 if (!rdev->msi_enabled)
3777 RREG32(IH_RB_WPTR);
3778
Dave Airlie682f1a52011-06-18 03:59:51 +00003779 wptr = r600_get_ih_wptr(rdev);
Christian Koenigc20dc362012-05-16 21:45:24 +02003780
3781restart_ih:
3782 /* is somebody else already processing irqs? */
3783 if (atomic_xchg(&rdev->ih.lock, 1))
3784 return IRQ_NONE;
3785
Dave Airlie682f1a52011-06-18 03:59:51 +00003786 rptr = rdev->ih.rptr;
3787 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3788
Benjamin Herrenschmidt964f6642011-07-13 16:28:19 +10003789 /* Order reading of wptr vs. reading of IH ring data */
3790 rmb();
3791
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003792 /* display interrupts */
Alex Deucher6f34be52010-11-21 10:59:01 -05003793 r600_irq_ack(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003794
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003795 while (rptr != wptr) {
3796 /* wptr/rptr are in bytes! */
3797 ring_index = rptr / 4;
Cédric Cano4eace7f2011-02-11 19:45:38 -05003798 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3799 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003800
3801 switch (src_id) {
3802 case 1: /* D1 vblank/vline */
3803 switch (src_data) {
3804 case 0: /* D1 vblank */
Alex Deucher6f34be52010-11-21 10:59:01 -05003805 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
Alex Deucher6f34be52010-11-21 10:59:01 -05003806 if (rdev->irq.crtc_vblank_int[0]) {
3807 drm_handle_vblank(rdev->ddev, 0);
3808 rdev->pm.vblank_sync = true;
3809 wake_up(&rdev->irq.vblank_queue);
3810 }
Christian Koenig736fc372012-05-17 19:52:00 +02003811 if (atomic_read(&rdev->irq.pflip[0]))
Mario Kleiner3e4ea742010-11-21 10:59:02 -05003812 radeon_crtc_handle_flip(rdev, 0);
Alex Deucher6f34be52010-11-21 10:59:01 -05003813 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003814 DRM_DEBUG("IH: D1 vblank\n");
3815 }
3816 break;
3817 case 1: /* D1 vline */
Alex Deucher6f34be52010-11-21 10:59:01 -05003818 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3819 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003820 DRM_DEBUG("IH: D1 vline\n");
3821 }
3822 break;
3823 default:
Alex Deucherb0425892010-01-11 19:47:38 -05003824 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003825 break;
3826 }
3827 break;
3828 case 5: /* D2 vblank/vline */
3829 switch (src_data) {
3830 case 0: /* D2 vblank */
Alex Deucher6f34be52010-11-21 10:59:01 -05003831 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
Alex Deucher6f34be52010-11-21 10:59:01 -05003832 if (rdev->irq.crtc_vblank_int[1]) {
3833 drm_handle_vblank(rdev->ddev, 1);
3834 rdev->pm.vblank_sync = true;
3835 wake_up(&rdev->irq.vblank_queue);
3836 }
Christian Koenig736fc372012-05-17 19:52:00 +02003837 if (atomic_read(&rdev->irq.pflip[1]))
Mario Kleiner3e4ea742010-11-21 10:59:02 -05003838 radeon_crtc_handle_flip(rdev, 1);
Alex Deucher6f34be52010-11-21 10:59:01 -05003839 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003840 DRM_DEBUG("IH: D2 vblank\n");
3841 }
3842 break;
3843 case 1: /* D1 vline */
Alex Deucher6f34be52010-11-21 10:59:01 -05003844 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3845 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003846 DRM_DEBUG("IH: D2 vline\n");
3847 }
3848 break;
3849 default:
Alex Deucherb0425892010-01-11 19:47:38 -05003850 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003851 break;
3852 }
3853 break;
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003854 case 19: /* HPD/DAC hotplug */
3855 switch (src_data) {
3856 case 0:
Alex Deucher6f34be52010-11-21 10:59:01 -05003857 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3858 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003859 queue_hotplug = true;
3860 DRM_DEBUG("IH: HPD1\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003861 }
3862 break;
3863 case 1:
Alex Deucher6f34be52010-11-21 10:59:01 -05003864 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3865 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003866 queue_hotplug = true;
3867 DRM_DEBUG("IH: HPD2\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003868 }
3869 break;
3870 case 4:
Alex Deucher6f34be52010-11-21 10:59:01 -05003871 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3872 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003873 queue_hotplug = true;
3874 DRM_DEBUG("IH: HPD3\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003875 }
3876 break;
3877 case 5:
Alex Deucher6f34be52010-11-21 10:59:01 -05003878 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3879 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003880 queue_hotplug = true;
3881 DRM_DEBUG("IH: HPD4\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003882 }
3883 break;
3884 case 10:
Alex Deucher6f34be52010-11-21 10:59:01 -05003885 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3886 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003887 queue_hotplug = true;
3888 DRM_DEBUG("IH: HPD5\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003889 }
3890 break;
3891 case 12:
Alex Deucher6f34be52010-11-21 10:59:01 -05003892 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3893 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
Alex Deucherd4877cf2009-12-04 16:56:37 -05003894 queue_hotplug = true;
3895 DRM_DEBUG("IH: HPD6\n");
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003896 }
3897 break;
3898 default:
Alex Deucherb0425892010-01-11 19:47:38 -05003899 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deuchere0df1ac2009-12-04 15:12:21 -05003900 break;
3901 }
3902 break;
Alex Deucherf122c612012-03-30 08:59:57 -04003903 case 21: /* hdmi */
3904 switch (src_data) {
3905 case 4:
3906 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3907 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3908 queue_hdmi = true;
3909 DRM_DEBUG("IH: HDMI0\n");
3910 }
3911 break;
3912 case 5:
3913 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3914 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3915 queue_hdmi = true;
3916 DRM_DEBUG("IH: HDMI1\n");
3917 }
3918 break;
3919 default:
3920 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3921 break;
3922 }
Christian Koenigf2594932010-04-10 03:13:16 +02003923 break;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003924 case 176: /* CP_INT in ring buffer */
3925 case 177: /* CP_INT in IB1 */
3926 case 178: /* CP_INT in IB2 */
3927 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
Alex Deucher74652802011-08-25 13:39:48 -04003928 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003929 break;
3930 case 181: /* CP EOP event */
3931 DRM_DEBUG("IH: CP EOP\n");
Alex Deucher74652802011-08-25 13:39:48 -04003932 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003933 break;
Alex Deucher4d756582012-09-27 15:08:35 -04003934 case 224: /* DMA trap event */
3935 DRM_DEBUG("IH: DMA trap\n");
3936 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3937 break;
Alex Deucher2031f772010-04-22 12:52:11 -04003938 case 233: /* GUI IDLE */
Ilija Hadzic303c8052011-06-07 14:54:48 -04003939 DRM_DEBUG("IH: GUI idle\n");
Alex Deucher2031f772010-04-22 12:52:11 -04003940 break;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003941 default:
Alex Deucherb0425892010-01-11 19:47:38 -05003942 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003943 break;
3944 }
3945
3946 /* wptr/rptr are in bytes! */
Jerome Glisse0c452492010-01-15 14:44:37 +01003947 rptr += 16;
3948 rptr &= rdev->ih.ptr_mask;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003949 }
Alex Deucherd4877cf2009-12-04 16:56:37 -05003950 if (queue_hotplug)
Tejun Heo32c87fc2011-01-03 14:49:32 +01003951 schedule_work(&rdev->hotplug_work);
Alex Deucherf122c612012-03-30 08:59:57 -04003952 if (queue_hdmi)
3953 schedule_work(&rdev->audio_work);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003954 rdev->ih.rptr = rptr;
3955 WREG32(IH_RB_RPTR, rdev->ih.rptr);
Christian Koenigc20dc362012-05-16 21:45:24 +02003956 atomic_set(&rdev->ih.lock, 0);
3957
3958 /* make sure wptr hasn't changed while processing */
3959 wptr = r600_get_ih_wptr(rdev);
3960 if (wptr != rptr)
3961 goto restart_ih;
3962
Alex Deucherd8f60cf2009-12-01 13:43:46 -05003963 return IRQ_HANDLED;
3964}
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003965
3966/*
3967 * Debugfs info
3968 */
3969#if defined(CONFIG_DEBUG_FS)
3970
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003971static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3972{
3973 struct drm_info_node *node = (struct drm_info_node *) m->private;
3974 struct drm_device *dev = node->minor->dev;
3975 struct radeon_device *rdev = dev->dev_private;
3976
3977 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3978 DREG32_SYS(m, rdev, VM_L2_STATUS);
3979 return 0;
3980}
3981
3982static struct drm_info_list r600_mc_info_list[] = {
3983 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
Jerome Glisse3ce0a232009-09-08 10:10:24 +10003984};
3985#endif
3986
3987int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3988{
3989#if defined(CONFIG_DEBUG_FS)
3990 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3991#else
3992 return 0;
3993#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003994}
Jerome Glisse062b3892010-02-04 20:36:39 +01003995
3996/**
3997 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3998 * rdev: radeon device structure
3999 * bo: buffer object struct which userspace is waiting for idle
4000 *
4001 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4002 * through ring buffer, this leads to corruption in rendering, see
4003 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4004 * directly perform HDP flush by writing register through MMIO.
4005 */
4006void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4007{
Alex Deucher812d0462010-07-26 18:51:53 -04004008 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
Alex Deucherf3886f82010-12-08 10:05:34 -05004009 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4010 * This seems to cause problems on some AGP cards. Just use the old
4011 * method for them.
Alex Deucher812d0462010-07-26 18:51:53 -04004012 */
Alex Deuchere4884592010-09-27 10:57:10 -04004013 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
Alex Deucherf3886f82010-12-08 10:05:34 -05004014 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04004015 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
Alex Deucher812d0462010-07-26 18:51:53 -04004016 u32 tmp;
4017
4018 WREG32(HDP_DEBUG1, 0);
4019 tmp = readl((void __iomem *)ptr);
4020 } else
4021 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
Jerome Glisse062b3892010-02-04 20:36:39 +01004022}
Alex Deucher3313e3d2011-01-06 18:49:34 -05004023
4024void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4025{
4026 u32 link_width_cntl, mask, target_reg;
4027
4028 if (rdev->flags & RADEON_IS_IGP)
4029 return;
4030
4031 if (!(rdev->flags & RADEON_IS_PCIE))
4032 return;
4033
4034 /* x2 cards have a special sequence */
4035 if (ASIC_IS_X2(rdev))
4036 return;
4037
4038 /* FIXME wait for idle */
4039
4040 switch (lanes) {
4041 case 0:
4042 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4043 break;
4044 case 1:
4045 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4046 break;
4047 case 2:
4048 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4049 break;
4050 case 4:
4051 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4052 break;
4053 case 8:
4054 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4055 break;
4056 case 12:
4057 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4058 break;
4059 case 16:
4060 default:
4061 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4062 break;
4063 }
4064
4065 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4066
4067 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4068 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4069 return;
4070
4071 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4072 return;
4073
4074 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4075 RADEON_PCIE_LC_RECONFIG_NOW |
4076 R600_PCIE_LC_RENEGOTIATE_EN |
4077 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4078 link_width_cntl |= mask;
4079
4080 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4081
4082 /* some northbridges can renegotiate the link rather than requiring
4083 * a complete re-config.
4084 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4085 */
4086 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4087 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4088 else
4089 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4090
4091 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4092 RADEON_PCIE_LC_RECONFIG_NOW));
4093
4094 if (rdev->family >= CHIP_RV770)
4095 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4096 else
4097 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4098
4099 /* wait for lane set to complete */
4100 link_width_cntl = RREG32(target_reg);
4101 while (link_width_cntl == 0xffffffff)
4102 link_width_cntl = RREG32(target_reg);
4103
4104}
4105
4106int r600_get_pcie_lanes(struct radeon_device *rdev)
4107{
4108 u32 link_width_cntl;
4109
4110 if (rdev->flags & RADEON_IS_IGP)
4111 return 0;
4112
4113 if (!(rdev->flags & RADEON_IS_PCIE))
4114 return 0;
4115
4116 /* x2 cards have a special sequence */
4117 if (ASIC_IS_X2(rdev))
4118 return 0;
4119
4120 /* FIXME wait for idle */
4121
4122 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4123
4124 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4125 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4126 return 0;
4127 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4128 return 1;
4129 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4130 return 2;
4131 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4132 return 4;
4133 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4134 return 8;
4135 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4136 default:
4137 return 16;
4138 }
4139}
4140
Alex Deucher9e46a482011-01-06 18:49:35 -05004141static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4142{
4143 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4144 u16 link_cntl2;
Dave Airlie197bbb32012-06-27 08:35:54 +01004145 u32 mask;
4146 int ret;
Alex Deucher9e46a482011-01-06 18:49:35 -05004147
Alex Deucherd42dd572011-01-12 20:05:11 -05004148 if (radeon_pcie_gen2 == 0)
4149 return;
4150
Alex Deucher9e46a482011-01-06 18:49:35 -05004151 if (rdev->flags & RADEON_IS_IGP)
4152 return;
4153
4154 if (!(rdev->flags & RADEON_IS_PCIE))
4155 return;
4156
4157 /* x2 cards have a special sequence */
4158 if (ASIC_IS_X2(rdev))
4159 return;
4160
4161 /* only RV6xx+ chips are supported */
4162 if (rdev->family <= CHIP_R600)
4163 return;
4164
Dave Airlie197bbb32012-06-27 08:35:54 +01004165 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4166 if (ret != 0)
4167 return;
4168
4169 if (!(mask & DRM_PCIE_SPEED_50))
4170 return;
4171
Alex Deucher3691fee2012-10-08 17:46:27 -04004172 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4173 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4174 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4175 return;
4176 }
4177
Dave Airlie197bbb32012-06-27 08:35:54 +01004178 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4179
Alex Deucher9e46a482011-01-06 18:49:35 -05004180 /* 55 nm r6xx asics */
4181 if ((rdev->family == CHIP_RV670) ||
4182 (rdev->family == CHIP_RV620) ||
4183 (rdev->family == CHIP_RV635)) {
4184 /* advertise upconfig capability */
4185 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4186 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4187 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4188 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4189 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4190 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4191 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4192 LC_RECONFIG_ARC_MISSING_ESCAPE);
4193 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4194 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4195 } else {
4196 link_width_cntl |= LC_UPCONFIGURE_DIS;
4197 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4198 }
4199 }
4200
4201 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4202 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4203 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4204
4205 /* 55 nm r6xx asics */
4206 if ((rdev->family == CHIP_RV670) ||
4207 (rdev->family == CHIP_RV620) ||
4208 (rdev->family == CHIP_RV635)) {
4209 WREG32(MM_CFGREGS_CNTL, 0x8);
4210 link_cntl2 = RREG32(0x4088);
4211 WREG32(MM_CFGREGS_CNTL, 0);
4212 /* not supported yet */
4213 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4214 return;
4215 }
4216
4217 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4218 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4219 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4220 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4221 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4222 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4223
4224 tmp = RREG32(0x541c);
4225 WREG32(0x541c, tmp | 0x8);
4226 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4227 link_cntl2 = RREG16(0x4088);
4228 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4229 link_cntl2 |= 0x2;
4230 WREG16(0x4088, link_cntl2);
4231 WREG32(MM_CFGREGS_CNTL, 0);
4232
4233 if ((rdev->family == CHIP_RV670) ||
4234 (rdev->family == CHIP_RV620) ||
4235 (rdev->family == CHIP_RV635)) {
4236 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4237 training_cntl &= ~LC_POINT_7_PLUS_EN;
4238 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4239 } else {
4240 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4241 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4242 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4243 }
4244
4245 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4246 speed_cntl |= LC_GEN2_EN_STRAP;
4247 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4248
4249 } else {
4250 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4251 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4252 if (1)
4253 link_width_cntl |= LC_UPCONFIGURE_DIS;
4254 else
4255 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4256 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4257 }
4258}
Marek Olšák6759a0a2012-08-09 16:34:17 +02004259
4260/**
4261 * r600_get_gpu_clock - return GPU clock counter snapshot
4262 *
4263 * @rdev: radeon_device pointer
4264 *
4265 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4266 * Returns the 64 bit clock counter snapshot.
4267 */
4268uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4269{
4270 uint64_t clock;
4271
4272 mutex_lock(&rdev->gpu_clock_mutex);
4273 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4274 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4275 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4276 mutex_unlock(&rdev->gpu_clock_mutex);
4277 return clock;
4278}