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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
Scott Wood22d168c2011-03-24 16:43:54 -05009 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Paul Mackerras14cf11a2005-09-26 16:04:21 +100010 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16#undef DEBUG
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +110017#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
Paul Mackerras14cf11a2005-09-26 16:04:21 +100020
Paul Mackerras14cf11a2005-09-26 16:04:21 +100021#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/bootmem.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +020031#include <linux/syscore_ops.h>
Christian Dietrich76462232011-06-04 05:36:54 +000032#include <linux/ratelimit.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100033
34#include <asm/ptrace.h>
35#include <asm/signal.h>
36#include <asm/io.h>
37#include <asm/pgtable.h>
38#include <asm/irq.h>
39#include <asm/machdep.h>
40#include <asm/mpic.h>
41#include <asm/smp.h>
42
Michael Ellermana7de7c72007-05-08 12:58:36 +100043#include "mpic.h"
44
Paul Mackerras14cf11a2005-09-26 16:04:21 +100045#ifdef DEBUG
46#define DBG(fmt...) printk(fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51static struct mpic *mpics;
52static struct mpic *mpic_primary;
Thomas Gleixner203041a2010-02-18 02:23:18 +000053static DEFINE_RAW_SPINLOCK(mpic_lock);
Paul Mackerras14cf11a2005-09-26 16:04:21 +100054
Paul Mackerrasc0c0d992005-10-01 13:49:08 +100055#ifdef CONFIG_PPC32 /* XXX for now */
Andy Whitcrofte40c7f02005-11-29 19:25:54 +000056#ifdef CONFIG_IRQ_ALL_CPUS
57#define distribute_irqs (1)
58#else
59#define distribute_irqs (0)
60#endif
Paul Mackerrasc0c0d992005-10-01 13:49:08 +100061#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100062
Zang Roy-r6191172335932006-08-25 14:16:30 +100063#ifdef CONFIG_MPIC_WEIRD
64static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
66 MPIC_GREG_BASE,
67 MPIC_GREG_FEATURE_0,
68 MPIC_GREG_GLOBAL_CONF_0,
69 MPIC_GREG_VENDOR_ID,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
71 MPIC_GREG_IPI_STRIDE,
72 MPIC_GREG_SPURIOUS,
73 MPIC_GREG_TIMER_FREQ,
74
75 MPIC_TIMER_BASE,
76 MPIC_TIMER_STRIDE,
77 MPIC_TIMER_CURRENT_CNT,
78 MPIC_TIMER_BASE_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
81
82 MPIC_CPU_BASE,
83 MPIC_CPU_STRIDE,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
87 MPIC_CPU_WHOAMI,
88 MPIC_CPU_INTACK,
89 MPIC_CPU_EOI,
Olof Johanssonf3653552007-12-20 13:11:18 -060090 MPIC_CPU_MCACK,
Zang Roy-r6191172335932006-08-25 14:16:30 +100091
92 MPIC_IRQ_BASE,
93 MPIC_IRQ_STRIDE,
94 MPIC_IRQ_VECTOR_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
102 MPIC_IRQ_DESTINATION
103 },
104 [1] = { /* Tsi108/109 PIC */
105 TSI108_GREG_BASE,
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
113
114 TSI108_TIMER_BASE,
115 TSI108_TIMER_STRIDE,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
120
121 TSI108_CPU_BASE,
122 TSI108_CPU_STRIDE,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
126 TSI108_CPU_WHOAMI,
127 TSI108_CPU_INTACK,
128 TSI108_CPU_EOI,
Olof Johanssonf3653552007-12-20 13:11:18 -0600129 TSI108_CPU_MCACK,
Zang Roy-r6191172335932006-08-25 14:16:30 +1000130
131 TSI108_IRQ_BASE,
132 TSI108_IRQ_STRIDE,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
142 },
143};
144
145#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
146
147#else /* CONFIG_MPIC_WEIRD */
148
149#define MPIC_INFO(name) MPIC_##name
150
151#endif /* CONFIG_MPIC_WEIRD */
152
Meador Inged6a26392011-03-14 10:01:07 +0000153static inline unsigned int mpic_processor_id(struct mpic *mpic)
154{
155 unsigned int cpu = 0;
156
Kyle Moffettbe8bec52011-12-02 06:28:03 +0000157 if (!(mpic->flags & MPIC_SECONDARY))
Meador Inged6a26392011-03-14 10:01:07 +0000158 cpu = hard_smp_processor_id();
159
160 return cpu;
161}
162
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000163/*
164 * Register accessor functions
165 */
166
167
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100168static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
170 unsigned int reg)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000171{
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100172 switch(type) {
173#ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
Michael Ellerman83f34df2007-10-15 19:34:36 +1000175 return dcr_read(rb->dhost, reg);
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100176#endif
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
180 default:
181 return in_le32(rb->base + (reg >> 2));
182 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000183}
184
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100185static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000188{
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100189 switch(type) {
190#ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
Johannes Bergd9d10632008-02-21 20:39:01 +1100192 dcr_write(rb->dhost, reg, value);
193 break;
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100194#endif
195 case mpic_access_mmio_be:
Johannes Bergd9d10632008-02-21 20:39:01 +1100196 out_be32(rb->base + (reg >> 2), value);
197 break;
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100198 case mpic_access_mmio_le:
199 default:
Johannes Bergd9d10632008-02-21 20:39:01 +1100200 out_le32(rb->base + (reg >> 2), value);
201 break;
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100202 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000203}
204
205static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
206{
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100207 enum mpic_reg_type type = mpic->reg_type;
Zang Roy-r6191172335932006-08-25 14:16:30 +1000208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000210
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000214}
215
216static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
217{
Zang Roy-r6191172335932006-08-25 14:16:30 +1000218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000220
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000222}
223
Scott Woodea941872011-03-24 16:43:55 -0500224static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
225{
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
228
229 if (tm >= 4)
230 offset += 0x1000 / 4;
231
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
233}
234
235static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
236{
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
239
240 if (tm >= 4)
241 offset += 0x1000 / 4;
242
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
244}
245
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000246static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
247{
Meador Inged6a26392011-03-14 10:01:07 +0000248 unsigned int cpu = mpic_processor_id(mpic);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000249
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000251}
252
253static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
254{
Meador Inged6a26392011-03-14 10:01:07 +0000255 unsigned int cpu = mpic_processor_id(mpic);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000256
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000258}
259
260static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
261{
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
Michael Ellerman11a6b292009-07-05 16:08:52 +0000264 unsigned int val;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000265
Michael Ellerman11a6b292009-07-05 16:08:52 +0000266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
Olof Johansson0d72ba92007-09-08 05:13:19 +1000268#ifdef CONFIG_MPIC_BROKEN_REGREAD
269 if (reg == 0)
Michael Ellerman11a6b292009-07-05 16:08:52 +0000270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
Olof Johansson0d72ba92007-09-08 05:13:19 +1000272#endif
Michael Ellerman11a6b292009-07-05 16:08:52 +0000273 return val;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000274}
275
276static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
278{
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
281
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
Zang Roy-r6191172335932006-08-25 14:16:30 +1000283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
Olof Johansson0d72ba92007-09-08 05:13:19 +1000284
285#ifdef CONFIG_MPIC_BROKEN_REGREAD
286 if (reg == 0)
Michael Ellerman11a6b292009-07-05 16:08:52 +0000287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
Olof Johansson0d72ba92007-09-08 05:13:19 +1000289#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000290}
291
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100292#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000294#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
Scott Woodea941872011-03-24 16:43:55 -0500296#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000298#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
302
303
304/*
305 * Low level utility functions
306 */
307
308
Becky Brucec51a3fdc2008-01-14 20:56:18 -0600309static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100310 struct mpic_reg_bank *rb, unsigned int offset,
311 unsigned int size)
312{
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
315}
316
317#ifdef CONFIG_PPC_DCR
Kyle Moffettc51242e2011-12-02 06:28:06 +0000318static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100319 unsigned int offset, unsigned int size)
320{
Kyle Moffettc51242e2011-12-02 06:28:06 +0000321 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
Kyle Moffette62b7602011-12-02 06:28:04 +0000322 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100323 BUG_ON(!DCR_MAP_OK(rb->dhost));
324}
325
Kyle Moffettc51242e2011-12-02 06:28:06 +0000326static inline void mpic_map(struct mpic *mpic,
Benjamin Herrenschmidt5a2642f2009-06-22 16:47:59 +0000327 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
328 unsigned int offset, unsigned int size)
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100329{
330 if (mpic->flags & MPIC_USES_DCR)
Kyle Moffettc51242e2011-12-02 06:28:06 +0000331 _mpic_map_dcr(mpic, rb, offset, size);
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100332 else
333 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
334}
335#else /* CONFIG_PPC_DCR */
Kyle Moffettc51242e2011-12-02 06:28:06 +0000336#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +1100337#endif /* !CONFIG_PPC_DCR */
338
339
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000340
341/* Check if we have one of those nice broken MPICs with a flipped endian on
342 * reads from IPI registers
343 */
344static void __init mpic_test_broken_ipi(struct mpic *mpic)
345{
346 u32 r;
347
Zang Roy-r6191172335932006-08-25 14:16:30 +1000348 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
349 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000350
351 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
352 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
353 mpic->flags |= MPIC_BROKEN_IPI;
354 }
355}
356
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000357#ifdef CONFIG_MPIC_U3_HT_IRQS
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000358
359/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
360 * to force the edge setting on the MPIC and do the ack workaround.
361 */
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100362static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000363{
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100364 if (source >= 128 || !mpic->fixups)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000365 return 0;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100366 return mpic->fixups[source].base != NULL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000367}
368
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100369
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100370static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000371{
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100372 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000373
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100374 if (fixup->applebase) {
375 unsigned int soff = (fixup->index >> 3) & ~3;
376 unsigned int mask = 1U << (fixup->index & 0x1f);
377 writel(mask, fixup->applebase + soff);
378 } else {
Thomas Gleixner203041a2010-02-18 02:23:18 +0000379 raw_spin_lock(&mpic->fixup_lock);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100380 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
381 writel(fixup->data, fixup->base + 4);
Thomas Gleixner203041a2010-02-18 02:23:18 +0000382 raw_spin_unlock(&mpic->fixup_lock);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100383 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000384}
385
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100386static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100387 bool level)
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100388{
389 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
390 unsigned long flags;
391 u32 tmp;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000392
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100393 if (fixup->base == NULL)
394 return;
395
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100396 DBG("startup_ht_interrupt(0x%x) index: %d\n",
397 source, fixup->index);
Thomas Gleixner203041a2010-02-18 02:23:18 +0000398 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100399 /* Enable and configure */
400 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
401 tmp = readl(fixup->base + 4);
402 tmp &= ~(0x23U);
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100403 if (level)
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100404 tmp |= 0x22;
405 writel(tmp, fixup->base + 4);
Thomas Gleixner203041a2010-02-18 02:23:18 +0000406 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
Johannes Berg3669e932007-05-02 16:33:41 +1000407
408#ifdef CONFIG_PM
409 /* use the lowest bit inverted to the actual HW,
410 * set if this fixup was enabled, clear otherwise */
411 mpic->save_data[source].fixup_data = tmp | 1;
412#endif
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100413}
414
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100415static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100416{
417 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
418 unsigned long flags;
419 u32 tmp;
420
421 if (fixup->base == NULL)
422 return;
423
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100424 DBG("shutdown_ht_interrupt(0x%x)\n", source);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100425
426 /* Disable */
Thomas Gleixner203041a2010-02-18 02:23:18 +0000427 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100428 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
429 tmp = readl(fixup->base + 4);
Segher Boessenkool72b13812006-02-17 11:25:42 +0100430 tmp |= 1;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100431 writel(tmp, fixup->base + 4);
Thomas Gleixner203041a2010-02-18 02:23:18 +0000432 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
Johannes Berg3669e932007-05-02 16:33:41 +1000433
434#ifdef CONFIG_PM
435 /* use the lowest bit inverted to the actual HW,
436 * set if this fixup was enabled, clear otherwise */
437 mpic->save_data[source].fixup_data = tmp & ~1;
438#endif
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100439}
440
Michael Ellerman812fd1f2007-05-08 12:58:36 +1000441#ifdef CONFIG_PCI_MSI
442static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
443 unsigned int devfn)
444{
445 u8 __iomem *base;
446 u8 pos, flags;
447 u64 addr = 0;
448
449 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
450 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
451 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
452 if (id == PCI_CAP_ID_HT) {
453 id = readb(devbase + pos + 3);
454 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
455 break;
456 }
457 }
458
459 if (pos == 0)
460 return;
461
462 base = devbase + pos;
463
464 flags = readb(base + HT_MSI_FLAGS);
465 if (!(flags & HT_MSI_FLAGS_FIXED)) {
466 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
467 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
468 }
469
Ingo Molnarfe333322009-01-06 14:26:03 +0000470 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
Michael Ellerman812fd1f2007-05-08 12:58:36 +1000471 PCI_SLOT(devfn), PCI_FUNC(devfn),
472 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
473
474 if (!(flags & HT_MSI_FLAGS_ENABLE))
475 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
476}
477#else
478static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
479 unsigned int devfn)
480{
481 return;
482}
483#endif
484
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100485static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
486 unsigned int devfn, u32 vdid)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000487{
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100488 int i, irq, n;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100489 u8 __iomem *base;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000490 u32 tmp;
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100491 u8 pos;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000492
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100493 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
494 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
495 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
Brice Goglin46ff3462006-08-31 01:55:24 -0400496 if (id == PCI_CAP_ID_HT) {
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100497 id = readb(devbase + pos + 3);
Michael Ellermanbeb7cc82006-11-22 18:26:22 +1100498 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100499 break;
500 }
501 }
502 if (pos == 0)
503 return;
504
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100505 base = devbase + pos;
506 writeb(0x01, base + 2);
507 n = (readl(base + 4) >> 16) & 0xff;
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100508
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100509 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
510 " has %d irqs\n",
511 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100512
513 for (i = 0; i <= n; i++) {
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100514 writeb(0x10 + 2 * i, base + 2);
515 tmp = readl(base + 4);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000516 irq = (tmp >> 16) & 0xff;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100517 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
518 /* mask it , will be unmasked later */
519 tmp |= 0x1;
520 writel(tmp, base + 4);
521 mpic->fixups[irq].index = i;
522 mpic->fixups[irq].base = base;
523 /* Apple HT PIC has a non-standard way of doing EOIs */
524 if ((vdid & 0xffff) == 0x106b)
525 mpic->fixups[irq].applebase = devbase + 0x60;
526 else
527 mpic->fixups[irq].applebase = NULL;
528 writeb(0x11 + 2 * i, base + 2);
529 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000530 }
531}
532
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000533
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100534static void __init mpic_scan_ht_pics(struct mpic *mpic)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000535{
536 unsigned int devfn;
537 u8 __iomem *cfgspace;
538
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100539 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000540
541 /* Allocate fixups array */
Anton Vorontsovea960252009-07-01 10:59:57 +0000542 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000543 BUG_ON(mpic->fixups == NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000544
545 /* Init spinlock */
Thomas Gleixner203041a2010-02-18 02:23:18 +0000546 raw_spin_lock_init(&mpic->fixup_lock);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000547
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100548 /* Map U3 config space. We assume all IO-APICs are on the primary bus
549 * so we only need to map 64kB.
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000550 */
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100551 cfgspace = ioremap(0xf2000000, 0x10000);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000552 BUG_ON(cfgspace == NULL);
553
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100554 /* Now we scan all slots. We do a very quick scan, we read the header
555 * type, vendor ID and device ID only, that's plenty enough
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000556 */
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100557 for (devfn = 0; devfn < 0x100; devfn++) {
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000558 u8 __iomem *devbase = cfgspace + (devfn << 8);
559 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
560 u32 l = readl(devbase + PCI_VENDOR_ID);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100561 u16 s;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000562
563 DBG("devfn %x, l: %x\n", devfn, l);
564
565 /* If no device, skip */
566 if (l == 0xffffffff || l == 0x00000000 ||
567 l == 0x0000ffff || l == 0xffff0000)
568 goto next;
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100569 /* Check if is supports capability lists */
570 s = readw(devbase + PCI_STATUS);
571 if (!(s & PCI_STATUS_CAP_LIST))
572 goto next;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000573
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100574 mpic_scan_ht_pic(mpic, devbase, devfn, l);
Michael Ellerman812fd1f2007-05-08 12:58:36 +1000575 mpic_scan_ht_msi(mpic, devbase, devfn);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000576
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000577 next:
578 /* next device, if function 0 */
Segher Boessenkoolc4b22f22005-12-13 18:04:29 +1100579 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000580 devfn += 7;
581 }
582}
583
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000584#else /* CONFIG_MPIC_U3_HT_IRQS */
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700585
586static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
587{
588 return 0;
589}
590
591static void __init mpic_scan_ht_pics(struct mpic *mpic)
592{
593}
594
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000595#endif /* CONFIG_MPIC_U3_HT_IRQS */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000596
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000597/* Find an mpic associated with a given linux interrupt */
Tony Breedsd69a78d2009-04-07 18:26:54 +0000598static struct mpic *mpic_find(unsigned int irq)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000599{
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000600 if (irq < NUM_ISA_INTERRUPTS)
601 return NULL;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000602
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100603 return irq_get_chip_data(irq);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000604}
605
Tony Breedsd69a78d2009-04-07 18:26:54 +0000606/* Determine if the linux irq is an IPI */
607static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
608{
Grant Likely476eb492011-05-04 15:02:15 +1000609 unsigned int src = virq_to_hw(irq);
Tony Breedsd69a78d2009-04-07 18:26:54 +0000610
611 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
612}
613
Scott Woodea941872011-03-24 16:43:55 -0500614/* Determine if the linux irq is a timer */
615static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
616{
617 unsigned int src = virq_to_hw(irq);
618
619 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
620}
Tony Breedsd69a78d2009-04-07 18:26:54 +0000621
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000622/* Convert a cpu mask from logical to physical cpu numbers. */
623static inline u32 mpic_physmask(u32 cpumask)
624{
625 int i;
626 u32 mask = 0;
627
Milton Millerebc04212011-05-10 19:28:59 +0000628 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000629 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
630 return mask;
631}
632
633#ifdef CONFIG_SMP
634/* Get the mpic structure from the IPI number */
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000635static inline struct mpic * mpic_from_ipi(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000636{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000637 return irq_data_get_irq_chip_data(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000638}
639#endif
640
641/* Get the mpic structure from the irq number */
642static inline struct mpic * mpic_from_irq(unsigned int irq)
643{
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100644 return irq_get_chip_data(irq);
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000645}
646
647/* Get the mpic structure from the irq data */
648static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
649{
650 return irq_data_get_irq_chip_data(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000651}
652
653/* Send an EOI */
654static inline void mpic_eoi(struct mpic *mpic)
655{
Zang Roy-r6191172335932006-08-25 14:16:30 +1000656 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
657 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000658}
659
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000660/*
661 * Linux descriptor level callbacks
662 */
663
664
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000665void mpic_unmask_irq(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000666{
667 unsigned int loops = 100000;
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000668 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000669 unsigned int src = irqd_to_hwirq(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000670
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000672
Zang Roy-r6191172335932006-08-25 14:16:30 +1000673 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
674 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
Benjamin Herrenschmidte5356642005-11-18 17:18:15 +1100675 ~MPIC_VECPRI_MASK);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000676 /* make sure mask gets to controller before we return to user */
677 do {
678 if (!loops--) {
Scott Wood8bfc5e32011-01-17 12:10:41 +0000679 printk(KERN_ERR "%s: timeout on hwirq %u\n",
680 __func__, src);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000681 break;
682 }
Zang Roy-r6191172335932006-08-25 14:16:30 +1000683 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100684}
685
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000686void mpic_mask_irq(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000687{
688 unsigned int loops = 100000;
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000689 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000690 unsigned int src = irqd_to_hwirq(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000691
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000693
Zang Roy-r6191172335932006-08-25 14:16:30 +1000694 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
695 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
Benjamin Herrenschmidte5356642005-11-18 17:18:15 +1100696 MPIC_VECPRI_MASK);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000697
698 /* make sure mask gets to controller before we return to user */
699 do {
700 if (!loops--) {
Scott Wood8bfc5e32011-01-17 12:10:41 +0000701 printk(KERN_ERR "%s: timeout on hwirq %u\n",
702 __func__, src);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000703 break;
704 }
Zang Roy-r6191172335932006-08-25 14:16:30 +1000705 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000706}
707
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000708void mpic_end_irq(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000709{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000710 struct mpic *mpic = mpic_from_irq_data(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000711
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100712#ifdef DEBUG_IRQ
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000713 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +1100714#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000715 /* We always EOI on end_irq() even for edge interrupts since that
716 * should only lower the priority, the MPIC should have properly
717 * latched another edge interrupt coming in anyway
718 */
719
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000720 mpic_eoi(mpic);
721}
722
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000723#ifdef CONFIG_MPIC_U3_HT_IRQS
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000724
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000725static void mpic_unmask_ht_irq(struct irq_data *d)
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000726{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000727 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000728 unsigned int src = irqd_to_hwirq(d);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000729
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000730 mpic_unmask_irq(d);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000731
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100732 if (irqd_is_level_type(d))
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000733 mpic_ht_end_irq(mpic, src);
734}
735
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000736static unsigned int mpic_startup_ht_irq(struct irq_data *d)
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000737{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000738 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000739 unsigned int src = irqd_to_hwirq(d);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000740
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000741 mpic_unmask_irq(d);
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100742 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000743
744 return 0;
745}
746
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000747static void mpic_shutdown_ht_irq(struct irq_data *d)
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000748{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000749 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000750 unsigned int src = irqd_to_hwirq(d);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000751
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100752 mpic_shutdown_ht_interrupt(mpic, src);
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000753 mpic_mask_irq(d);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000754}
755
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000756static void mpic_end_ht_irq(struct irq_data *d)
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000757{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000758 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000759 unsigned int src = irqd_to_hwirq(d);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000760
761#ifdef DEBUG_IRQ
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000762 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000763#endif
764 /* We always EOI on end_irq() even for edge interrupts since that
765 * should only lower the priority, the MPIC should have properly
766 * latched another edge interrupt coming in anyway
767 */
768
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100769 if (irqd_is_level_type(d))
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000770 mpic_ht_end_irq(mpic, src);
771 mpic_eoi(mpic);
772}
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000773#endif /* !CONFIG_MPIC_U3_HT_IRQS */
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000774
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000775#ifdef CONFIG_SMP
776
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000777static void mpic_unmask_ipi(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000778{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000779 struct mpic *mpic = mpic_from_ipi(d);
Grant Likely476eb492011-05-04 15:02:15 +1000780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000781
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000783 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
784}
785
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000786static void mpic_mask_ipi(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000787{
788 /* NEVER disable an IPI... that's just plain wrong! */
789}
790
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000791static void mpic_end_ipi(struct irq_data *d)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000792{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000793 struct mpic *mpic = mpic_from_ipi(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000794
795 /*
796 * IPIs are marked IRQ_PER_CPU. This has the side effect of
797 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
798 * applying to them. We EOI them late to avoid re-entering.
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000799 */
800 mpic_eoi(mpic);
801}
802
803#endif /* CONFIG_SMP */
804
Scott Woodea941872011-03-24 16:43:55 -0500805static void mpic_unmask_tm(struct irq_data *d)
806{
807 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
809
Dmitry Eremin-Solenikov77ef4892011-05-30 01:56:09 +0000810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
Scott Woodea941872011-03-24 16:43:55 -0500811 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
812 mpic_tm_read(src);
813}
814
815static void mpic_mask_tm(struct irq_data *d)
816{
817 struct mpic *mpic = mpic_from_irq_data(d);
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
819
820 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
821 mpic_tm_read(src);
822}
823
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000824int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
825 bool force)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000826{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000827 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000828 unsigned int src = irqd_to_hwirq(d);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000829
Kumar Gala3c10c9c2008-10-28 18:01:39 +0000830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
Yang Li38e13132009-12-16 20:18:11 +0000831 int cpuid = irq_choose_cpu(cpumask);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000832
Kumar Gala3c10c9c2008-10-28 18:01:39 +0000833 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
834 } else {
Milton Miller2a116f32011-05-10 19:29:02 +0000835 u32 mask = cpumask_bits(cpumask)[0];
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000836
Milton Miller2a116f32011-05-10 19:29:02 +0000837 mask &= cpumask_bits(cpu_online_mask)[0];
Kumar Gala3c10c9c2008-10-28 18:01:39 +0000838
839 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
Milton Miller2a116f32011-05-10 19:29:02 +0000840 mpic_physmask(mask));
Kumar Gala3c10c9c2008-10-28 18:01:39 +0000841 }
Yinghai Lud5dedd42009-04-27 17:59:21 -0700842
843 return 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000844}
845
Zang Roy-r6191172335932006-08-25 14:16:30 +1000846static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000847{
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000848 /* Now convert sense value */
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700849 switch(type & IRQ_TYPE_SENSE_MASK) {
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000850 case IRQ_TYPE_EDGE_RISING:
Zang Roy-r6191172335932006-08-25 14:16:30 +1000851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000853 case IRQ_TYPE_EDGE_FALLING:
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700854 case IRQ_TYPE_EDGE_BOTH:
Zang Roy-r6191172335932006-08-25 14:16:30 +1000855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000857 case IRQ_TYPE_LEVEL_HIGH:
Zang Roy-r6191172335932006-08-25 14:16:30 +1000858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000860 case IRQ_TYPE_LEVEL_LOW:
861 default:
Zang Roy-r6191172335932006-08-25 14:16:30 +1000862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000864 }
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700865}
866
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000867int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700868{
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000869 struct mpic *mpic = mpic_from_irq_data(d);
Grant Likely476eb492011-05-04 15:02:15 +1000870 unsigned int src = irqd_to_hwirq(d);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700871 unsigned int vecpri, vold, vnew;
872
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -0700873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000874 mpic, d->irq, src, flow_type);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700875
Kyle Moffett50196092011-12-22 10:19:12 +0000876 if (src >= mpic->num_sources)
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700877 return -EINVAL;
878
879 if (flow_type == IRQ_TYPE_NONE)
880 if (mpic->senses && src < mpic->senses_count)
881 flow_type = mpic->senses[src];
882 if (flow_type == IRQ_TYPE_NONE)
883 flow_type = IRQ_TYPE_LEVEL_LOW;
884
Thomas Gleixner24a3f2e2011-03-25 16:20:15 +0100885 irqd_set_trigger_type(d, flow_type);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700886
887 if (mpic_is_ht_interrupt(mpic, src))
888 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
889 MPIC_VECPRI_SENSE_EDGE;
890 else
Zang Roy-r6191172335932006-08-25 14:16:30 +1000891 vecpri = mpic_type_to_vecpri(mpic, flow_type);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700892
Zang Roy-r6191172335932006-08-25 14:16:30 +1000893 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
894 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
895 MPIC_INFO(VECPRI_SENSE_MASK));
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700896 vnew |= vecpri;
897 if (vold != vnew)
Zang Roy-r6191172335932006-08-25 14:16:30 +1000898 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700899
Justin P. Mattocke075cd72011-11-21 06:43:26 +0000900 return IRQ_SET_MASK_OK_NOCOPY;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000901}
902
Olof Johansson38958dd2007-12-12 17:44:46 +1100903void mpic_set_vector(unsigned int virq, unsigned int vector)
904{
905 struct mpic *mpic = mpic_from_irq(virq);
Grant Likely476eb492011-05-04 15:02:15 +1000906 unsigned int src = virq_to_hw(virq);
Olof Johansson38958dd2007-12-12 17:44:46 +1100907 unsigned int vecpri;
908
909 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
910 mpic, virq, src, vector);
911
Kyle Moffett50196092011-12-22 10:19:12 +0000912 if (src >= mpic->num_sources)
Olof Johansson38958dd2007-12-12 17:44:46 +1100913 return;
914
915 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
916 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
917 vecpri |= vector;
918 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
919}
920
Meador Ingedfec2202011-03-14 10:01:06 +0000921void mpic_set_destination(unsigned int virq, unsigned int cpuid)
922{
923 struct mpic *mpic = mpic_from_irq(virq);
Grant Likely476eb492011-05-04 15:02:15 +1000924 unsigned int src = virq_to_hw(virq);
Meador Ingedfec2202011-03-14 10:01:06 +0000925
926 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
927 mpic, virq, src, cpuid);
928
Kyle Moffett50196092011-12-22 10:19:12 +0000929 if (src >= mpic->num_sources)
Meador Ingedfec2202011-03-14 10:01:06 +0000930 return;
931
932 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
933}
934
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000935static struct irq_chip mpic_irq_chip = {
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000936 .irq_mask = mpic_mask_irq,
937 .irq_unmask = mpic_unmask_irq,
938 .irq_eoi = mpic_end_irq,
939 .irq_set_type = mpic_set_irq_type,
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000940};
941
942#ifdef CONFIG_SMP
943static struct irq_chip mpic_ipi_chip = {
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000944 .irq_mask = mpic_mask_ipi,
945 .irq_unmask = mpic_unmask_ipi,
946 .irq_eoi = mpic_end_ipi,
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000947};
948#endif /* CONFIG_SMP */
949
Scott Woodea941872011-03-24 16:43:55 -0500950static struct irq_chip mpic_tm_chip = {
951 .irq_mask = mpic_mask_tm,
952 .irq_unmask = mpic_unmask_tm,
953 .irq_eoi = mpic_end_irq,
954};
955
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000956#ifdef CONFIG_MPIC_U3_HT_IRQS
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000957static struct irq_chip mpic_irq_ht_chip = {
Lennert Buytenhek835c05532011-03-08 22:26:43 +0000958 .irq_startup = mpic_startup_ht_irq,
959 .irq_shutdown = mpic_shutdown_ht_irq,
960 .irq_mask = mpic_mask_irq,
961 .irq_unmask = mpic_unmask_ht_irq,
962 .irq_eoi = mpic_end_ht_irq,
963 .irq_set_type = mpic_set_irq_type,
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000964};
Michael Ellerman6cfef5b2007-04-23 18:47:08 +1000965#endif /* CONFIG_MPIC_U3_HT_IRQS */
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +1000966
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000967
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000968static int mpic_host_match(struct irq_host *h, struct device_node *node)
969{
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000970 /* Exact match, unless mpic node is NULL */
Michael Ellerman52964f82007-08-28 18:47:54 +1000971 return h->of_node == NULL || h->of_node == node;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000972}
973
974static int mpic_host_map(struct irq_host *h, unsigned int virq,
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700975 irq_hw_number_t hw)
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000976{
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000977 struct mpic *mpic = h->host_data;
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -0700978 struct irq_chip *chip;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000979
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -0700980 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000981
Olof Johansson7df24572007-01-28 23:33:18 -0600982 if (hw == mpic->spurious_vec)
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000983 return -EINVAL;
Benjamin Herrenschmidt7fd72182007-07-21 09:55:21 +1000984 if (mpic->protected && test_bit(hw, mpic->protected))
985 return -EINVAL;
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -0700986
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000987#ifdef CONFIG_SMP
Olof Johansson7df24572007-01-28 23:33:18 -0600988 else if (hw >= mpic->ipi_vecs[0]) {
Kyle Moffettbe8bec52011-12-02 06:28:03 +0000989 WARN_ON(mpic->flags & MPIC_SECONDARY);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000990
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -0700991 DBG("mpic: mapping as IPI\n");
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100992 irq_set_chip_data(virq, mpic);
993 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000994 handle_percpu_irq);
995 return 0;
996 }
997#endif /* CONFIG_SMP */
998
Scott Woodea941872011-03-24 16:43:55 -0500999 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
Kyle Moffettbe8bec52011-12-02 06:28:03 +00001000 WARN_ON(mpic->flags & MPIC_SECONDARY);
Scott Woodea941872011-03-24 16:43:55 -05001001
1002 DBG("mpic: mapping as timer\n");
1003 irq_set_chip_data(virq, mpic);
1004 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1005 handle_fasteoi_irq);
1006 return 0;
1007 }
1008
Kyle Moffett50196092011-12-22 10:19:12 +00001009 if (hw >= mpic->num_sources)
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001010 return -EINVAL;
1011
Michael Ellermana7de7c72007-05-08 12:58:36 +10001012 mpic_msi_reserve_hwirq(mpic, hw);
1013
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -07001014 /* Default chip */
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001015 chip = &mpic->hc_irq;
1016
Michael Ellerman6cfef5b2007-04-23 18:47:08 +10001017#ifdef CONFIG_MPIC_U3_HT_IRQS
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001018 /* Check for HT interrupts, override vecpri */
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -07001019 if (mpic_is_ht_interrupt(mpic, hw))
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001020 chip = &mpic->hc_ht_irq;
Michael Ellerman6cfef5b2007-04-23 18:47:08 +10001021#endif /* CONFIG_MPIC_U3_HT_IRQS */
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001022
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -07001023 DBG("mpic: mapping to irq chip @%p\n", chip);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001024
Thomas Gleixnerec775d02011-03-25 16:45:20 +01001025 irq_set_chip_data(virq, mpic);
1026 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -07001027
1028 /* Set default irq type */
Thomas Gleixnerec775d02011-03-25 16:45:20 +01001029 irq_set_irq_type(virq, IRQ_TYPE_NONE);
Benjamin Herrenschmidt6e99e452006-07-10 04:44:42 -07001030
Meador Ingedfec2202011-03-14 10:01:06 +00001031 /* If the MPIC was reset, then all vectors have already been
1032 * initialized. Otherwise, a per source lazy initialization
1033 * is done here.
1034 */
1035 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
Meador Ingedfec2202011-03-14 10:01:06 +00001036 mpic_set_vector(virq, hw);
Meador Inged6a26392011-03-14 10:01:07 +00001037 mpic_set_destination(virq, mpic_processor_id(mpic));
Meador Ingedfec2202011-03-14 10:01:06 +00001038 mpic_irq_set_priority(virq, 8);
1039 }
1040
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001041 return 0;
1042}
1043
1044static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
Roman Fietze40d50cf2009-12-08 02:39:50 +00001045 const u32 *intspec, unsigned int intsize,
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001046 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1047
1048{
Scott Wood22d168c2011-03-24 16:43:54 -05001049 struct mpic *mpic = h->host_data;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001050 static unsigned char map_mpic_senses[4] = {
1051 IRQ_TYPE_EDGE_RISING,
1052 IRQ_TYPE_LEVEL_LOW,
1053 IRQ_TYPE_LEVEL_HIGH,
1054 IRQ_TYPE_EDGE_FALLING,
1055 };
1056
1057 *out_hwirq = intspec[0];
Scott Wood22d168c2011-03-24 16:43:54 -05001058 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1059 /*
1060 * Freescale MPIC with extended intspec:
1061 * First two cells are as usual. Third specifies
1062 * an "interrupt type". Fourth is type-specific data.
1063 *
1064 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1065 */
1066 switch (intspec[2]) {
1067 case 0:
1068 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1069 break;
1070 case 2:
1071 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1072 return -EINVAL;
1073
1074 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1075 break;
1076 case 3:
1077 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1078 return -EINVAL;
1079
1080 *out_hwirq = mpic->timer_vecs[intspec[0]];
1081 break;
1082 default:
1083 pr_debug("%s: unknown irq type %u\n",
1084 __func__, intspec[2]);
1085 return -EINVAL;
1086 }
1087
1088 *out_flags = map_mpic_senses[intspec[1] & 3];
1089 } else if (intsize > 1) {
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -07001090 u32 mask = 0x3;
1091
1092 /* Apple invented a new race of encoding on machines with
1093 * an HT APIC. They encode, among others, the index within
1094 * the HT APIC. We don't care about it here since thankfully,
1095 * it appears that they have the APIC already properly
1096 * configured, and thus our current fixup code that reads the
1097 * APIC config works fine. However, we still need to mask out
1098 * bits in the specifier to make sure we only get bit 0 which
1099 * is the level/edge bit (the only sense bit exposed by Apple),
1100 * as their bit 1 means something else.
1101 */
1102 if (machine_is(powermac))
1103 mask = 0x1;
1104 *out_flags = map_mpic_senses[intspec[1] & mask];
1105 } else
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001106 *out_flags = IRQ_TYPE_NONE;
1107
Benjamin Herrenschmidt06fe98e2006-07-10 04:44:43 -07001108 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1109 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1110
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001111 return 0;
1112}
1113
Kyle Moffett09dc34a2011-12-02 06:28:07 +00001114/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1115static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1116{
1117 struct irq_chip *chip = irq_desc_get_chip(desc);
1118 struct mpic *mpic = irq_desc_get_handler_data(desc);
1119 unsigned int virq;
1120
1121 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1122
1123 virq = mpic_get_one_irq(mpic);
1124 if (virq != NO_IRQ)
1125 generic_handle_irq(virq);
1126
1127 chip->irq_eoi(&desc->irq_data);
1128}
1129
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001130static struct irq_host_ops mpic_host_ops = {
1131 .match = mpic_host_match,
1132 .map = mpic_host_map,
1133 .xlate = mpic_host_xlate,
1134};
1135
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001136/*
1137 * Exported functions
1138 */
1139
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001140struct mpic * __init mpic_alloc(struct device_node *node,
Benjamin Herrenschmidta959ff52006-11-11 17:24:56 +11001141 phys_addr_t phys_addr,
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001142 unsigned int flags,
1143 unsigned int isu_size,
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001144 unsigned int irq_count,
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001145 const char *name)
1146{
Kyle Moffett5bdb6f22011-12-02 06:28:00 +00001147 int i, psize, intvec_top;
1148 struct mpic *mpic;
1149 u32 greg_feature;
1150 const char *vers;
1151 const u32 *psrc;
Kyle Moffettc1b8d452011-12-22 10:19:13 +00001152 u32 last_irq;
Kyle Moffett8bf41562011-12-02 06:27:59 +00001153
Kyle Moffett996983b2011-12-02 06:28:02 +00001154 /* Default MPIC search parameters */
1155 static const struct of_device_id __initconst mpic_device_id[] = {
1156 { .type = "open-pic", },
1157 { .compatible = "open-pic", },
1158 {},
1159 };
1160
1161 /*
1162 * If we were not passed a device-tree node, then perform the default
1163 * search for standardized a standardized OpenPIC.
1164 */
1165 if (node) {
1166 node = of_node_get(node);
1167 } else {
1168 node = of_find_matching_node(NULL, mpic_device_id);
1169 if (!node)
1170 return NULL;
1171 }
Kyle Moffett5bdb6f22011-12-02 06:28:00 +00001172
1173 /* Pick the physical address from the device tree if unspecified */
Kyle Moffett8bf41562011-12-02 06:27:59 +00001174 if (!phys_addr) {
Kyle Moffett8bf41562011-12-02 06:27:59 +00001175 /* Check if it is DCR-based */
1176 if (of_get_property(node, "dcr-reg", NULL)) {
1177 flags |= MPIC_USES_DCR;
1178 } else {
1179 struct resource r;
1180 if (of_address_to_resource(node, 0, &r))
Kyle Moffett996983b2011-12-02 06:28:02 +00001181 goto err_of_node_put;
Kyle Moffett8bf41562011-12-02 06:27:59 +00001182 phys_addr = r.start;
1183 }
1184 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001185
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001186 /* Read extra device-tree properties into the flags variable */
1187 if (of_get_property(node, "big-endian", NULL))
1188 flags |= MPIC_BIG_ENDIAN;
1189 if (of_get_property(node, "pic-no-reset", NULL))
1190 flags |= MPIC_NO_RESET;
Kyle Moffett9ca163c2011-12-22 10:19:11 +00001191 if (of_get_property(node, "single-cpu-affinity", NULL))
1192 flags |= MPIC_SINGLE_DEST_CPU;
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001193 if (of_device_is_compatible(node, "fsl,mpic"))
1194 flags |= MPIC_FSL;
1195
Kumar Gala85355bb2009-06-18 22:01:20 +00001196 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001197 if (mpic == NULL)
Kyle Moffett996983b2011-12-02 06:28:02 +00001198 goto err_of_node_put;
Kumar Gala85355bb2009-06-18 22:01:20 +00001199
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001200 mpic->name = name;
Kyle Moffettc51242e2011-12-02 06:28:06 +00001201 mpic->node = node;
Kyle Moffette7a98672011-12-02 06:28:01 +00001202 mpic->paddr = phys_addr;
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001203 mpic->flags = flags;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001204
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +10001205 mpic->hc_irq = mpic_irq_chip;
Thomas Gleixnerb27df672009-11-18 23:44:21 +00001206 mpic->hc_irq.name = name;
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001207 if (!(mpic->flags & MPIC_SECONDARY))
Lennert Buytenhek835c05532011-03-08 22:26:43 +00001208 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
Michael Ellerman6cfef5b2007-04-23 18:47:08 +10001209#ifdef CONFIG_MPIC_U3_HT_IRQS
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +10001210 mpic->hc_ht_irq = mpic_irq_ht_chip;
Thomas Gleixnerb27df672009-11-18 23:44:21 +00001211 mpic->hc_ht_irq.name = name;
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001212 if (!(mpic->flags & MPIC_SECONDARY))
Lennert Buytenhek835c05532011-03-08 22:26:43 +00001213 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
Michael Ellerman6cfef5b2007-04-23 18:47:08 +10001214#endif /* CONFIG_MPIC_U3_HT_IRQS */
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001215
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001216#ifdef CONFIG_SMP
Benjamin Herrenschmidtb9e5b4e2006-07-03 19:32:51 +10001217 mpic->hc_ipi = mpic_ipi_chip;
Thomas Gleixnerb27df672009-11-18 23:44:21 +00001218 mpic->hc_ipi.name = name;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001219#endif /* CONFIG_SMP */
1220
Scott Woodea941872011-03-24 16:43:55 -05001221 mpic->hc_tm = mpic_tm_chip;
1222 mpic->hc_tm.name = name;
1223
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001224 mpic->num_sources = 0; /* so far */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001225
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001226 if (mpic->flags & MPIC_LARGE_VECTORS)
Olof Johansson7df24572007-01-28 23:33:18 -06001227 intvec_top = 2047;
1228 else
1229 intvec_top = 255;
1230
Scott Woodea941872011-03-24 16:43:55 -05001231 mpic->timer_vecs[0] = intvec_top - 12;
1232 mpic->timer_vecs[1] = intvec_top - 11;
1233 mpic->timer_vecs[2] = intvec_top - 10;
1234 mpic->timer_vecs[3] = intvec_top - 9;
1235 mpic->timer_vecs[4] = intvec_top - 8;
1236 mpic->timer_vecs[5] = intvec_top - 7;
1237 mpic->timer_vecs[6] = intvec_top - 6;
1238 mpic->timer_vecs[7] = intvec_top - 5;
Olof Johansson7df24572007-01-28 23:33:18 -06001239 mpic->ipi_vecs[0] = intvec_top - 4;
1240 mpic->ipi_vecs[1] = intvec_top - 3;
1241 mpic->ipi_vecs[2] = intvec_top - 2;
1242 mpic->ipi_vecs[3] = intvec_top - 1;
1243 mpic->spurious_vec = intvec_top;
1244
Benjamin Herrenschmidt7fd72182007-07-21 09:55:21 +10001245 /* Look for protected sources */
Kyle Moffettc51242e2011-12-02 06:28:06 +00001246 psrc = of_get_property(mpic->node, "protected-sources", &psize);
Kyle Moffett5bdb6f22011-12-02 06:28:00 +00001247 if (psrc) {
1248 /* Allocate a bitmap with one bit per interrupt */
1249 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1250 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1251 BUG_ON(mpic->protected == NULL);
1252 for (i = 0; i < psize/sizeof(u32); i++) {
1253 if (psrc[i] > intvec_top)
1254 continue;
1255 __set_bit(psrc[i], mpic->protected);
Benjamin Herrenschmidt7fd72182007-07-21 09:55:21 +10001256 }
1257 }
Benjamin Herrenschmidta959ff52006-11-11 17:24:56 +11001258
Zang Roy-r6191172335932006-08-25 14:16:30 +10001259#ifdef CONFIG_MPIC_WEIRD
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001260 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
Zang Roy-r6191172335932006-08-25 14:16:30 +10001261#endif
1262
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001263 /* default register type */
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001264 if (mpic->flags & MPIC_BIG_ENDIAN)
Kyle Moffett8bf41562011-12-02 06:27:59 +00001265 mpic->reg_type = mpic_access_mmio_be;
1266 else
1267 mpic->reg_type = mpic_access_mmio_le;
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001268
Kyle Moffett8bf41562011-12-02 06:27:59 +00001269 /*
1270 * An MPIC with a "dcr-reg" property must be accessed that way, but
1271 * only if the kernel includes DCR support.
1272 */
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001273#ifdef CONFIG_PPC_DCR
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001274 if (mpic->flags & MPIC_USES_DCR)
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001275 mpic->reg_type = mpic_access_dcr;
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001276#else
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001277 BUG_ON(mpic->flags & MPIC_USES_DCR);
Kyle Moffett8bf41562011-12-02 06:27:59 +00001278#endif
Benjamin Herrenschmidta959ff52006-11-11 17:24:56 +11001279
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001280 /* Map the global registers */
Kyle Moffettc51242e2011-12-02 06:28:06 +00001281 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1282 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001283
1284 /* Reset */
Meador Ingedfec2202011-03-14 10:01:06 +00001285
1286 /* When using a device-node, reset requests are only honored if the MPIC
1287 * is allowed to reset.
1288 */
Kyle Moffette55d7f72011-12-22 10:19:14 +00001289 if (!(mpic->flags & MPIC_NO_RESET)) {
Meador Ingedfec2202011-03-14 10:01:06 +00001290 printk(KERN_DEBUG "mpic: Resetting\n");
Zang Roy-r6191172335932006-08-25 14:16:30 +10001291 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1292 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001293 | MPIC_GREG_GCONF_RESET);
Zang Roy-r6191172335932006-08-25 14:16:30 +10001294 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001295 & MPIC_GREG_GCONF_RESET)
1296 mb();
1297 }
1298
Kumar Galad91e4ea2009-01-07 15:53:29 -06001299 /* CoreInt */
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001300 if (mpic->flags & MPIC_ENABLE_COREINT)
Kumar Galad91e4ea2009-01-07 15:53:29 -06001301 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1302 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1303 | MPIC_GREG_GCONF_COREINT);
1304
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001305 if (mpic->flags & MPIC_ENABLE_MCK)
Olof Johanssonf3653552007-12-20 13:11:18 -06001306 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1307 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1308 | MPIC_GREG_GCONF_MCK);
1309
Timur Tabi14b92472011-07-08 11:12:42 +00001310 /*
Timur Tabi14b92472011-07-08 11:12:42 +00001311 * The MPIC driver will crash if there are more cores than we
1312 * can initialize, so we may as well catch that problem here.
1313 */
1314 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1315
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001316 /* Map the per-CPU registers */
Timur Tabi14b92472011-07-08 11:12:42 +00001317 for_each_possible_cpu(i) {
1318 unsigned int cpu = get_hard_smp_processor_id(i);
1319
Kyle Moffettc51242e2011-12-02 06:28:06 +00001320 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
Timur Tabi14b92472011-07-08 11:12:42 +00001321 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001322 0x1000);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001323 }
1324
Kyle Moffettc1b8d452011-12-22 10:19:13 +00001325 /*
1326 * Read feature register. For non-ISU MPICs, num sources as well. On
1327 * ISU MPICs, sources are counted as ISUs are added
1328 */
1329 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1330
1331 /*
1332 * By default, the last source number comes from the MPIC, but the
1333 * device-tree and board support code can override it on buggy hw.
1334 */
1335 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1336 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1337 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1338 if (irq_count)
1339 last_irq = irq_count - 1;
1340
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001341 /* Initialize main ISU if none provided */
Kyle Moffettc1b8d452011-12-22 10:19:13 +00001342 if (!isu_size) {
1343 isu_size = last_irq + 1;
1344 mpic->num_sources = isu_size;
Kyle Moffettc51242e2011-12-02 06:28:06 +00001345 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
Kyle Moffettc1b8d452011-12-22 10:19:13 +00001346 MPIC_INFO(IRQ_BASE),
1347 MPIC_INFO(IRQ_STRIDE) * isu_size);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001348 }
Kyle Moffettc1b8d452011-12-22 10:19:13 +00001349
1350 mpic->isu_size = isu_size;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001351 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1352 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1353
Kyle Moffettc51242e2011-12-02 06:28:06 +00001354 mpic->irqhost = irq_alloc_host(mpic->node, IRQ_HOST_MAP_LINEAR,
Kyle Moffettc1b8d452011-12-22 10:19:13 +00001355 mpic->isu_size, &mpic_host_ops,
1356 intvec_top + 1);
Kyle Moffett996983b2011-12-02 06:28:02 +00001357
1358 /*
1359 * FIXME: The code leaks the MPIC object and mappings here; this
1360 * is very unlikely to fail but it ought to be fixed anyways.
1361 */
Kumar Gala31207da2009-05-08 12:08:20 +00001362 if (mpic->irqhost == NULL)
1363 return NULL;
1364
1365 mpic->irqhost->host_data = mpic;
1366
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001367 /* Display version */
Johannes Bergd9d10632008-02-21 20:39:01 +11001368 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001369 case 1:
1370 vers = "1.0";
1371 break;
1372 case 2:
1373 vers = "1.2";
1374 break;
1375 case 3:
1376 vers = "1.3";
1377 break;
1378 default:
1379 vers = "<unknown>";
1380 break;
1381 }
Benjamin Herrenschmidta959ff52006-11-11 17:24:56 +11001382 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1383 " max %d CPUs\n",
Kyle Moffette7a98672011-12-02 06:28:01 +00001384 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
Benjamin Herrenschmidta959ff52006-11-11 17:24:56 +11001385 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1386 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001387
1388 mpic->next = mpics;
1389 mpics = mpic;
1390
Kyle Moffett3a7a7172011-12-22 10:19:09 +00001391 if (!(mpic->flags & MPIC_SECONDARY)) {
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001392 mpic_primary = mpic;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001393 irq_set_default_host(mpic->irqhost);
1394 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001395
1396 return mpic;
Kyle Moffett996983b2011-12-02 06:28:02 +00001397
1398err_of_node_put:
1399 of_node_put(node);
1400 return NULL;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001401}
1402
1403void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
Benjamin Herrenschmidta959ff52006-11-11 17:24:56 +11001404 phys_addr_t paddr)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001405{
1406 unsigned int isu_first = isu_num * mpic->isu_size;
1407
1408 BUG_ON(isu_num >= MPIC_MAX_ISU);
1409
Kyle Moffettc51242e2011-12-02 06:28:06 +00001410 mpic_map(mpic,
Benjamin Herrenschmidt5a2642f2009-06-22 16:47:59 +00001411 paddr, &mpic->isus[isu_num], 0,
Benjamin Herrenschmidtfbf02742006-11-11 17:24:55 +11001412 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
Benjamin Herrenschmidt5a2642f2009-06-22 16:47:59 +00001413
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001414 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1415 mpic->num_sources = isu_first + mpic->isu_size;
1416}
1417
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001418void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1419{
1420 mpic->senses = senses;
1421 mpic->senses_count = count;
1422}
1423
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001424void __init mpic_init(struct mpic *mpic)
1425{
Kyle Moffett09dc34a2011-12-02 06:28:07 +00001426 int i, cpu;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001427
1428 BUG_ON(mpic->num_sources == 0);
1429
1430 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1431
1432 /* Set current processor priority to max */
Zang Roy-r6191172335932006-08-25 14:16:30 +10001433 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001434
Scott Woodea941872011-03-24 16:43:55 -05001435 /* Initialize timers to our reserved vectors and mask them for now */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001436 for (i = 0; i < 4; i++) {
1437 mpic_write(mpic->tmregs,
Zang Roy-r6191172335932006-08-25 14:16:30 +10001438 i * MPIC_INFO(TIMER_STRIDE) +
Scott Woodea941872011-03-24 16:43:55 -05001439 MPIC_INFO(TIMER_DESTINATION),
1440 1 << hard_smp_processor_id());
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001441 mpic_write(mpic->tmregs,
Zang Roy-r6191172335932006-08-25 14:16:30 +10001442 i * MPIC_INFO(TIMER_STRIDE) +
1443 MPIC_INFO(TIMER_VECTOR_PRI),
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001444 MPIC_VECPRI_MASK |
Scott Woodea941872011-03-24 16:43:55 -05001445 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
Olof Johansson7df24572007-01-28 23:33:18 -06001446 (mpic->timer_vecs[0] + i));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001447 }
1448
1449 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1450 mpic_test_broken_ipi(mpic);
1451 for (i = 0; i < 4; i++) {
1452 mpic_ipi_write(i,
1453 MPIC_VECPRI_MASK |
1454 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
Olof Johansson7df24572007-01-28 23:33:18 -06001455 (mpic->ipi_vecs[0] + i));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001456 }
1457
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001458 /* Do the HT PIC fixups on U3 broken mpic */
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001459 DBG("MPIC flags: %x\n", mpic->flags);
Kyle Moffettbe8bec52011-12-02 06:28:03 +00001460 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
Johannes Berg3669e932007-05-02 16:33:41 +10001461 mpic_scan_ht_pics(mpic);
Michael Ellerman05af7bd2007-05-08 12:58:37 +10001462 mpic_u3msi_init(mpic);
1463 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001464
Olof Johansson38958dd2007-12-12 17:44:46 +11001465 mpic_pasemi_msi_init(mpic);
1466
Meador Inged6a26392011-03-14 10:01:07 +00001467 cpu = mpic_processor_id(mpic);
Arnd Bergmanncc353c32008-11-28 09:51:23 +00001468
Meador Ingedfec2202011-03-14 10:01:06 +00001469 if (!(mpic->flags & MPIC_NO_RESET)) {
1470 for (i = 0; i < mpic->num_sources; i++) {
1471 /* start with vector = source number, and masked */
1472 u32 vecpri = MPIC_VECPRI_MASK | i |
1473 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001474
Meador Ingedfec2202011-03-14 10:01:06 +00001475 /* check if protected */
1476 if (mpic->protected && test_bit(i, mpic->protected))
1477 continue;
1478 /* init hw */
1479 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1480 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1481 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001482 }
1483
Olof Johansson7df24572007-01-28 23:33:18 -06001484 /* Init spurious vector */
1485 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001486
Zang Roy-r6191172335932006-08-25 14:16:30 +10001487 /* Disable 8259 passthrough, if supported */
1488 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1489 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1490 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1491 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001492
Olof Johanssond87bf3b2007-12-27 22:16:29 -06001493 if (mpic->flags & MPIC_NO_BIAS)
1494 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1495 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1496 | MPIC_GREG_GCONF_NO_BIAS);
1497
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001498 /* Set current processor priority to 0 */
Zang Roy-r6191172335932006-08-25 14:16:30 +10001499 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
Johannes Berg3669e932007-05-02 16:33:41 +10001500
1501#ifdef CONFIG_PM
1502 /* allocate memory to save mpic state */
Anton Vorontsovea960252009-07-01 10:59:57 +00001503 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1504 GFP_KERNEL);
Johannes Berg3669e932007-05-02 16:33:41 +10001505 BUG_ON(mpic->save_data == NULL);
1506#endif
Kyle Moffett09dc34a2011-12-02 06:28:07 +00001507
1508 /* Check if this MPIC is chained from a parent interrupt controller */
1509 if (mpic->flags & MPIC_SECONDARY) {
1510 int virq = irq_of_parse_and_map(mpic->node, 0);
1511 if (virq != NO_IRQ) {
1512 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1513 mpic->node->full_name, virq);
1514 irq_set_handler_data(virq, mpic);
1515 irq_set_chained_handler(virq, &mpic_cascade);
1516 }
1517 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001518}
1519
Mark A. Greer868ea0c2006-06-20 14:15:36 -07001520void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1521{
1522 u32 v;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001523
Mark A. Greer868ea0c2006-06-20 14:15:36 -07001524 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1525 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1526 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1527 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1528}
1529
1530void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1531{
Benjamin Herrenschmidtba1826e2006-07-05 15:36:15 +10001532 unsigned long flags;
Mark A. Greer868ea0c2006-06-20 14:15:36 -07001533 u32 v;
1534
Thomas Gleixner203041a2010-02-18 02:23:18 +00001535 raw_spin_lock_irqsave(&mpic_lock, flags);
Mark A. Greer868ea0c2006-06-20 14:15:36 -07001536 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1537 if (enable)
1538 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1539 else
1540 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1541 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
Thomas Gleixner203041a2010-02-18 02:23:18 +00001542 raw_spin_unlock_irqrestore(&mpic_lock, flags);
Mark A. Greer868ea0c2006-06-20 14:15:36 -07001543}
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001544
1545void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1546{
Tony Breedsd69a78d2009-04-07 18:26:54 +00001547 struct mpic *mpic = mpic_find(irq);
Grant Likely476eb492011-05-04 15:02:15 +10001548 unsigned int src = virq_to_hw(irq);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001549 unsigned long flags;
1550 u32 reg;
1551
Stephen Rothwell06a901c2008-05-21 16:24:31 +10001552 if (!mpic)
1553 return;
1554
Thomas Gleixner203041a2010-02-18 02:23:18 +00001555 raw_spin_lock_irqsave(&mpic_lock, flags);
Tony Breedsd69a78d2009-04-07 18:26:54 +00001556 if (mpic_is_ipi(mpic, irq)) {
Olof Johansson7df24572007-01-28 23:33:18 -06001557 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
Benjamin Herrenschmidte5356642005-11-18 17:18:15 +11001558 ~MPIC_VECPRI_PRIORITY_MASK;
Olof Johansson7df24572007-01-28 23:33:18 -06001559 mpic_ipi_write(src - mpic->ipi_vecs[0],
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001560 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
Scott Woodea941872011-03-24 16:43:55 -05001561 } else if (mpic_is_tm(mpic, irq)) {
1562 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1563 ~MPIC_VECPRI_PRIORITY_MASK;
1564 mpic_tm_write(src - mpic->timer_vecs[0],
1565 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001566 } else {
Zang Roy-r6191172335932006-08-25 14:16:30 +10001567 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
Benjamin Herrenschmidte5356642005-11-18 17:18:15 +11001568 & ~MPIC_VECPRI_PRIORITY_MASK;
Zang Roy-r6191172335932006-08-25 14:16:30 +10001569 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001570 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1571 }
Thomas Gleixner203041a2010-02-18 02:23:18 +00001572 raw_spin_unlock_irqrestore(&mpic_lock, flags);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001573}
1574
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001575void mpic_setup_this_cpu(void)
1576{
1577#ifdef CONFIG_SMP
1578 struct mpic *mpic = mpic_primary;
1579 unsigned long flags;
1580 u32 msk = 1 << hard_smp_processor_id();
1581 unsigned int i;
1582
1583 BUG_ON(mpic == NULL);
1584
1585 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1586
Thomas Gleixner203041a2010-02-18 02:23:18 +00001587 raw_spin_lock_irqsave(&mpic_lock, flags);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001588
1589 /* let the mpic know we want intrs. default affinity is 0xffffffff
1590 * until changed via /proc. That's how it's done on x86. If we want
1591 * it differently, then we should make sure we also change the default
Ingo Molnara53da522006-06-29 02:24:38 -07001592 * values of irq_desc[].affinity in irq.c.
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001593 */
1594 if (distribute_irqs) {
1595 for (i = 0; i < mpic->num_sources ; i++)
Zang Roy-r6191172335932006-08-25 14:16:30 +10001596 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1597 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001598 }
1599
1600 /* Set current processor priority to 0 */
Zang Roy-r6191172335932006-08-25 14:16:30 +10001601 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001602
Thomas Gleixner203041a2010-02-18 02:23:18 +00001603 raw_spin_unlock_irqrestore(&mpic_lock, flags);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001604#endif /* CONFIG_SMP */
1605}
1606
1607int mpic_cpu_get_priority(void)
1608{
1609 struct mpic *mpic = mpic_primary;
1610
Zang Roy-r6191172335932006-08-25 14:16:30 +10001611 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001612}
1613
1614void mpic_cpu_set_priority(int prio)
1615{
1616 struct mpic *mpic = mpic_primary;
1617
1618 prio &= MPIC_CPU_TASKPRI_MASK;
Zang Roy-r6191172335932006-08-25 14:16:30 +10001619 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001620}
1621
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001622void mpic_teardown_this_cpu(int secondary)
1623{
1624 struct mpic *mpic = mpic_primary;
1625 unsigned long flags;
1626 u32 msk = 1 << hard_smp_processor_id();
1627 unsigned int i;
1628
1629 BUG_ON(mpic == NULL);
1630
1631 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
Thomas Gleixner203041a2010-02-18 02:23:18 +00001632 raw_spin_lock_irqsave(&mpic_lock, flags);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001633
1634 /* let the mpic know we don't want intrs. */
1635 for (i = 0; i < mpic->num_sources ; i++)
Zang Roy-r6191172335932006-08-25 14:16:30 +10001636 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1637 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001638
1639 /* Set current processor priority to max */
Zang Roy-r6191172335932006-08-25 14:16:30 +10001640 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
Valentine Barshak71327992008-04-03 23:09:43 +04001641 /* We need to EOI the IPI since not all platforms reset the MPIC
1642 * on boot and new interrupts wouldn't get delivered otherwise.
1643 */
1644 mpic_eoi(mpic);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001645
Thomas Gleixner203041a2010-02-18 02:23:18 +00001646 raw_spin_unlock_irqrestore(&mpic_lock, flags);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001647}
1648
1649
Olof Johanssonf3653552007-12-20 13:11:18 -06001650static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001651{
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001652 u32 src;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001653
Olof Johanssonf3653552007-12-20 13:11:18 -06001654 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001655#ifdef DEBUG_LOW
Olof Johanssonf3653552007-12-20 13:11:18 -06001656 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001657#endif
Josh Boyer5cddd2e2007-05-01 06:38:11 +10001658 if (unlikely(src == mpic->spurious_vec)) {
1659 if (mpic->flags & MPIC_SPV_EOI)
1660 mpic_eoi(mpic);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001661 return NO_IRQ;
Josh Boyer5cddd2e2007-05-01 06:38:11 +10001662 }
Benjamin Herrenschmidt7fd72182007-07-21 09:55:21 +10001663 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
Christian Dietrich76462232011-06-04 05:36:54 +00001664 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1665 mpic->name, (int)src);
Benjamin Herrenschmidt7fd72182007-07-21 09:55:21 +10001666 mpic_eoi(mpic);
1667 return NO_IRQ;
1668 }
1669
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001670 return irq_linear_revmap(mpic->irqhost, src);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001671}
1672
Olof Johanssonf3653552007-12-20 13:11:18 -06001673unsigned int mpic_get_one_irq(struct mpic *mpic)
1674{
1675 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1676}
1677
Olaf Hering35a84c22006-10-07 22:08:26 +10001678unsigned int mpic_get_irq(void)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001679{
1680 struct mpic *mpic = mpic_primary;
1681
1682 BUG_ON(mpic == NULL);
1683
Olaf Hering35a84c22006-10-07 22:08:26 +10001684 return mpic_get_one_irq(mpic);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001685}
1686
Kumar Galad91e4ea2009-01-07 15:53:29 -06001687unsigned int mpic_get_coreint_irq(void)
1688{
1689#ifdef CONFIG_BOOKE
1690 struct mpic *mpic = mpic_primary;
1691 u32 src;
1692
1693 BUG_ON(mpic == NULL);
1694
1695 src = mfspr(SPRN_EPR);
1696
1697 if (unlikely(src == mpic->spurious_vec)) {
1698 if (mpic->flags & MPIC_SPV_EOI)
1699 mpic_eoi(mpic);
1700 return NO_IRQ;
1701 }
1702 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
Christian Dietrich76462232011-06-04 05:36:54 +00001703 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1704 mpic->name, (int)src);
Kumar Galad91e4ea2009-01-07 15:53:29 -06001705 return NO_IRQ;
1706 }
1707
1708 return irq_linear_revmap(mpic->irqhost, src);
1709#else
1710 return NO_IRQ;
1711#endif
1712}
1713
Olof Johanssonf3653552007-12-20 13:11:18 -06001714unsigned int mpic_get_mcirq(void)
1715{
1716 struct mpic *mpic = mpic_primary;
1717
1718 BUG_ON(mpic == NULL);
1719
1720 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1721}
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001722
1723#ifdef CONFIG_SMP
1724void mpic_request_ipis(void)
1725{
1726 struct mpic *mpic = mpic_primary;
Milton Miller78608dd2008-10-10 01:56:50 +00001727 int i;
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001728 BUG_ON(mpic == NULL);
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001729
Frans Pop8354be92010-02-06 07:47:20 +00001730 printk(KERN_INFO "mpic: requesting IPIs...\n");
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001731
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001732 for (i = 0; i < 4; i++) {
1733 unsigned int vipi = irq_create_mapping(mpic->irqhost,
Olof Johansson7df24572007-01-28 23:33:18 -06001734 mpic->ipi_vecs[0] + i);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001735 if (vipi == NO_IRQ) {
Milton Miller78608dd2008-10-10 01:56:50 +00001736 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1737 continue;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001738 }
Milton Miller78608dd2008-10-10 01:56:50 +00001739 smp_request_message_ipi(vipi, i);
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +10001740 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001741}
Paul Mackerrasa9c59262005-10-20 17:09:51 +10001742
Milton Miller3caba982011-05-10 19:29:17 +00001743void smp_mpic_message_pass(int cpu, int msg)
Benjamin Herrenschmidt2ef613cb2010-05-06 18:01:46 +10001744{
1745 struct mpic *mpic = mpic_primary;
Milton Miller3caba982011-05-10 19:29:17 +00001746 u32 physmask;
Benjamin Herrenschmidt2ef613cb2010-05-06 18:01:46 +10001747
1748 BUG_ON(mpic == NULL);
1749
Paul Mackerrasa9c59262005-10-20 17:09:51 +10001750 /* make sure we're sending something that translates to an IPI */
1751 if ((unsigned int)msg > 3) {
1752 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1753 smp_processor_id(), msg);
1754 return;
1755 }
Milton Miller3caba982011-05-10 19:29:17 +00001756
1757#ifdef DEBUG_IPI
1758 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1759#endif
1760
1761 physmask = 1 << get_hard_smp_processor_id(cpu);
1762
1763 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1764 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
Paul Mackerrasa9c59262005-10-20 17:09:51 +10001765}
Michael Ellerman775aeff2007-02-08 18:34:04 +11001766
1767int __init smp_mpic_probe(void)
1768{
1769 int nr_cpus;
1770
1771 DBG("smp_mpic_probe()...\n");
1772
Benjamin Herrenschmidt2ef613cb2010-05-06 18:01:46 +10001773 nr_cpus = cpumask_weight(cpu_possible_mask);
Michael Ellerman775aeff2007-02-08 18:34:04 +11001774
1775 DBG("nr_cpus: %d\n", nr_cpus);
1776
1777 if (nr_cpus > 1)
1778 mpic_request_ipis();
1779
1780 return nr_cpus;
1781}
1782
1783void __devinit smp_mpic_setup_cpu(int cpu)
1784{
1785 mpic_setup_this_cpu();
1786}
Matthew McClintock66953eb2010-06-29 09:42:26 +00001787
1788void mpic_reset_core(int cpu)
1789{
1790 struct mpic *mpic = mpic_primary;
1791 u32 pir;
1792 int cpuid = get_hard_smp_processor_id(cpu);
Matthew McClintock44f16fc2011-10-26 13:46:57 -05001793 int i;
Matthew McClintock66953eb2010-06-29 09:42:26 +00001794
1795 /* Set target bit for core reset */
1796 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1797 pir |= (1 << cpuid);
1798 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1799 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1800
1801 /* Restore target bit after reset complete */
1802 pir &= ~(1 << cpuid);
1803 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1804 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
Matthew McClintock44f16fc2011-10-26 13:46:57 -05001805
1806 /* Perform 15 EOI on each reset core to clear pending interrupts.
1807 * This is required for FSL CoreNet based devices */
1808 if (mpic->flags & MPIC_FSL) {
1809 for (i = 0; i < 15; i++) {
1810 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1811 MPIC_CPU_EOI, 0);
1812 }
1813 }
Matthew McClintock66953eb2010-06-29 09:42:26 +00001814}
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001815#endif /* CONFIG_SMP */
Johannes Berg3669e932007-05-02 16:33:41 +10001816
1817#ifdef CONFIG_PM
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +02001818static void mpic_suspend_one(struct mpic *mpic)
Johannes Berg3669e932007-05-02 16:33:41 +10001819{
Johannes Berg3669e932007-05-02 16:33:41 +10001820 int i;
1821
1822 for (i = 0; i < mpic->num_sources; i++) {
1823 mpic->save_data[i].vecprio =
1824 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1825 mpic->save_data[i].dest =
1826 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1827 }
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +02001828}
1829
1830static int mpic_suspend(void)
1831{
1832 struct mpic *mpic = mpics;
1833
1834 while (mpic) {
1835 mpic_suspend_one(mpic);
1836 mpic = mpic->next;
1837 }
Johannes Berg3669e932007-05-02 16:33:41 +10001838
1839 return 0;
1840}
1841
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +02001842static void mpic_resume_one(struct mpic *mpic)
Johannes Berg3669e932007-05-02 16:33:41 +10001843{
Johannes Berg3669e932007-05-02 16:33:41 +10001844 int i;
1845
1846 for (i = 0; i < mpic->num_sources; i++) {
1847 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1848 mpic->save_data[i].vecprio);
1849 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1850 mpic->save_data[i].dest);
1851
1852#ifdef CONFIG_MPIC_U3_HT_IRQS
Alastair Bridgewater7c9d9362010-06-12 15:36:48 +00001853 if (mpic->fixups) {
Johannes Berg3669e932007-05-02 16:33:41 +10001854 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1855
1856 if (fixup->base) {
1857 /* we use the lowest bit in an inverted meaning */
1858 if ((mpic->save_data[i].fixup_data & 1) == 0)
1859 continue;
1860
1861 /* Enable and configure */
1862 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1863
1864 writel(mpic->save_data[i].fixup_data & ~1,
1865 fixup->base + 4);
1866 }
1867 }
1868#endif
1869 } /* end for loop */
Johannes Berg3669e932007-05-02 16:33:41 +10001870}
Johannes Berg3669e932007-05-02 16:33:41 +10001871
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +02001872static void mpic_resume(void)
1873{
1874 struct mpic *mpic = mpics;
1875
1876 while (mpic) {
1877 mpic_resume_one(mpic);
1878 mpic = mpic->next;
1879 }
1880}
1881
1882static struct syscore_ops mpic_syscore_ops = {
Johannes Berg3669e932007-05-02 16:33:41 +10001883 .resume = mpic_resume,
1884 .suspend = mpic_suspend,
Johannes Berg3669e932007-05-02 16:33:41 +10001885};
1886
1887static int mpic_init_sys(void)
1888{
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +02001889 register_syscore_ops(&mpic_syscore_ops);
1890 return 0;
Johannes Berg3669e932007-05-02 16:33:41 +10001891}
1892
1893device_initcall(mpic_init_sys);
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +02001894#endif