blob: 3c12f396d96a3223664fae8d633f15f583ce7545 [file] [log] [blame]
Zhiwu Song1cc2df92012-02-13 17:45:38 +08001/*
2 * SPI bus driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/of_gpio.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
Barry Songde39f5f2013-08-06 14:21:21 +080022#include <linux/dmaengine.h>
23#include <linux/dma-direction.h>
24#include <linux/dma-mapping.h>
Zhiwu Song1cc2df92012-02-13 17:45:38 +080025
26#define DRIVER_NAME "sirfsoc_spi"
27
28#define SIRFSOC_SPI_CTRL 0x0000
29#define SIRFSOC_SPI_CMD 0x0004
30#define SIRFSOC_SPI_TX_RX_EN 0x0008
31#define SIRFSOC_SPI_INT_EN 0x000C
32#define SIRFSOC_SPI_INT_STATUS 0x0010
33#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
34#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
35#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
36#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
37#define SIRFSOC_SPI_TXFIFO_OP 0x0110
38#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
39#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
40#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
41#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
42#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
43#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
44#define SIRFSOC_SPI_RXFIFO_OP 0x0130
45#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
46#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
47#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
48
49/* SPI CTRL register defines */
50#define SIRFSOC_SPI_SLV_MODE BIT(16)
51#define SIRFSOC_SPI_CMD_MODE BIT(17)
52#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
53#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
54#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
55#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
56#define SIRFSOC_SPI_TRAN_MSB BIT(22)
57#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
58#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
59#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
60#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
61#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
62#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
63#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
64#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
65#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
66#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
67
68/* Interrupt Enable */
69#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
70#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
71#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
72#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
73#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
74#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
75#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
76#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
77#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
78#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
79#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
80
81#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
82
83/* Interrupt status */
84#define SIRFSOC_SPI_RX_DONE BIT(0)
85#define SIRFSOC_SPI_TX_DONE BIT(1)
86#define SIRFSOC_SPI_RX_OFLOW BIT(2)
87#define SIRFSOC_SPI_TX_UFLOW BIT(3)
88#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
89#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
90#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
91#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
92#define SIRFSOC_SPI_FRM_END BIT(10)
93
94/* TX RX enable */
95#define SIRFSOC_SPI_RX_EN BIT(0)
96#define SIRFSOC_SPI_TX_EN BIT(1)
97#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
98
99#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
100#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
101
102/* FIFO OPs */
103#define SIRFSOC_SPI_FIFO_RESET BIT(0)
104#define SIRFSOC_SPI_FIFO_START BIT(1)
105
106/* FIFO CTRL */
107#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
108#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
109#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
110
111/* FIFO Status */
112#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
113#define SIRFSOC_SPI_FIFO_FULL BIT(8)
114#define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
115
116/* 256 bytes rx/tx FIFO */
117#define SIRFSOC_SPI_FIFO_SIZE 256
118#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
119
120#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
121#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
122#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
123#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
124
Barry Songde39f5f2013-08-06 14:21:21 +0800125/*
126 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
127 * due to the limitation of dma controller
128 */
129
130#define ALIGNED(x) (!((u32)x & 0x3))
131#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
Qipan Li692fb0f2013-08-25 21:42:50 +0800132 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
Barry Songde39f5f2013-08-06 14:21:21 +0800133
Qipan Lieeb713952014-03-01 12:38:17 +0800134#define SIRFSOC_MAX_CMD_BYTES 4
135
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800136struct sirfsoc_spi {
137 struct spi_bitbang bitbang;
Barry Songde39f5f2013-08-06 14:21:21 +0800138 struct completion rx_done;
139 struct completion tx_done;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800140
141 void __iomem *base;
142 u32 ctrl_freq; /* SPI controller clock speed */
143 struct clk *clk;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800144
145 /* rx & tx bufs from the spi_transfer */
146 const void *tx;
147 void *rx;
148
149 /* place received word into rx buffer */
150 void (*rx_word) (struct sirfsoc_spi *);
151 /* get word from tx buffer for sending */
152 void (*tx_word) (struct sirfsoc_spi *);
153
154 /* number of words left to be tranmitted/received */
Qipan Li692fb0f2013-08-25 21:42:50 +0800155 unsigned int left_tx_word;
156 unsigned int left_rx_word;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800157
Barry Songde39f5f2013-08-06 14:21:21 +0800158 /* rx & tx DMA channels */
159 struct dma_chan *rx_chan;
160 struct dma_chan *tx_chan;
161 dma_addr_t src_start;
162 dma_addr_t dst_start;
163 void *dummypage;
164 int word_width; /* in bytes */
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800165
Qipan Lieeb713952014-03-01 12:38:17 +0800166 /*
167 * if tx size is not more than 4 and rx size is NULL, use
168 * command model
169 */
170 bool tx_by_cmd;
171
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800172 int chipselect[0];
173};
174
175static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
176{
177 u32 data;
178 u8 *rx = sspi->rx;
179
180 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
181
182 if (rx) {
183 *rx++ = (u8) data;
184 sspi->rx = rx;
185 }
186
Qipan Li692fb0f2013-08-25 21:42:50 +0800187 sspi->left_rx_word--;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800188}
189
190static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
191{
192 u32 data = 0;
193 const u8 *tx = sspi->tx;
194
195 if (tx) {
196 data = *tx++;
197 sspi->tx = tx;
198 }
199
200 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
Qipan Li692fb0f2013-08-25 21:42:50 +0800201 sspi->left_tx_word--;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800202}
203
204static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
205{
206 u32 data;
207 u16 *rx = sspi->rx;
208
209 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
210
211 if (rx) {
212 *rx++ = (u16) data;
213 sspi->rx = rx;
214 }
215
Qipan Li692fb0f2013-08-25 21:42:50 +0800216 sspi->left_rx_word--;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800217}
218
219static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
220{
221 u32 data = 0;
222 const u16 *tx = sspi->tx;
223
224 if (tx) {
225 data = *tx++;
226 sspi->tx = tx;
227 }
228
229 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
Qipan Li692fb0f2013-08-25 21:42:50 +0800230 sspi->left_tx_word--;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800231}
232
233static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
234{
235 u32 data;
236 u32 *rx = sspi->rx;
237
238 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
239
240 if (rx) {
241 *rx++ = (u32) data;
242 sspi->rx = rx;
243 }
244
Qipan Li692fb0f2013-08-25 21:42:50 +0800245 sspi->left_rx_word--;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800246
247}
248
249static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
250{
251 u32 data = 0;
252 const u32 *tx = sspi->tx;
253
254 if (tx) {
255 data = *tx++;
256 sspi->tx = tx;
257 }
258
259 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
Qipan Li692fb0f2013-08-25 21:42:50 +0800260 sspi->left_tx_word--;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800261}
262
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800263static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
264{
265 struct sirfsoc_spi *sspi = dev_id;
266 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
267
268 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
269
Qipan Lieeb713952014-03-01 12:38:17 +0800270 if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
271 complete(&sspi->tx_done);
272 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
273 return IRQ_HANDLED;
274 }
275
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800276 /* Error Conditions */
277 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
278 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
Barry Songde39f5f2013-08-06 14:21:21 +0800279 complete(&sspi->rx_done);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800280 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
281 }
282
Qipan Li237ce462013-05-18 19:46:06 +0800283 if (spi_stat & (SIRFSOC_SPI_FRM_END
284 | SIRFSOC_SPI_RXFIFO_THD_REACH))
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800285 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
286 & SIRFSOC_SPI_FIFO_EMPTY)) &&
Qipan Li692fb0f2013-08-25 21:42:50 +0800287 sspi->left_rx_word)
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800288 sspi->rx_word(sspi);
289
Qipan Li818e9162014-04-14 14:29:57 +0800290 if (spi_stat & (SIRFSOC_SPI_TXFIFO_EMPTY |
291 SIRFSOC_SPI_TXFIFO_THD_REACH))
Qipan Li237ce462013-05-18 19:46:06 +0800292 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
293 & SIRFSOC_SPI_FIFO_FULL)) &&
Qipan Li692fb0f2013-08-25 21:42:50 +0800294 sspi->left_tx_word)
Qipan Li237ce462013-05-18 19:46:06 +0800295 sspi->tx_word(sspi);
296
297 /* Received all words */
Qipan Li692fb0f2013-08-25 21:42:50 +0800298 if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) {
Barry Songde39f5f2013-08-06 14:21:21 +0800299 complete(&sspi->rx_done);
Qipan Li237ce462013-05-18 19:46:06 +0800300 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800301 }
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800302 return IRQ_HANDLED;
303}
304
Barry Songde39f5f2013-08-06 14:21:21 +0800305static void spi_sirfsoc_dma_fini_callback(void *data)
306{
307 struct completion *dma_complete = data;
308
309 complete(dma_complete);
310}
311
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800312static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
313{
314 struct sirfsoc_spi *sspi;
315 int timeout = t->len * 10;
316 sspi = spi_master_get_devdata(spi->master);
317
Barry Songde39f5f2013-08-06 14:21:21 +0800318 sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
319 sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
Qipan Li692fb0f2013-08-25 21:42:50 +0800320 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
Wolfram Sang16735d02013-11-14 14:32:02 -0800321 reinit_completion(&sspi->rx_done);
322 reinit_completion(&sspi->tx_done);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800323
324 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
325
Qipan Lieeb713952014-03-01 12:38:17 +0800326 /*
327 * fill tx_buf into command register and wait for its completion
328 */
329 if (sspi->tx_by_cmd) {
330 u32 cmd;
331 memcpy(&cmd, sspi->tx, t->len);
332
333 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
334 cmd = cpu_to_be32(cmd) >>
335 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
336 if (sspi->word_width == 2 && t->len == 4 &&
337 (!(spi->mode & SPI_LSB_FIRST)))
338 cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
339
340 writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
341 writel(SIRFSOC_SPI_FRM_END_INT_EN,
342 sspi->base + SIRFSOC_SPI_INT_EN);
343 writel(SIRFSOC_SPI_CMD_TX_EN,
344 sspi->base + SIRFSOC_SPI_TX_RX_EN);
345
346 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
347 dev_err(&spi->dev, "transfer timeout\n");
348 return 0;
349 }
350
351 return t->len;
352 }
353
Qipan Li692fb0f2013-08-25 21:42:50 +0800354 if (sspi->left_tx_word == 1) {
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800355 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
356 SIRFSOC_SPI_ENA_AUTO_CLR,
357 sspi->base + SIRFSOC_SPI_CTRL);
358 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
359 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
Qipan Li692fb0f2013-08-25 21:42:50 +0800360 } else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word <
361 SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800362 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
363 SIRFSOC_SPI_MUL_DAT_MODE |
364 SIRFSOC_SPI_ENA_AUTO_CLR,
365 sspi->base + SIRFSOC_SPI_CTRL);
Qipan Li692fb0f2013-08-25 21:42:50 +0800366 writel(sspi->left_tx_word - 1,
367 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
368 writel(sspi->left_tx_word - 1,
369 sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800370 } else {
371 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
372 sspi->base + SIRFSOC_SPI_CTRL);
373 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
374 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
375 }
376
377 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
378 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
379 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
380 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
381
Barry Songde39f5f2013-08-06 14:21:21 +0800382 if (IS_DMA_VALID(t)) {
383 struct dma_async_tx_descriptor *rx_desc, *tx_desc;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800384
Qipan Lid77ec5d2014-04-14 14:30:00 +0800385 sspi->dst_start = dma_map_single(&spi->dev,
386 sspi->rx, t->len, DMA_FROM_DEVICE);
Barry Songde39f5f2013-08-06 14:21:21 +0800387 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
Qipan Li692fb0f2013-08-25 21:42:50 +0800388 sspi->dst_start, t->len, DMA_DEV_TO_MEM,
Barry Songde39f5f2013-08-06 14:21:21 +0800389 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
390 rx_desc->callback = spi_sirfsoc_dma_fini_callback;
391 rx_desc->callback_param = &sspi->rx_done;
392
Qipan Lid77ec5d2014-04-14 14:30:00 +0800393 sspi->src_start = dma_map_single(&spi->dev,
394 (void *)sspi->tx, t->len, DMA_TO_DEVICE);
Barry Songde39f5f2013-08-06 14:21:21 +0800395 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
Qipan Li692fb0f2013-08-25 21:42:50 +0800396 sspi->src_start, t->len, DMA_MEM_TO_DEV,
Barry Songde39f5f2013-08-06 14:21:21 +0800397 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
398 tx_desc->callback = spi_sirfsoc_dma_fini_callback;
399 tx_desc->callback_param = &sspi->tx_done;
400
401 dmaengine_submit(tx_desc);
402 dmaengine_submit(rx_desc);
403 dma_async_issue_pending(sspi->tx_chan);
404 dma_async_issue_pending(sspi->rx_chan);
405 } else {
406 /* Send the first word to trigger the whole tx/rx process */
407 sspi->tx_word(sspi);
408
Qipan Lid77ec5d2014-04-14 14:30:00 +0800409 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN |
410 SIRFSOC_SPI_TX_UFLOW_INT_EN |
411 SIRFSOC_SPI_RXFIFO_THD_INT_EN |
412 SIRFSOC_SPI_TXFIFO_THD_INT_EN |
413 SIRFSOC_SPI_FRM_END_INT_EN |
414 SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
415 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN,
416 sspi->base + SIRFSOC_SPI_INT_EN);
Barry Songde39f5f2013-08-06 14:21:21 +0800417 }
418
Qipan Lid77ec5d2014-04-14 14:30:00 +0800419 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
420 sspi->base + SIRFSOC_SPI_TX_RX_EN);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800421
Barry Songde39f5f2013-08-06 14:21:21 +0800422 if (!IS_DMA_VALID(t)) { /* for PIO */
423 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
424 dev_err(&spi->dev, "transfer timeout\n");
425 } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800426 dev_err(&spi->dev, "transfer timeout\n");
Barry Songde39f5f2013-08-06 14:21:21 +0800427 dmaengine_terminate_all(sspi->rx_chan);
428 } else
Qipan Li692fb0f2013-08-25 21:42:50 +0800429 sspi->left_rx_word = 0;
Barry Songde39f5f2013-08-06 14:21:21 +0800430
431 /*
432 * we only wait tx-done event if transferring by DMA. for PIO,
433 * we get rx data by writing tx data, so if rx is done, tx has
434 * done earlier
435 */
436 if (IS_DMA_VALID(t)) {
437 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
438 dev_err(&spi->dev, "transfer timeout\n");
439 dmaengine_terminate_all(sspi->tx_chan);
440 }
441 }
442
443 if (IS_DMA_VALID(t)) {
Qipan Lid77ec5d2014-04-14 14:30:00 +0800444 dma_unmap_single(&spi->dev,
445 sspi->src_start, t->len, DMA_TO_DEVICE);
446 dma_unmap_single(&spi->dev,
447 sspi->dst_start, t->len, DMA_FROM_DEVICE);
Barry Songde39f5f2013-08-06 14:21:21 +0800448 }
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800449
450 /* TX, RX FIFO stop */
451 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
452 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
453 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
454 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
455
Qipan Li692fb0f2013-08-25 21:42:50 +0800456 return t->len - sspi->left_rx_word * sspi->word_width;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800457}
458
459static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
460{
461 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
462
463 if (sspi->chipselect[spi->chip_select] == 0) {
464 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800465 switch (value) {
466 case BITBANG_CS_ACTIVE:
467 if (spi->mode & SPI_CS_HIGH)
468 regval |= SIRFSOC_SPI_CS_IO_OUT;
469 else
470 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
471 break;
472 case BITBANG_CS_INACTIVE:
473 if (spi->mode & SPI_CS_HIGH)
474 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
475 else
476 regval |= SIRFSOC_SPI_CS_IO_OUT;
477 break;
478 }
479 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
480 } else {
481 int gpio = sspi->chipselect[spi->chip_select];
Qipan Li6ee8a2f2014-04-14 14:29:59 +0800482 switch (value) {
483 case BITBANG_CS_ACTIVE:
484 gpio_direction_output(gpio,
485 spi->mode & SPI_CS_HIGH ? 1 : 0);
486 break;
487 case BITBANG_CS_INACTIVE:
488 gpio_direction_output(gpio,
489 spi->mode & SPI_CS_HIGH ? 0 : 1);
490 break;
491 }
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800492 }
493}
494
495static int
496spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
497{
498 struct sirfsoc_spi *sspi;
499 u8 bits_per_word = 0;
500 int hz = 0;
501 u32 regval;
502 u32 txfifo_ctrl, rxfifo_ctrl;
503 u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
504
505 sspi = spi_master_get_devdata(spi->master);
506
Laxman Dewangan766ed702012-12-18 14:25:43 +0530507 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800508 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
509
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800510 regval = (sspi->ctrl_freq / (2 * hz)) - 1;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800511 if (regval > 0xFFFF || regval < 0) {
512 dev_err(&spi->dev, "Speed %d not supported\n", hz);
513 return -EINVAL;
514 }
515
516 switch (bits_per_word) {
517 case 8:
518 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
519 sspi->rx_word = spi_sirfsoc_rx_word_u8;
520 sspi->tx_word = spi_sirfsoc_tx_word_u8;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800521 break;
522 case 12:
523 case 16:
Qipan Lid77ec5d2014-04-14 14:30:00 +0800524 regval |= (bits_per_word == 12) ?
525 SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800526 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
527 sspi->rx_word = spi_sirfsoc_rx_word_u16;
528 sspi->tx_word = spi_sirfsoc_tx_word_u16;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800529 break;
530 case 32:
531 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
532 sspi->rx_word = spi_sirfsoc_rx_word_u32;
533 sspi->tx_word = spi_sirfsoc_tx_word_u32;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800534 break;
Arnd Bergmann804ae432013-06-03 15:24:53 +0200535 default:
536 BUG();
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800537 }
538
Axel Lin8c328a22014-01-15 17:07:43 +0800539 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
540 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
541 sspi->word_width;
542 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
543 sspi->word_width;
544
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800545 if (!(spi->mode & SPI_CS_HIGH))
546 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
547 if (!(spi->mode & SPI_LSB_FIRST))
548 regval |= SIRFSOC_SPI_TRAN_MSB;
549 if (spi->mode & SPI_CPOL)
550 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
551
552 /*
Qipan Lid77ec5d2014-04-14 14:30:00 +0800553 * Data should be driven at least 1/2 cycle before the fetch edge
554 * to make sure that data gets stable at the fetch edge.
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800555 */
556 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
557 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
558 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
559 else
560 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
561
562 writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
563 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
564 SIRFSOC_SPI_FIFO_HC(2),
565 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
566 writel(SIRFSOC_SPI_FIFO_SC(2) |
567 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
568 SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
569 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
570 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
571 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
572
Qipan Lieeb713952014-03-01 12:38:17 +0800573 if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
574 regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
575 SIRFSOC_SPI_CMD_MODE);
576 sspi->tx_by_cmd = true;
577 } else {
578 regval &= ~SIRFSOC_SPI_CMD_MODE;
579 sspi->tx_by_cmd = false;
580 }
Qipan Li625227a42014-04-14 14:29:58 +0800581 /*
582 * set spi controller in RISC chipselect mode, we are controlling CS by
583 * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE.
584 */
585 regval |= SIRFSOC_SPI_CS_IO_MODE;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800586 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
Barry Songde39f5f2013-08-06 14:21:21 +0800587
588 if (IS_DMA_VALID(t)) {
589 /* Enable DMA mode for RX, TX */
590 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
Qipan Lid77ec5d2014-04-14 14:30:00 +0800591 writel(SIRFSOC_SPI_RX_DMA_FLUSH,
592 sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
Barry Songde39f5f2013-08-06 14:21:21 +0800593 } else {
594 /* Enable IO mode for RX, TX */
Qipan Lid77ec5d2014-04-14 14:30:00 +0800595 writel(SIRFSOC_SPI_IO_MODE_SEL,
596 sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
597 writel(SIRFSOC_SPI_IO_MODE_SEL,
598 sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
Barry Songde39f5f2013-08-06 14:21:21 +0800599 }
600
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800601 return 0;
602}
603
604static int spi_sirfsoc_setup(struct spi_device *spi)
605{
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800606 if (!spi->max_speed_hz)
607 return -EINVAL;
608
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800609 return spi_sirfsoc_setup_transfer(spi, NULL);
610}
611
Grant Likelyfd4a3192012-12-07 16:57:14 +0000612static int spi_sirfsoc_probe(struct platform_device *pdev)
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800613{
614 struct sirfsoc_spi *sspi;
615 struct spi_master *master;
616 struct resource *mem_res;
617 int num_cs, cs_gpio, irq;
618 int i;
619 int ret;
620
621 ret = of_property_read_u32(pdev->dev.of_node,
622 "sirf,spi-num-chipselects", &num_cs);
623 if (ret < 0) {
624 dev_err(&pdev->dev, "Unable to get chip select number\n");
625 goto err_cs;
626 }
627
Qipan Lid77ec5d2014-04-14 14:30:00 +0800628 master = spi_alloc_master(&pdev->dev,
629 sizeof(*sspi) + sizeof(int) * num_cs);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800630 if (!master) {
631 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
632 return -ENOMEM;
633 }
634 platform_set_drvdata(pdev, master);
635 sspi = spi_master_get_devdata(master);
636
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800637 master->num_chipselect = num_cs;
638
639 for (i = 0; i < master->num_chipselect; i++) {
640 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
641 if (cs_gpio < 0) {
642 dev_err(&pdev->dev, "can't get cs gpio from DT\n");
643 ret = -ENODEV;
644 goto free_master;
645 }
646
647 sspi->chipselect[i] = cs_gpio;
648 if (cs_gpio == 0)
649 continue; /* use cs from spi controller */
650
651 ret = gpio_request(cs_gpio, DRIVER_NAME);
652 if (ret) {
653 while (i > 0) {
654 i--;
655 if (sspi->chipselect[i] > 0)
656 gpio_free(sspi->chipselect[i]);
657 }
658 dev_err(&pdev->dev, "fail to request cs gpios\n");
659 goto free_master;
660 }
661 }
662
Julia Lawall24797902013-08-14 11:11:29 +0200663 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Redingb0ee5602013-01-21 11:09:18 +0100664 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
665 if (IS_ERR(sspi->base)) {
666 ret = PTR_ERR(sspi->base);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800667 goto free_master;
668 }
669
670 irq = platform_get_irq(pdev, 0);
671 if (irq < 0) {
672 ret = -ENXIO;
673 goto free_master;
674 }
675 ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
676 DRIVER_NAME, sspi);
677 if (ret)
678 goto free_master;
679
Axel Lin94c69f72013-09-10 15:43:41 +0800680 sspi->bitbang.master = master;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800681 sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
682 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
683 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
684 sspi->bitbang.master->setup = spi_sirfsoc_setup;
685 master->bus_num = pdev->id;
Qipan Li94b1f0d2013-06-25 19:45:29 +0800686 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -0600687 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
688 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800689 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
690
Barry Songde39f5f2013-08-06 14:21:21 +0800691 /* request DMA channels */
Barry Songdd7243d2014-02-13 00:30:19 +0800692 sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
Barry Songde39f5f2013-08-06 14:21:21 +0800693 if (!sspi->rx_chan) {
694 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
Wei Yongjun6cca9e22013-08-23 08:33:39 +0800695 ret = -ENODEV;
Barry Songde39f5f2013-08-06 14:21:21 +0800696 goto free_master;
697 }
Barry Songdd7243d2014-02-13 00:30:19 +0800698 sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx");
Barry Songde39f5f2013-08-06 14:21:21 +0800699 if (!sspi->tx_chan) {
700 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
Wei Yongjun6cca9e22013-08-23 08:33:39 +0800701 ret = -ENODEV;
Barry Songde39f5f2013-08-06 14:21:21 +0800702 goto free_rx_dma;
703 }
704
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800705 sspi->clk = clk_get(&pdev->dev, NULL);
706 if (IS_ERR(sspi->clk)) {
Barry Songde39f5f2013-08-06 14:21:21 +0800707 ret = PTR_ERR(sspi->clk);
708 goto free_tx_dma;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800709 }
Barry Songe5118cd2012-12-26 10:48:33 +0800710 clk_prepare_enable(sspi->clk);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800711 sspi->ctrl_freq = clk_get_rate(sspi->clk);
712
Barry Songde39f5f2013-08-06 14:21:21 +0800713 init_completion(&sspi->rx_done);
714 init_completion(&sspi->tx_done);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800715
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800716 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
717 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
718 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
719 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
720 /* We are not using dummy delay between command and data */
721 writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
722
Barry Songde39f5f2013-08-06 14:21:21 +0800723 sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
Wei Yongjun6cca9e22013-08-23 08:33:39 +0800724 if (!sspi->dummypage) {
725 ret = -ENOMEM;
Barry Songde39f5f2013-08-06 14:21:21 +0800726 goto free_clk;
Wei Yongjun6cca9e22013-08-23 08:33:39 +0800727 }
Barry Songde39f5f2013-08-06 14:21:21 +0800728
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800729 ret = spi_bitbang_start(&sspi->bitbang);
730 if (ret)
Barry Songde39f5f2013-08-06 14:21:21 +0800731 goto free_dummypage;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800732
733 dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
734
735 return 0;
Barry Songde39f5f2013-08-06 14:21:21 +0800736free_dummypage:
737 kfree(sspi->dummypage);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800738free_clk:
Barry Songe5118cd2012-12-26 10:48:33 +0800739 clk_disable_unprepare(sspi->clk);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800740 clk_put(sspi->clk);
Barry Songde39f5f2013-08-06 14:21:21 +0800741free_tx_dma:
742 dma_release_channel(sspi->tx_chan);
743free_rx_dma:
744 dma_release_channel(sspi->rx_chan);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800745free_master:
746 spi_master_put(master);
747err_cs:
748 return ret;
749}
750
Grant Likelyfd4a3192012-12-07 16:57:14 +0000751static int spi_sirfsoc_remove(struct platform_device *pdev)
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800752{
753 struct spi_master *master;
754 struct sirfsoc_spi *sspi;
755 int i;
756
757 master = platform_get_drvdata(pdev);
758 sspi = spi_master_get_devdata(master);
759
760 spi_bitbang_stop(&sspi->bitbang);
761 for (i = 0; i < master->num_chipselect; i++) {
762 if (sspi->chipselect[i] > 0)
763 gpio_free(sspi->chipselect[i]);
764 }
Barry Songde39f5f2013-08-06 14:21:21 +0800765 kfree(sspi->dummypage);
Barry Songe5118cd2012-12-26 10:48:33 +0800766 clk_disable_unprepare(sspi->clk);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800767 clk_put(sspi->clk);
Barry Songde39f5f2013-08-06 14:21:21 +0800768 dma_release_channel(sspi->rx_chan);
769 dma_release_channel(sspi->tx_chan);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800770 spi_master_put(master);
771 return 0;
772}
773
Qipan Lifacffed2014-02-13 00:30:20 +0800774#ifdef CONFIG_PM_SLEEP
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800775static int spi_sirfsoc_suspend(struct device *dev)
776{
Axel Lina12163942013-08-09 15:35:16 +0800777 struct spi_master *master = dev_get_drvdata(dev);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800778 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
Axel Lina82ba3a2014-03-05 15:19:09 +0800779 int ret;
780
781 ret = spi_master_suspend(master);
782 if (ret)
783 return ret;
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800784
785 clk_disable(sspi->clk);
786 return 0;
787}
788
789static int spi_sirfsoc_resume(struct device *dev)
790{
Axel Lina12163942013-08-09 15:35:16 +0800791 struct spi_master *master = dev_get_drvdata(dev);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800792 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
793
794 clk_enable(sspi->clk);
795 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
796 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
797 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
798 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
799
Axel Lina82ba3a2014-03-05 15:19:09 +0800800 return spi_master_resume(master);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800801}
Qipan Lifacffed2014-02-13 00:30:20 +0800802#endif
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800803
Jingoo Han71aa2e32014-02-26 10:32:48 +0900804static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
805 spi_sirfsoc_resume);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800806
807static const struct of_device_id spi_sirfsoc_of_match[] = {
808 { .compatible = "sirf,prima2-spi", },
Barry Songf3b8a8e2012-12-26 10:48:34 +0800809 { .compatible = "sirf,marco-spi", },
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800810 {}
811};
Arnd Bergmann3af4ed72013-04-23 18:30:41 +0200812MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800813
814static struct platform_driver spi_sirfsoc_driver = {
815 .driver = {
816 .name = DRIVER_NAME,
817 .owner = THIS_MODULE,
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800818 .pm = &spi_sirfsoc_pm_ops,
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800819 .of_match_table = spi_sirfsoc_of_match,
820 },
821 .probe = spi_sirfsoc_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000822 .remove = spi_sirfsoc_remove,
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800823};
824module_platform_driver(spi_sirfsoc_driver);
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800825MODULE_DESCRIPTION("SiRF SoC SPI master driver");
Qipan Lid77ec5d2014-04-14 14:30:00 +0800826MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
827MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
Zhiwu Song1cc2df92012-02-13 17:45:38 +0800828MODULE_LICENSE("GPL v2");