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David J. Choid0507002010-04-29 06:12:41 +00001/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
David J. Choi7ab59dc2013-01-23 14:05:15 +00008 * Copyright (c) 2010-2013 Micrel, Inc.
David J. Choid0507002010-04-29 06:12:41 +00009 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
David J. Choi7ab59dc2013-01-23 14:05:15 +000015 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
David J. Choid0507002010-04-29 06:12:41 +000022 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
Baruch Siachd606ef32011-02-14 02:05:33 +000027#include <linux/micrel_phy.h>
Sean Cross954c3962013-08-21 01:46:12 +000028#include <linux/of.h>
Sascha Hauer1fadee02014-10-10 09:48:05 +020029#include <linux/clk.h>
David J. Choid0507002010-04-29 06:12:41 +000030
Marek Vasut212ea992012-09-23 16:58:49 +000031/* Operation Mode Strap Override */
32#define MII_KSZPHY_OMSO 0x16
Johan Hovold00aee092014-11-11 20:00:09 +010033#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
34#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
35#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
Marek Vasut212ea992012-09-23 16:58:49 +000036
Choi, David51f932c2010-06-28 15:23:41 +000037/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
Johan Hovold00aee092014-11-11 20:00:09 +010039#define KSZPHY_INTCS_JABBER BIT(15)
40#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
41#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
42#define KSZPHY_INTCS_PARELLEL BIT(12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
44#define KSZPHY_INTCS_LINK_DOWN BIT(10)
45#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
46#define KSZPHY_INTCS_LINK_UP BIT(8)
Choi, David51f932c2010-06-28 15:23:41 +000047#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
Johan Hovold5a167782014-11-11 20:00:14 +010050/* PHY Control 1 */
51#define MII_KSZPHY_CTRL_1 0x1e
52
53/* PHY Control 2 / PHY Control (if no PHY Control 1) */
54#define MII_KSZPHY_CTRL_2 0x1f
55#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
Choi, David51f932c2010-06-28 15:23:41 +000056/* bitmap of PHY register to set interrupt mode */
Johan Hovold00aee092014-11-11 20:00:09 +010057#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
Johan Hovold63f44b22014-11-19 12:59:18 +010058#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
Choi, David51f932c2010-06-28 15:23:41 +000059
Sean Cross954c3962013-08-21 01:46:12 +000060/* Write/read to/from extended registers */
61#define MII_KSZPHY_EXTREG 0x0b
62#define KSZPHY_EXTREG_WRITE 0x8000
63
64#define MII_KSZPHY_EXTREG_WRITE 0x0c
65#define MII_KSZPHY_EXTREG_READ 0x0d
66
67/* Extended registers */
68#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
69#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
70#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
71
72#define PS_TO_REG 200
73
Johan Hovolde6a423a2014-11-19 12:59:15 +010074struct kszphy_type {
75 u32 led_mode_reg;
Johan Hovoldc6f95752014-11-19 12:59:22 +010076 u16 interrupt_level_mask;
Johan Hovold0f959032014-11-19 12:59:17 +010077 bool has_broadcast_disable;
Johan Hovold63f44b22014-11-19 12:59:18 +010078 bool has_rmii_ref_clk_sel;
Johan Hovolde6a423a2014-11-19 12:59:15 +010079};
80
81struct kszphy_priv {
82 const struct kszphy_type *type;
Johan Hovolde7a792e2014-11-19 12:59:16 +010083 int led_mode;
Johan Hovold63f44b22014-11-19 12:59:18 +010084 bool rmii_ref_clk_sel;
85 bool rmii_ref_clk_sel_val;
Johan Hovolde6a423a2014-11-19 12:59:15 +010086};
87
88static const struct kszphy_type ksz8021_type = {
89 .led_mode_reg = MII_KSZPHY_CTRL_2,
Johan Hovold63f44b22014-11-19 12:59:18 +010090 .has_rmii_ref_clk_sel = true,
Johan Hovolde6a423a2014-11-19 12:59:15 +010091};
92
93static const struct kszphy_type ksz8041_type = {
94 .led_mode_reg = MII_KSZPHY_CTRL_1,
95};
96
97static const struct kszphy_type ksz8051_type = {
98 .led_mode_reg = MII_KSZPHY_CTRL_2,
99};
100
101static const struct kszphy_type ksz8081_type = {
102 .led_mode_reg = MII_KSZPHY_CTRL_2,
Johan Hovold0f959032014-11-19 12:59:17 +0100103 .has_broadcast_disable = true,
Johan Hovold86dc1342014-11-19 12:59:19 +0100104 .has_rmii_ref_clk_sel = true,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100105};
106
Johan Hovoldc6f95752014-11-19 12:59:22 +0100107static const struct kszphy_type ks8737_type = {
108 .interrupt_level_mask = BIT(14),
109};
110
111static const struct kszphy_type ksz9021_type = {
112 .interrupt_level_mask = BIT(14),
113};
114
Sean Cross954c3962013-08-21 01:46:12 +0000115static int kszphy_extended_write(struct phy_device *phydev,
Florian Fainelli756b5082013-12-17 21:38:11 -0800116 u32 regnum, u16 val)
Sean Cross954c3962013-08-21 01:46:12 +0000117{
118 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
119 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
120}
121
122static int kszphy_extended_read(struct phy_device *phydev,
Florian Fainelli756b5082013-12-17 21:38:11 -0800123 u32 regnum)
Sean Cross954c3962013-08-21 01:46:12 +0000124{
125 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
126 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
127}
128
Choi, David51f932c2010-06-28 15:23:41 +0000129static int kszphy_ack_interrupt(struct phy_device *phydev)
130{
131 /* bit[7..0] int status, which is a read and clear register. */
132 int rc;
133
134 rc = phy_read(phydev, MII_KSZPHY_INTCS);
135
136 return (rc < 0) ? rc : 0;
137}
138
Choi, David51f932c2010-06-28 15:23:41 +0000139static int kszphy_config_intr(struct phy_device *phydev)
140{
Johan Hovoldc6f95752014-11-19 12:59:22 +0100141 const struct kszphy_type *type = phydev->drv->driver_data;
142 int temp;
143 u16 mask;
144
145 if (type && type->interrupt_level_mask)
146 mask = type->interrupt_level_mask;
147 else
148 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
Choi, David51f932c2010-06-28 15:23:41 +0000149
150 /* set the interrupt pin active low */
151 temp = phy_read(phydev, MII_KSZPHY_CTRL);
Johan Hovold5bb8fc02014-11-11 20:00:08 +0100152 if (temp < 0)
153 return temp;
Johan Hovoldc6f95752014-11-19 12:59:22 +0100154 temp &= ~mask;
Choi, David51f932c2010-06-28 15:23:41 +0000155 phy_write(phydev, MII_KSZPHY_CTRL, temp);
Choi, David51f932c2010-06-28 15:23:41 +0000156
Johan Hovoldc6f95752014-11-19 12:59:22 +0100157 /* enable / disable interrupts */
158 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
159 temp = KSZPHY_INTCS_ALL;
160 else
161 temp = 0;
Choi, David51f932c2010-06-28 15:23:41 +0000162
Johan Hovoldc6f95752014-11-19 12:59:22 +0100163 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
Choi, David51f932c2010-06-28 15:23:41 +0000164}
David J. Choid0507002010-04-29 06:12:41 +0000165
Johan Hovold63f44b22014-11-19 12:59:18 +0100166static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
167{
168 int ctrl;
169
170 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
171 if (ctrl < 0)
172 return ctrl;
173
174 if (val)
175 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
176 else
177 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
178
179 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
180}
181
Johan Hovolde7a792e2014-11-19 12:59:16 +0100182static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
Ben Dooks20d84352014-02-26 11:48:00 +0000183{
Johan Hovold5a167782014-11-11 20:00:14 +0100184 int rc, temp, shift;
Johan Hovold86205462014-11-11 20:00:12 +0100185
Johan Hovold5a167782014-11-11 20:00:14 +0100186 switch (reg) {
187 case MII_KSZPHY_CTRL_1:
188 shift = 14;
189 break;
190 case MII_KSZPHY_CTRL_2:
191 shift = 4;
192 break;
193 default:
194 return -EINVAL;
195 }
196
Ben Dooks20d84352014-02-26 11:48:00 +0000197 temp = phy_read(phydev, reg);
Johan Hovoldb7035862014-11-11 20:00:13 +0100198 if (temp < 0) {
199 rc = temp;
200 goto out;
201 }
Ben Dooks20d84352014-02-26 11:48:00 +0000202
Sergei Shtylyov28bdc492014-03-19 02:58:16 +0300203 temp &= ~(3 << shift);
Ben Dooks20d84352014-02-26 11:48:00 +0000204 temp |= val << shift;
205 rc = phy_write(phydev, reg, temp);
Johan Hovoldb7035862014-11-11 20:00:13 +0100206out:
207 if (rc < 0)
208 dev_err(&phydev->dev, "failed to set led mode\n");
Ben Dooks20d84352014-02-26 11:48:00 +0000209
Johan Hovoldb7035862014-11-11 20:00:13 +0100210 return rc;
Ben Dooks20d84352014-02-26 11:48:00 +0000211}
212
Johan Hovoldbde15122014-11-11 20:00:10 +0100213/* Disable PHY address 0 as the broadcast address, so that it can be used as a
214 * unique (non-broadcast) address on a shared bus.
215 */
216static int kszphy_broadcast_disable(struct phy_device *phydev)
217{
218 int ret;
219
220 ret = phy_read(phydev, MII_KSZPHY_OMSO);
221 if (ret < 0)
222 goto out;
223
224 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
225out:
226 if (ret)
227 dev_err(&phydev->dev, "failed to disable broadcast address\n");
228
229 return ret;
230}
231
David J. Choid0507002010-04-29 06:12:41 +0000232static int kszphy_config_init(struct phy_device *phydev)
233{
Johan Hovolde6a423a2014-11-19 12:59:15 +0100234 struct kszphy_priv *priv = phydev->priv;
235 const struct kszphy_type *type;
Johan Hovold63f44b22014-11-19 12:59:18 +0100236 int ret;
David J. Choid0507002010-04-29 06:12:41 +0000237
Johan Hovolde6a423a2014-11-19 12:59:15 +0100238 if (!priv)
239 return 0;
240
241 type = priv->type;
242
Johan Hovold0f959032014-11-19 12:59:17 +0100243 if (type->has_broadcast_disable)
244 kszphy_broadcast_disable(phydev);
245
Johan Hovold63f44b22014-11-19 12:59:18 +0100246 if (priv->rmii_ref_clk_sel) {
247 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
248 if (ret) {
249 dev_err(&phydev->dev, "failed to set rmii reference clock\n");
250 return ret;
251 }
252 }
253
Johan Hovolde7a792e2014-11-19 12:59:16 +0100254 if (priv->led_mode >= 0)
255 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
Johan Hovolde6a423a2014-11-19 12:59:15 +0100256
257 return 0;
Ben Dooks20d84352014-02-26 11:48:00 +0000258}
259
Marek Vasut212ea992012-09-23 16:58:49 +0000260static int ksz8021_config_init(struct phy_device *phydev)
261{
Ben Dooks20d84352014-02-26 11:48:00 +0000262 int rc;
263
Johan Hovold63f44b22014-11-19 12:59:18 +0100264 rc = kszphy_config_init(phydev);
265 if (rc)
Bruno Thomsenb838b4a2014-10-09 16:48:14 +0200266 return rc;
Johan Hovoldbde15122014-11-11 20:00:10 +0100267
268 rc = kszphy_broadcast_disable(phydev);
269
Hector Palaciosb6bb4dfc2013-03-10 22:50:03 +0000270 return rc < 0 ? rc : 0;
Marek Vasut212ea992012-09-23 16:58:49 +0000271}
272
Sean Cross954c3962013-08-21 01:46:12 +0000273static int ksz9021_load_values_from_of(struct phy_device *phydev,
274 struct device_node *of_node, u16 reg,
275 char *field1, char *field2,
276 char *field3, char *field4)
277{
278 int val1 = -1;
279 int val2 = -2;
280 int val3 = -3;
281 int val4 = -4;
282 int newval;
283 int matches = 0;
284
285 if (!of_property_read_u32(of_node, field1, &val1))
286 matches++;
287
288 if (!of_property_read_u32(of_node, field2, &val2))
289 matches++;
290
291 if (!of_property_read_u32(of_node, field3, &val3))
292 matches++;
293
294 if (!of_property_read_u32(of_node, field4, &val4))
295 matches++;
296
297 if (!matches)
298 return 0;
299
300 if (matches < 4)
301 newval = kszphy_extended_read(phydev, reg);
302 else
303 newval = 0;
304
305 if (val1 != -1)
306 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
307
Hubert Chaumette6a119742014-04-22 15:01:04 +0200308 if (val2 != -2)
Sean Cross954c3962013-08-21 01:46:12 +0000309 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
310
Hubert Chaumette6a119742014-04-22 15:01:04 +0200311 if (val3 != -3)
Sean Cross954c3962013-08-21 01:46:12 +0000312 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
313
Hubert Chaumette6a119742014-04-22 15:01:04 +0200314 if (val4 != -4)
Sean Cross954c3962013-08-21 01:46:12 +0000315 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
316
317 return kszphy_extended_write(phydev, reg, newval);
318}
319
320static int ksz9021_config_init(struct phy_device *phydev)
321{
322 struct device *dev = &phydev->dev;
323 struct device_node *of_node = dev->of_node;
324
325 if (!of_node && dev->parent->of_node)
326 of_node = dev->parent->of_node;
327
328 if (of_node) {
329 ksz9021_load_values_from_of(phydev, of_node,
330 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
331 "txen-skew-ps", "txc-skew-ps",
332 "rxdv-skew-ps", "rxc-skew-ps");
333 ksz9021_load_values_from_of(phydev, of_node,
334 MII_KSZPHY_RX_DATA_PAD_SKEW,
335 "rxd0-skew-ps", "rxd1-skew-ps",
336 "rxd2-skew-ps", "rxd3-skew-ps");
337 ksz9021_load_values_from_of(phydev, of_node,
338 MII_KSZPHY_TX_DATA_PAD_SKEW,
339 "txd0-skew-ps", "txd1-skew-ps",
340 "txd2-skew-ps", "txd3-skew-ps");
341 }
342 return 0;
343}
344
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200345#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
346#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
347#define OP_DATA 1
348#define KSZ9031_PS_TO_REG 60
349
350/* Extended registers */
351#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
352#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
353#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
354#define MII_KSZ9031RN_CLK_PAD_SKEW 8
355
356static int ksz9031_extended_write(struct phy_device *phydev,
357 u8 mode, u32 dev_addr, u32 regnum, u16 val)
358{
359 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
360 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
361 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
362 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
363}
364
365static int ksz9031_extended_read(struct phy_device *phydev,
366 u8 mode, u32 dev_addr, u32 regnum)
367{
368 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
369 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
370 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
371 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
372}
373
374static int ksz9031_of_load_skew_values(struct phy_device *phydev,
375 struct device_node *of_node,
376 u16 reg, size_t field_sz,
377 char *field[], u8 numfields)
378{
379 int val[4] = {-1, -2, -3, -4};
380 int matches = 0;
381 u16 mask;
382 u16 maxval;
383 u16 newval;
384 int i;
385
386 for (i = 0; i < numfields; i++)
387 if (!of_property_read_u32(of_node, field[i], val + i))
388 matches++;
389
390 if (!matches)
391 return 0;
392
393 if (matches < numfields)
394 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
395 else
396 newval = 0;
397
398 maxval = (field_sz == 4) ? 0xf : 0x1f;
399 for (i = 0; i < numfields; i++)
400 if (val[i] != -(i + 1)) {
401 mask = 0xffff;
402 mask ^= maxval << (field_sz * i);
403 newval = (newval & mask) |
404 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
405 << (field_sz * i));
406 }
407
408 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
409}
410
411static int ksz9031_config_init(struct phy_device *phydev)
412{
413 struct device *dev = &phydev->dev;
414 struct device_node *of_node = dev->of_node;
415 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
416 char *rx_data_skews[4] = {
417 "rxd0-skew-ps", "rxd1-skew-ps",
418 "rxd2-skew-ps", "rxd3-skew-ps"
419 };
420 char *tx_data_skews[4] = {
421 "txd0-skew-ps", "txd1-skew-ps",
422 "txd2-skew-ps", "txd3-skew-ps"
423 };
424 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
425
426 if (!of_node && dev->parent->of_node)
427 of_node = dev->parent->of_node;
428
429 if (of_node) {
430 ksz9031_of_load_skew_values(phydev, of_node,
431 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
432 clk_skews, 2);
433
434 ksz9031_of_load_skew_values(phydev, of_node,
435 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
436 control_skews, 2);
437
438 ksz9031_of_load_skew_values(phydev, of_node,
439 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
440 rx_data_skews, 4);
441
442 ksz9031_of_load_skew_values(phydev, of_node,
443 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
444 tx_data_skews, 4);
445 }
446 return 0;
447}
448
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000449#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
Johan Hovold00aee092014-11-11 20:00:09 +0100450#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
451#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
Jingoo Han32d73b12013-08-06 17:29:35 +0900452static int ksz8873mll_read_status(struct phy_device *phydev)
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000453{
454 int regval;
455
456 /* dummy read */
457 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
458
459 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
460
461 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
462 phydev->duplex = DUPLEX_HALF;
463 else
464 phydev->duplex = DUPLEX_FULL;
465
466 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
467 phydev->speed = SPEED_10;
468 else
469 phydev->speed = SPEED_100;
470
471 phydev->link = 1;
472 phydev->pause = phydev->asym_pause = 0;
473
474 return 0;
475}
476
477static int ksz8873mll_config_aneg(struct phy_device *phydev)
478{
479 return 0;
480}
481
Vince Bridgers19936942014-07-29 15:19:58 -0500482/* This routine returns -1 as an indication to the caller that the
483 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
484 * MMD extended PHY registers.
485 */
486static int
487ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
488 int regnum)
489{
490 return -1;
491}
492
493/* This routine does nothing since the Micrel ksz9021 does not support
494 * standard IEEE MMD extended PHY registers.
495 */
496static void
497ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
498 int regnum, u32 val)
499{
500}
501
Johan Hovolde6a423a2014-11-19 12:59:15 +0100502static int kszphy_probe(struct phy_device *phydev)
503{
504 const struct kszphy_type *type = phydev->drv->driver_data;
Johan Hovolde7a792e2014-11-19 12:59:16 +0100505 struct device_node *np = phydev->dev.of_node;
Johan Hovolde6a423a2014-11-19 12:59:15 +0100506 struct kszphy_priv *priv;
Johan Hovold63f44b22014-11-19 12:59:18 +0100507 struct clk *clk;
Johan Hovolde7a792e2014-11-19 12:59:16 +0100508 int ret;
Johan Hovolde6a423a2014-11-19 12:59:15 +0100509
510 priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL);
511 if (!priv)
512 return -ENOMEM;
513
514 phydev->priv = priv;
515
516 priv->type = type;
517
Johan Hovolde7a792e2014-11-19 12:59:16 +0100518 if (type->led_mode_reg) {
519 ret = of_property_read_u32(np, "micrel,led-mode",
520 &priv->led_mode);
521 if (ret)
522 priv->led_mode = -1;
523
524 if (priv->led_mode > 3) {
525 dev_err(&phydev->dev, "invalid led mode: 0x%02x\n",
526 priv->led_mode);
527 priv->led_mode = -1;
528 }
529 } else {
530 priv->led_mode = -1;
531 }
532
Sascha Hauer1fadee02014-10-10 09:48:05 +0200533 clk = devm_clk_get(&phydev->dev, "rmii-ref");
534 if (!IS_ERR(clk)) {
535 unsigned long rate = clk_get_rate(clk);
Johan Hovold86dc1342014-11-19 12:59:19 +0100536 bool rmii_ref_clk_sel_25_mhz;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200537
Johan Hovold63f44b22014-11-19 12:59:18 +0100538 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
Johan Hovold86dc1342014-11-19 12:59:19 +0100539 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
540 "micrel,rmii-reference-clock-select-25-mhz");
Johan Hovold63f44b22014-11-19 12:59:18 +0100541
Sascha Hauer1fadee02014-10-10 09:48:05 +0200542 if (rate > 24500000 && rate < 25500000) {
Johan Hovold86dc1342014-11-19 12:59:19 +0100543 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200544 } else if (rate > 49500000 && rate < 50500000) {
Johan Hovold86dc1342014-11-19 12:59:19 +0100545 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200546 } else {
547 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
548 return -EINVAL;
549 }
550 }
551
Johan Hovold63f44b22014-11-19 12:59:18 +0100552 /* Support legacy board-file configuration */
553 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
554 priv->rmii_ref_clk_sel = true;
555 priv->rmii_ref_clk_sel_val = true;
556 }
557
558 return 0;
Sascha Hauer1fadee02014-10-10 09:48:05 +0200559}
560
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000561static struct phy_driver ksphy_driver[] = {
562{
Choi, David51f932c2010-06-28 15:23:41 +0000563 .phy_id = PHY_ID_KS8737,
David J. Choid0507002010-04-29 06:12:41 +0000564 .phy_id_mask = 0x00fffff0,
Choi, David51f932c2010-06-28 15:23:41 +0000565 .name = "Micrel KS8737",
566 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
567 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100568 .driver_data = &ks8737_type,
David J. Choid0507002010-04-29 06:12:41 +0000569 .config_init = kszphy_config_init,
570 .config_aneg = genphy_config_aneg,
571 .read_status = genphy_read_status,
Choi, David51f932c2010-06-28 15:23:41 +0000572 .ack_interrupt = kszphy_ack_interrupt,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100573 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200574 .suspend = genphy_suspend,
575 .resume = genphy_resume,
David J. Choid0507002010-04-29 06:12:41 +0000576 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000577}, {
Marek Vasut212ea992012-09-23 16:58:49 +0000578 .phy_id = PHY_ID_KSZ8021,
579 .phy_id_mask = 0x00ffffff,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000580 .name = "Micrel KSZ8021 or KSZ8031",
Marek Vasut212ea992012-09-23 16:58:49 +0000581 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
582 SUPPORTED_Asym_Pause),
583 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100584 .driver_data = &ksz8021_type,
Johan Hovold63f44b22014-11-19 12:59:18 +0100585 .probe = kszphy_probe,
Marek Vasut212ea992012-09-23 16:58:49 +0000586 .config_init = ksz8021_config_init,
587 .config_aneg = genphy_config_aneg,
588 .read_status = genphy_read_status,
589 .ack_interrupt = kszphy_ack_interrupt,
590 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200591 .suspend = genphy_suspend,
592 .resume = genphy_resume,
Marek Vasut212ea992012-09-23 16:58:49 +0000593 .driver = { .owner = THIS_MODULE,},
594}, {
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000595 .phy_id = PHY_ID_KSZ8031,
596 .phy_id_mask = 0x00ffffff,
597 .name = "Micrel KSZ8031",
598 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
599 SUPPORTED_Asym_Pause),
600 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100601 .driver_data = &ksz8021_type,
Johan Hovold63f44b22014-11-19 12:59:18 +0100602 .probe = kszphy_probe,
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000603 .config_init = ksz8021_config_init,
604 .config_aneg = genphy_config_aneg,
605 .read_status = genphy_read_status,
606 .ack_interrupt = kszphy_ack_interrupt,
607 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200608 .suspend = genphy_suspend,
609 .resume = genphy_resume,
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000610 .driver = { .owner = THIS_MODULE,},
611}, {
Marek Vasut510d5732012-09-23 16:58:50 +0000612 .phy_id = PHY_ID_KSZ8041,
David J. Choid0507002010-04-29 06:12:41 +0000613 .phy_id_mask = 0x00fffff0,
Marek Vasut510d5732012-09-23 16:58:50 +0000614 .name = "Micrel KSZ8041",
Choi, David51f932c2010-06-28 15:23:41 +0000615 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
616 | SUPPORTED_Asym_Pause),
617 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100618 .driver_data = &ksz8041_type,
619 .probe = kszphy_probe,
620 .config_init = kszphy_config_init,
David J. Choid0507002010-04-29 06:12:41 +0000621 .config_aneg = genphy_config_aneg,
622 .read_status = genphy_read_status,
Choi, David51f932c2010-06-28 15:23:41 +0000623 .ack_interrupt = kszphy_ack_interrupt,
624 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200625 .suspend = genphy_suspend,
626 .resume = genphy_resume,
Choi, David51f932c2010-06-28 15:23:41 +0000627 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000628}, {
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300629 .phy_id = PHY_ID_KSZ8041RNLI,
630 .phy_id_mask = 0x00fffff0,
631 .name = "Micrel KSZ8041RNLI",
632 .features = PHY_BASIC_FEATURES |
633 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
634 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100635 .driver_data = &ksz8041_type,
636 .probe = kszphy_probe,
637 .config_init = kszphy_config_init,
Sergei Shtylyov4bd7b512013-12-10 02:20:41 +0300638 .config_aneg = genphy_config_aneg,
639 .read_status = genphy_read_status,
640 .ack_interrupt = kszphy_ack_interrupt,
641 .config_intr = kszphy_config_intr,
642 .suspend = genphy_suspend,
643 .resume = genphy_resume,
644 .driver = { .owner = THIS_MODULE,},
645}, {
Marek Vasut510d5732012-09-23 16:58:50 +0000646 .phy_id = PHY_ID_KSZ8051,
Choi, David51f932c2010-06-28 15:23:41 +0000647 .phy_id_mask = 0x00fffff0,
Marek Vasut510d5732012-09-23 16:58:50 +0000648 .name = "Micrel KSZ8051",
Choi, David51f932c2010-06-28 15:23:41 +0000649 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
650 | SUPPORTED_Asym_Pause),
651 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100652 .driver_data = &ksz8051_type,
653 .probe = kszphy_probe,
Johan Hovold63f44b22014-11-19 12:59:18 +0100654 .config_init = kszphy_config_init,
Choi, David51f932c2010-06-28 15:23:41 +0000655 .config_aneg = genphy_config_aneg,
656 .read_status = genphy_read_status,
657 .ack_interrupt = kszphy_ack_interrupt,
658 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200659 .suspend = genphy_suspend,
660 .resume = genphy_resume,
Choi, David51f932c2010-06-28 15:23:41 +0000661 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000662}, {
Marek Vasut510d5732012-09-23 16:58:50 +0000663 .phy_id = PHY_ID_KSZ8001,
664 .name = "Micrel KSZ8001 or KS8721",
Jason Wang48d7d0a2012-06-17 22:52:09 +0000665 .phy_id_mask = 0x00ffffff,
Choi, David51f932c2010-06-28 15:23:41 +0000666 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
667 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100668 .driver_data = &ksz8041_type,
669 .probe = kszphy_probe,
670 .config_init = kszphy_config_init,
Choi, David51f932c2010-06-28 15:23:41 +0000671 .config_aneg = genphy_config_aneg,
672 .read_status = genphy_read_status,
673 .ack_interrupt = kszphy_ack_interrupt,
674 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200675 .suspend = genphy_suspend,
676 .resume = genphy_resume,
David J. Choid0507002010-04-29 06:12:41 +0000677 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000678}, {
David J. Choi7ab59dc2013-01-23 14:05:15 +0000679 .phy_id = PHY_ID_KSZ8081,
680 .name = "Micrel KSZ8081 or KSZ8091",
681 .phy_id_mask = 0x00fffff0,
682 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
683 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovolde6a423a2014-11-19 12:59:15 +0100684 .driver_data = &ksz8081_type,
685 .probe = kszphy_probe,
Johan Hovold0f959032014-11-19 12:59:17 +0100686 .config_init = kszphy_config_init,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000687 .config_aneg = genphy_config_aneg,
688 .read_status = genphy_read_status,
689 .ack_interrupt = kszphy_ack_interrupt,
690 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200691 .suspend = genphy_suspend,
692 .resume = genphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000693 .driver = { .owner = THIS_MODULE,},
694}, {
695 .phy_id = PHY_ID_KSZ8061,
696 .name = "Micrel KSZ8061",
697 .phy_id_mask = 0x00fffff0,
698 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
699 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
700 .config_init = kszphy_config_init,
701 .config_aneg = genphy_config_aneg,
702 .read_status = genphy_read_status,
703 .ack_interrupt = kszphy_ack_interrupt,
704 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200705 .suspend = genphy_suspend,
706 .resume = genphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000707 .driver = { .owner = THIS_MODULE,},
708}, {
David J. Choid0507002010-04-29 06:12:41 +0000709 .phy_id = PHY_ID_KSZ9021,
Jason Wang48d7d0a2012-06-17 22:52:09 +0000710 .phy_id_mask = 0x000ffffe,
David J. Choid0507002010-04-29 06:12:41 +0000711 .name = "Micrel KSZ9021 Gigabit PHY",
Vlastimil Kosar32fcafb2013-02-28 08:45:22 +0000712 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
Choi, David51f932c2010-06-28 15:23:41 +0000713 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100714 .driver_data = &ksz9021_type,
Sean Cross954c3962013-08-21 01:46:12 +0000715 .config_init = ksz9021_config_init,
David J. Choid0507002010-04-29 06:12:41 +0000716 .config_aneg = genphy_config_aneg,
717 .read_status = genphy_read_status,
Choi, David51f932c2010-06-28 15:23:41 +0000718 .ack_interrupt = kszphy_ack_interrupt,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100719 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200720 .suspend = genphy_suspend,
721 .resume = genphy_resume,
Vince Bridgers19936942014-07-29 15:19:58 -0500722 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
723 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
David J. Choid0507002010-04-29 06:12:41 +0000724 .driver = { .owner = THIS_MODULE, },
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000725}, {
David J. Choi7ab59dc2013-01-23 14:05:15 +0000726 .phy_id = PHY_ID_KSZ9031,
727 .phy_id_mask = 0x00fffff0,
728 .name = "Micrel KSZ9031 Gigabit PHY",
Mike Looijmans95e8b102014-09-15 12:06:33 +0200729 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
David J. Choi7ab59dc2013-01-23 14:05:15 +0000730 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100731 .driver_data = &ksz9021_type,
Hubert Chaumette6e4b8272014-05-06 09:40:17 +0200732 .config_init = ksz9031_config_init,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000733 .config_aneg = genphy_config_aneg,
734 .read_status = genphy_read_status,
735 .ack_interrupt = kszphy_ack_interrupt,
Johan Hovoldc6f95752014-11-19 12:59:22 +0100736 .config_intr = kszphy_config_intr,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200737 .suspend = genphy_suspend,
738 .resume = genphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000739 .driver = { .owner = THIS_MODULE, },
740}, {
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000741 .phy_id = PHY_ID_KSZ8873MLL,
742 .phy_id_mask = 0x00fffff0,
743 .name = "Micrel KSZ8873MLL Switch",
744 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
745 .flags = PHY_HAS_MAGICANEG,
746 .config_init = kszphy_config_init,
747 .config_aneg = ksz8873mll_config_aneg,
748 .read_status = ksz8873mll_read_status,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200749 .suspend = genphy_suspend,
750 .resume = genphy_resume,
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000751 .driver = { .owner = THIS_MODULE, },
David J. Choi7ab59dc2013-01-23 14:05:15 +0000752}, {
753 .phy_id = PHY_ID_KSZ886X,
754 .phy_id_mask = 0x00fffff0,
755 .name = "Micrel KSZ886X Switch",
756 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
757 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
758 .config_init = kszphy_config_init,
759 .config_aneg = genphy_config_aneg,
760 .read_status = genphy_read_status,
Patrice Vilchez1a5465f2013-09-19 19:40:48 +0200761 .suspend = genphy_suspend,
762 .resume = genphy_resume,
David J. Choi7ab59dc2013-01-23 14:05:15 +0000763 .driver = { .owner = THIS_MODULE, },
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000764} };
David J. Choid0507002010-04-29 06:12:41 +0000765
Johan Hovold50fd7152014-11-11 19:45:59 +0100766module_phy_driver(ksphy_driver);
David J. Choid0507002010-04-29 06:12:41 +0000767
768MODULE_DESCRIPTION("Micrel PHY driver");
769MODULE_AUTHOR("David J. Choi");
770MODULE_LICENSE("GPL");
David S. Miller52a60ed2010-05-03 15:48:29 -0700771
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000772static struct mdio_device_id __maybe_unused micrel_tbl[] = {
Jason Wang48d7d0a2012-06-17 22:52:09 +0000773 { PHY_ID_KSZ9021, 0x000ffffe },
David J. Choi7ab59dc2013-01-23 14:05:15 +0000774 { PHY_ID_KSZ9031, 0x00fffff0 },
Marek Vasut510d5732012-09-23 16:58:50 +0000775 { PHY_ID_KSZ8001, 0x00ffffff },
Choi, David51f932c2010-06-28 15:23:41 +0000776 { PHY_ID_KS8737, 0x00fffff0 },
Marek Vasut212ea992012-09-23 16:58:49 +0000777 { PHY_ID_KSZ8021, 0x00ffffff },
Hector Palaciosb818d1a2013-03-10 22:50:02 +0000778 { PHY_ID_KSZ8031, 0x00ffffff },
Marek Vasut510d5732012-09-23 16:58:50 +0000779 { PHY_ID_KSZ8041, 0x00fffff0 },
780 { PHY_ID_KSZ8051, 0x00fffff0 },
David J. Choi7ab59dc2013-01-23 14:05:15 +0000781 { PHY_ID_KSZ8061, 0x00fffff0 },
782 { PHY_ID_KSZ8081, 0x00fffff0 },
Jean-Christophe PLAGNIOL-VILLARD93272e02012-11-21 05:38:07 +0000783 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
David J. Choi7ab59dc2013-01-23 14:05:15 +0000784 { PHY_ID_KSZ886X, 0x00fffff0 },
David S. Miller52a60ed2010-05-03 15:48:29 -0700785 { }
786};
787
788MODULE_DEVICE_TABLE(mdio, micrel_tbl);