blob: eba66a22a265df702c91bdefcd83bfb3f24cad2b [file] [log] [blame]
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001/*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <asm/barrier.h>
22#include <dt-bindings/dma/at91.h>
23#include <linux/clk.h>
24#include <linux/dmaengine.h>
25#include <linux/dmapool.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/list.h>
29#include <linux/module.h>
30#include <linux/of_dma.h>
31#include <linux/of_platform.h>
32#include <linux/platform_device.h>
33#include <linux/pm.h>
34
35#include "dmaengine.h"
36
37/* Global registers */
38#define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
39#define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
40#define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
41#define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
42#define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
43#define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
44#define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
45#define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
46#define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
47#define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
48#define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
49#define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
50#define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
51#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
52#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
53#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
54#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
55#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
56#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
57#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
58#define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
59
60/* Channel relative registers offsets */
61#define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
62#define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
63#define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
64#define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
65#define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
66#define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
67#define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
68#define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
69#define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
70#define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
71#define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
72#define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
73#define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
74#define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
75#define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
76#define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
77#define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
78#define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
79#define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
80#define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
81#define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
82#define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
83#define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
84#define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
85#define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
86#define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
87#define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
88#define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
89#define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
90#define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
91#define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
92#define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
93#define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
94#define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
95#define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
96#define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
97#define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
98#define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
99#define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
100#define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
101#define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
102#define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
103#define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
104#define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
105#define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
106#define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
107#define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
108#define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
109#define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
110#define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
111#define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
112#define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
113#define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
114#define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
115#define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
116#define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
117#define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
118#define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
119#define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
120#define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
121#define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
122#define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
123#define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
124#define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
125#define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
126#define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
127#define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
128#define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
129#define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
130#define AT_XDMAC_CC_DWIDTH_OFFSET 11
131#define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
132#define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
133#define AT_XDMAC_CC_DWIDTH_BYTE 0x0
134#define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
135#define AT_XDMAC_CC_DWIDTH_WORD 0x2
136#define AT_XDMAC_CC_DWIDTH_DWORD 0x3
137#define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
138#define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
139#define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
140#define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
141#define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
142#define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
143#define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
144#define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
145#define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
146#define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
147#define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
148#define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
149#define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
150#define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
151#define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
152#define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
153#define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
154#define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
155#define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
156#define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
157#define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
158#define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
159#define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
160#define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
161#define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
162
163#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
164
165/* Microblock control members */
166#define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
167#define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
168#define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
169#define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
170#define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
171#define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
172#define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
173#define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
174
175#define AT_XDMAC_MAX_CHAN 0x20
176
Ludovic Desroches8ac82f82014-11-17 14:42:44 +0100177#define AT_XDMAC_DMA_BUSWIDTHS\
178 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
179 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
180 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
181 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
182 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
183
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200184enum atc_status {
185 AT_XDMAC_CHAN_IS_CYCLIC = 0,
186 AT_XDMAC_CHAN_IS_PAUSED,
187};
188
189/* ----- Channels ----- */
190struct at_xdmac_chan {
191 struct dma_chan chan;
192 void __iomem *ch_regs;
193 u32 mask; /* Channel Mask */
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100194 u32 cfg[2]; /* Channel Configuration Register */
195 #define AT_XDMAC_DEV_TO_MEM_CFG 0 /* Predifined dev to mem channel conf */
196 #define AT_XDMAC_MEM_TO_DEV_CFG 1 /* Predifined mem to dev channel conf */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200197 u8 perid; /* Peripheral ID */
198 u8 perif; /* Peripheral Interface */
199 u8 memif; /* Memory Interface */
200 u32 per_src_addr;
201 u32 per_dst_addr;
Ludovic Desroches734bb9a2015-01-27 16:30:30 +0100202 u32 save_cc;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200203 u32 save_cim;
204 u32 save_cnda;
205 u32 save_cndc;
206 unsigned long status;
207 struct tasklet_struct tasklet;
208
209 spinlock_t lock;
210
211 struct list_head xfers_list;
212 struct list_head free_descs_list;
213};
214
215
216/* ----- Controller ----- */
217struct at_xdmac {
218 struct dma_device dma;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 u32 save_gim;
223 u32 save_gs;
224 struct dma_pool *at_xdmac_desc_pool;
225 struct at_xdmac_chan chan[0];
226};
227
228
229/* ----- Descriptors ----- */
230
231/* Linked List Descriptor */
232struct at_xdmac_lld {
233 dma_addr_t mbr_nda; /* Next Descriptor Member */
234 u32 mbr_ubc; /* Microblock Control Member */
235 dma_addr_t mbr_sa; /* Source Address Member */
236 dma_addr_t mbr_da; /* Destination Address Member */
237 u32 mbr_cfg; /* Configuration Register */
238};
239
240
241struct at_xdmac_desc {
242 struct at_xdmac_lld lld;
243 enum dma_transfer_direction direction;
244 struct dma_async_tx_descriptor tx_dma_desc;
245 struct list_head desc_node;
246 /* Following members are only used by the first descriptor */
247 bool active_xfer;
248 unsigned int xfer_size;
249 struct list_head descs_list;
250 struct list_head xfer_node;
251};
252
253static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
254{
255 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
256}
257
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100258#define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200259#define at_xdmac_write(atxdmac, reg, value) \
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100260 writel_relaxed((value), (atxdmac)->regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200261
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100262#define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
263#define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200264
265static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
266{
267 return container_of(dchan, struct at_xdmac_chan, chan);
268}
269
270static struct device *chan2dev(struct dma_chan *chan)
271{
272 return &chan->dev->device;
273}
274
275static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
276{
277 return container_of(ddev, struct at_xdmac, dma);
278}
279
280static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
281{
282 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
283}
284
285static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
286{
287 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
288}
289
290static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
291{
292 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
293}
294
295static inline int at_xdmac_csize(u32 maxburst)
296{
297 int csize;
298
299 csize = ffs(maxburst) - 1;
300 if (csize > 4)
301 csize = -EINVAL;
302
303 return csize;
304};
305
306static inline u8 at_xdmac_get_dwidth(u32 cfg)
307{
308 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
309};
310
311static unsigned int init_nr_desc_per_channel = 64;
312module_param(init_nr_desc_per_channel, uint, 0644);
313MODULE_PARM_DESC(init_nr_desc_per_channel,
314 "initial descriptors per channel (default: 64)");
315
316
317static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
318{
319 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
320}
321
322static void at_xdmac_off(struct at_xdmac *atxdmac)
323{
324 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
325
326 /* Wait that all chans are disabled. */
327 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
328 cpu_relax();
329
330 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
331}
332
333/* Call with lock hold. */
334static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
335 struct at_xdmac_desc *first)
336{
337 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
338 u32 reg;
339
340 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
341
342 if (at_xdmac_chan_is_enabled(atchan))
343 return;
344
345 /* Set transfer as active to not try to start it again. */
346 first->active_xfer = true;
347
348 /* Tell xdmac where to get the first descriptor. */
349 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
350 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
351 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
352
353 /*
354 * When doing memory to memory transfer we need to use the next
355 * descriptor view 2 since some fields of the configuration register
356 * depend on transfer size and src/dest addresses.
357 */
358 if (is_slave_direction(first->direction)) {
359 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100360 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200361 } else {
362 /*
363 * No need to write AT_XDMAC_CC reg, it will be done when the
364 * descriptor is fecthed.
365 */
366 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
367 }
368
369 reg |= AT_XDMAC_CNDC_NDDUP
370 | AT_XDMAC_CNDC_NDSUP
371 | AT_XDMAC_CNDC_NDE;
372 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
373
374 dev_vdbg(chan2dev(&atchan->chan),
375 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
376 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
377 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
378 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
379 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
380 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
381 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
382
383 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
384 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
385 /*
386 * There is no end of list when doing cyclic dma, we need to get
387 * an interrupt after each periods.
388 */
389 if (at_xdmac_chan_is_cyclic(atchan))
390 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
391 reg | AT_XDMAC_CIE_BIE);
392 else
393 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
394 reg | AT_XDMAC_CIE_LIE);
395 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
396 dev_vdbg(chan2dev(&atchan->chan),
397 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
398 wmb();
399 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
400
401 dev_vdbg(chan2dev(&atchan->chan),
402 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
403 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
404 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
405 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
406 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
407 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
408 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
409
410}
411
412static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
413{
414 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
415 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
416 dma_cookie_t cookie;
417
418 spin_lock_bh(&atchan->lock);
419 cookie = dma_cookie_assign(tx);
420
421 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
422 __func__, atchan, desc);
423 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
424 if (list_is_singular(&atchan->xfers_list))
425 at_xdmac_start_xfer(atchan, desc);
426
427 spin_unlock_bh(&atchan->lock);
428 return cookie;
429}
430
431static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
432 gfp_t gfp_flags)
433{
434 struct at_xdmac_desc *desc;
435 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
436 dma_addr_t phys;
437
438 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
439 if (desc) {
440 memset(desc, 0, sizeof(*desc));
441 INIT_LIST_HEAD(&desc->descs_list);
442 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
443 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
444 desc->tx_dma_desc.phys = phys;
445 }
446
447 return desc;
448}
449
450/* Call must be protected by lock. */
451static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
452{
453 struct at_xdmac_desc *desc;
454
455 if (list_empty(&atchan->free_descs_list)) {
456 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
457 } else {
458 desc = list_first_entry(&atchan->free_descs_list,
459 struct at_xdmac_desc, desc_node);
460 list_del(&desc->desc_node);
461 desc->active_xfer = false;
462 }
463
464 return desc;
465}
466
467static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
468 struct of_dma *of_dma)
469{
470 struct at_xdmac *atxdmac = of_dma->of_dma_data;
471 struct at_xdmac_chan *atchan;
472 struct dma_chan *chan;
473 struct device *dev = atxdmac->dma.dev;
474
475 if (dma_spec->args_count != 1) {
476 dev_err(dev, "dma phandler args: bad number of args\n");
477 return NULL;
478 }
479
480 chan = dma_get_any_slave_channel(&atxdmac->dma);
481 if (!chan) {
482 dev_err(dev, "can't get a dma channel\n");
483 return NULL;
484 }
485
486 atchan = to_at_xdmac_chan(chan);
487 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
488 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
489 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
490 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
491 atchan->memif, atchan->perif, atchan->perid);
492
493 return chan;
494}
495
496static int at_xdmac_set_slave_config(struct dma_chan *chan,
497 struct dma_slave_config *sconfig)
498{
499 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
500 u8 dwidth;
501 int csize;
502
503 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] =
504 AT91_XDMAC_DT_PERID(atchan->perid)
505 | AT_XDMAC_CC_DAM_INCREMENTED_AM
506 | AT_XDMAC_CC_SAM_FIXED_AM
507 | AT_XDMAC_CC_DIF(atchan->memif)
508 | AT_XDMAC_CC_SIF(atchan->perif)
509 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
510 | AT_XDMAC_CC_DSYNC_PER2MEM
511 | AT_XDMAC_CC_MBSIZE_SIXTEEN
512 | AT_XDMAC_CC_TYPE_PER_TRAN;
513 csize = at_xdmac_csize(sconfig->src_maxburst);
514 if (csize < 0) {
515 dev_err(chan2dev(chan), "invalid src maxburst value\n");
516 return -EINVAL;
517 }
518 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_CSIZE(csize);
519 dwidth = ffs(sconfig->src_addr_width) - 1;
520 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth);
521
522
523 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] =
524 AT91_XDMAC_DT_PERID(atchan->perid)
525 | AT_XDMAC_CC_DAM_FIXED_AM
526 | AT_XDMAC_CC_SAM_INCREMENTED_AM
527 | AT_XDMAC_CC_DIF(atchan->perif)
528 | AT_XDMAC_CC_SIF(atchan->memif)
529 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
530 | AT_XDMAC_CC_DSYNC_MEM2PER
531 | AT_XDMAC_CC_MBSIZE_SIXTEEN
532 | AT_XDMAC_CC_TYPE_PER_TRAN;
533 csize = at_xdmac_csize(sconfig->dst_maxburst);
534 if (csize < 0) {
535 dev_err(chan2dev(chan), "invalid src maxburst value\n");
536 return -EINVAL;
537 }
538 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_CSIZE(csize);
539 dwidth = ffs(sconfig->dst_addr_width) - 1;
540 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth);
541
542 /* Src and dst addr are needed to configure the link list descriptor. */
543 atchan->per_src_addr = sconfig->src_addr;
544 atchan->per_dst_addr = sconfig->dst_addr;
545
546 dev_dbg(chan2dev(chan),
547 "%s: cfg[dev2mem]=0x%08x, cfg[mem2dev]=0x%08x, per_src_addr=0x%08x, per_dst_addr=0x%08x\n",
548 __func__, atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG],
549 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG],
550 atchan->per_src_addr, atchan->per_dst_addr);
551
552 return 0;
553}
554
555static struct dma_async_tx_descriptor *
556at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
557 unsigned int sg_len, enum dma_transfer_direction direction,
558 unsigned long flags, void *context)
559{
560 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
561 struct at_xdmac_desc *first = NULL, *prev = NULL;
562 struct scatterlist *sg;
563 int i;
Cyrille Pitchen57819272014-11-13 11:52:42 +0100564 unsigned int xfer_size = 0;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200565
566 if (!sgl)
567 return NULL;
568
569 if (!is_slave_direction(direction)) {
570 dev_err(chan2dev(chan), "invalid DMA direction\n");
571 return NULL;
572 }
573
574 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
575 __func__, sg_len,
576 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
577 flags);
578
579 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
580 spin_lock_bh(&atchan->lock);
581
582 /* Prepare descriptors. */
583 for_each_sg(sgl, sg, sg_len, i) {
584 struct at_xdmac_desc *desc = NULL;
585 u32 len, mem;
586
587 len = sg_dma_len(sg);
588 mem = sg_dma_address(sg);
589 if (unlikely(!len)) {
590 dev_err(chan2dev(chan), "sg data length is zero\n");
591 spin_unlock_bh(&atchan->lock);
592 return NULL;
593 }
594 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
595 __func__, i, len, mem);
596
597 desc = at_xdmac_get_desc(atchan);
598 if (!desc) {
599 dev_err(chan2dev(chan), "can't get descriptor\n");
600 if (first)
601 list_splice_init(&first->descs_list, &atchan->free_descs_list);
602 spin_unlock_bh(&atchan->lock);
603 return NULL;
604 }
605
606 /* Linked list descriptor setup. */
607 if (direction == DMA_DEV_TO_MEM) {
608 desc->lld.mbr_sa = atchan->per_src_addr;
609 desc->lld.mbr_da = mem;
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100610 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG];
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200611 } else {
612 desc->lld.mbr_sa = mem;
613 desc->lld.mbr_da = atchan->per_dst_addr;
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100614 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200615 }
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100616 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 /* next descriptor view */
617 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
618 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
619 | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */
620 | len / (1 << at_xdmac_get_dwidth(desc->lld.mbr_cfg)); /* microblock length */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200621 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530622 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
623 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200624
625 /* Chain lld. */
626 if (prev) {
627 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
628 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530629 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
630 __func__, prev, &prev->lld.mbr_nda);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200631 }
632
633 prev = desc;
634 if (!first)
635 first = desc;
636
637 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
638 __func__, desc, first);
639 list_add_tail(&desc->desc_node, &first->descs_list);
Cyrille Pitchen57819272014-11-13 11:52:42 +0100640 xfer_size += len;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200641 }
642
643 spin_unlock_bh(&atchan->lock);
644
645 first->tx_dma_desc.flags = flags;
Cyrille Pitchen57819272014-11-13 11:52:42 +0100646 first->xfer_size = xfer_size;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200647 first->direction = direction;
648
649 return &first->tx_dma_desc;
650}
651
652static struct dma_async_tx_descriptor *
653at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
654 size_t buf_len, size_t period_len,
655 enum dma_transfer_direction direction,
656 unsigned long flags)
657{
658 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
659 struct at_xdmac_desc *first = NULL, *prev = NULL;
660 unsigned int periods = buf_len / period_len;
661 int i;
662 u32 cfg;
663
Vinod Koul82e24242014-11-06 18:02:52 +0530664 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
665 __func__, &buf_addr, buf_len, period_len,
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200666 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
667
668 if (!is_slave_direction(direction)) {
669 dev_err(chan2dev(chan), "invalid DMA direction\n");
670 return NULL;
671 }
672
673 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
674 dev_err(chan2dev(chan), "channel currently used\n");
675 return NULL;
676 }
677
678 for (i = 0; i < periods; i++) {
679 struct at_xdmac_desc *desc = NULL;
680
681 spin_lock_bh(&atchan->lock);
682 desc = at_xdmac_get_desc(atchan);
683 if (!desc) {
684 dev_err(chan2dev(chan), "can't get descriptor\n");
685 if (first)
686 list_splice_init(&first->descs_list, &atchan->free_descs_list);
687 spin_unlock_bh(&atchan->lock);
688 return NULL;
689 }
690 spin_unlock_bh(&atchan->lock);
691 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530692 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
693 __func__, desc, &desc->tx_dma_desc.phys);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200694
695 if (direction == DMA_DEV_TO_MEM) {
696 desc->lld.mbr_sa = atchan->per_src_addr;
697 desc->lld.mbr_da = buf_addr + i * period_len;
698 cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG];
699 } else {
700 desc->lld.mbr_sa = buf_addr + i * period_len;
701 desc->lld.mbr_da = atchan->per_dst_addr;
702 cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
kbuild test robot5ac7d582014-11-06 17:28:08 +0800703 }
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200704 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
705 | AT_XDMAC_MBR_UBC_NDEN
706 | AT_XDMAC_MBR_UBC_NSEN
707 | AT_XDMAC_MBR_UBC_NDE
708 | period_len >> at_xdmac_get_dwidth(cfg);
709
710 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530711 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
712 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200713
714 /* Chain lld. */
715 if (prev) {
716 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
717 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530718 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
719 __func__, prev, &prev->lld.mbr_nda);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200720 }
721
722 prev = desc;
723 if (!first)
724 first = desc;
725
726 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
727 __func__, desc, first);
728 list_add_tail(&desc->desc_node, &first->descs_list);
729 }
730
731 prev->lld.mbr_nda = first->tx_dma_desc.phys;
732 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530733 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
734 __func__, prev, &prev->lld.mbr_nda);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200735 first->tx_dma_desc.flags = flags;
736 first->xfer_size = buf_len;
737 first->direction = direction;
738
739 return &first->tx_dma_desc;
740}
741
742static struct dma_async_tx_descriptor *
743at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
744 size_t len, unsigned long flags)
745{
746 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
747 struct at_xdmac_desc *first = NULL, *prev = NULL;
748 size_t remaining_size = len, xfer_size = 0, ublen;
749 dma_addr_t src_addr = src, dst_addr = dest;
750 u32 dwidth;
751 /*
752 * WARNING: We don't know the direction, it involves we can't
753 * dynamically set the source and dest interface so we have to use the
754 * same one. Only interface 0 allows EBI access. Hopefully we can
755 * access DDR through both ports (at least on SAMA5D4x), so we can use
756 * the same interface for source and dest, that solves the fact we
757 * don't know the direction.
758 */
759 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
760 | AT_XDMAC_CC_SAM_INCREMENTED_AM
761 | AT_XDMAC_CC_DIF(0)
762 | AT_XDMAC_CC_SIF(0)
763 | AT_XDMAC_CC_MBSIZE_SIXTEEN
764 | AT_XDMAC_CC_TYPE_MEM_TRAN;
765
Vinod Koul82e24242014-11-06 18:02:52 +0530766 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
767 __func__, &src, &dest, len, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200768
769 if (unlikely(!len))
770 return NULL;
771
772 /*
773 * Check address alignment to select the greater data width we can use.
774 * Some XDMAC implementations don't provide dword transfer, in this
775 * case selecting dword has the same behavior as selecting word transfers.
776 */
777 if (!((src_addr | dst_addr) & 7)) {
778 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
779 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
780 } else if (!((src_addr | dst_addr) & 3)) {
781 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
782 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
783 } else if (!((src_addr | dst_addr) & 1)) {
784 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
785 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
786 } else {
787 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
788 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
789 }
790
791 /* Prepare descriptors. */
792 while (remaining_size) {
793 struct at_xdmac_desc *desc = NULL;
794
Vinod Koulc66ec042014-11-06 17:37:48 +0530795 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200796
797 spin_lock_bh(&atchan->lock);
798 desc = at_xdmac_get_desc(atchan);
799 spin_unlock_bh(&atchan->lock);
800 if (!desc) {
801 dev_err(chan2dev(chan), "can't get descriptor\n");
802 if (first)
803 list_splice_init(&first->descs_list, &atchan->free_descs_list);
804 return NULL;
805 }
806
807 /* Update src and dest addresses. */
808 src_addr += xfer_size;
809 dst_addr += xfer_size;
810
811 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
812 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
813 else
814 xfer_size = remaining_size;
815
Vinod Koulc66ec042014-11-06 17:37:48 +0530816 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200817
818 /* Check remaining length and change data width if needed. */
819 if (!((src_addr | dst_addr | xfer_size) & 7)) {
820 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
821 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
822 } else if (!((src_addr | dst_addr | xfer_size) & 3)) {
823 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
824 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
825 } else if (!((src_addr | dst_addr | xfer_size) & 1)) {
826 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
827 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
828 } else if ((src_addr | dst_addr | xfer_size) & 1) {
829 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
830 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
831 }
832 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
833
834 ublen = xfer_size >> dwidth;
835 remaining_size -= xfer_size;
836
837 desc->lld.mbr_sa = src_addr;
838 desc->lld.mbr_da = dst_addr;
839 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
840 | AT_XDMAC_MBR_UBC_NDEN
841 | AT_XDMAC_MBR_UBC_NSEN
842 | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0)
843 | ublen;
844 desc->lld.mbr_cfg = chan_cc;
845
846 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530847 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
848 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200849
850 /* Chain lld. */
851 if (prev) {
852 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
853 dev_dbg(chan2dev(chan),
854 "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
855 __func__, prev, prev->lld.mbr_nda);
856 }
857
858 prev = desc;
859 if (!first)
860 first = desc;
861
862 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
863 __func__, desc, first);
864 list_add_tail(&desc->desc_node, &first->descs_list);
865 }
866
867 first->tx_dma_desc.flags = flags;
868 first->xfer_size = len;
869
870 return &first->tx_dma_desc;
871}
872
873static enum dma_status
874at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
875 struct dma_tx_state *txstate)
876{
877 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
878 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
879 struct at_xdmac_desc *desc, *_desc;
880 struct list_head *descs_list;
881 enum dma_status ret;
882 int residue;
Cyrille Pitchen4e097822014-11-13 11:52:41 +0100883 u32 cur_nda, mask, value;
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100884 u8 dwidth = 0;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200885
886 ret = dma_cookie_status(chan, cookie, txstate);
887 if (ret == DMA_COMPLETE)
888 return ret;
889
890 if (!txstate)
891 return ret;
892
893 spin_lock_bh(&atchan->lock);
894
895 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
896
897 /*
898 * If the transfer has not been started yet, don't need to compute the
899 * residue, it's the transfer length.
900 */
901 if (!desc->active_xfer) {
902 dma_set_residue(txstate, desc->xfer_size);
Ludovic Desroches87809832014-11-13 11:52:43 +0100903 spin_unlock_bh(&atchan->lock);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200904 return ret;
905 }
906
907 residue = desc->xfer_size;
Cyrille Pitchen4e097822014-11-13 11:52:41 +0100908 /*
909 * Flush FIFO: only relevant when the transfer is source peripheral
910 * synchronized.
911 */
912 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
913 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100914 if ((desc->lld.mbr_cfg & mask) == value) {
Cyrille Pitchen4e097822014-11-13 11:52:41 +0100915 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
916 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
917 cpu_relax();
918 }
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200919
920 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
921 /*
922 * Remove size of all microblocks already transferred and the current
923 * one. Then add the remaining size to transfer of the current
924 * microblock.
925 */
926 descs_list = &desc->descs_list;
927 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100928 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200929 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
930 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
931 break;
932 }
933 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
934
935 spin_unlock_bh(&atchan->lock);
936
937 dma_set_residue(txstate, residue);
938
939 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530940 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
941 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200942
943 return ret;
944}
945
946/* Call must be protected by lock. */
947static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
948 struct at_xdmac_desc *desc)
949{
950 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
951
952 /*
953 * Remove the transfer from the transfer list then move the transfer
954 * descriptors into the free descriptors list.
955 */
956 list_del(&desc->xfer_node);
957 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
958}
959
960static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
961{
962 struct at_xdmac_desc *desc;
963
964 spin_lock_bh(&atchan->lock);
965
966 /*
967 * If channel is enabled, do nothing, advance_work will be triggered
968 * after the interruption.
969 */
970 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
971 desc = list_first_entry(&atchan->xfers_list,
972 struct at_xdmac_desc,
973 xfer_node);
974 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
975 if (!desc->active_xfer)
976 at_xdmac_start_xfer(atchan, desc);
977 }
978
979 spin_unlock_bh(&atchan->lock);
980}
981
982static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
983{
984 struct at_xdmac_desc *desc;
985 struct dma_async_tx_descriptor *txd;
986
987 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
988 txd = &desc->tx_dma_desc;
989
990 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
991 txd->callback(txd->callback_param);
992}
993
994static void at_xdmac_tasklet(unsigned long data)
995{
996 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
997 struct at_xdmac_desc *desc;
998 u32 error_mask;
999
1000 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1001 __func__, atchan->status);
1002
1003 error_mask = AT_XDMAC_CIS_RBEIS
1004 | AT_XDMAC_CIS_WBEIS
1005 | AT_XDMAC_CIS_ROIS;
1006
1007 if (at_xdmac_chan_is_cyclic(atchan)) {
1008 at_xdmac_handle_cyclic(atchan);
1009 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1010 || (atchan->status & error_mask)) {
1011 struct dma_async_tx_descriptor *txd;
1012
1013 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1014 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1015 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1016 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1017 if (atchan->status & AT_XDMAC_CIS_ROIS)
1018 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1019
1020 spin_lock_bh(&atchan->lock);
1021 desc = list_first_entry(&atchan->xfers_list,
1022 struct at_xdmac_desc,
1023 xfer_node);
1024 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1025 BUG_ON(!desc->active_xfer);
1026
1027 txd = &desc->tx_dma_desc;
1028
1029 at_xdmac_remove_xfer(atchan, desc);
1030 spin_unlock_bh(&atchan->lock);
1031
1032 if (!at_xdmac_chan_is_cyclic(atchan)) {
1033 dma_cookie_complete(txd);
1034 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1035 txd->callback(txd->callback_param);
1036 }
1037
1038 dma_run_dependencies(txd);
1039
1040 at_xdmac_advance_work(atchan);
1041 }
1042}
1043
1044static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1045{
1046 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1047 struct at_xdmac_chan *atchan;
1048 u32 imr, status, pending;
1049 u32 chan_imr, chan_status;
1050 int i, ret = IRQ_NONE;
1051
1052 do {
1053 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1054 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1055 pending = status & imr;
1056
1057 dev_vdbg(atxdmac->dma.dev,
1058 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1059 __func__, status, imr, pending);
1060
1061 if (!pending)
1062 break;
1063
1064 /* We have to find which channel has generated the interrupt. */
1065 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1066 if (!((1 << i) & pending))
1067 continue;
1068
1069 atchan = &atxdmac->chan[i];
1070 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1071 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1072 atchan->status = chan_status & chan_imr;
1073 dev_vdbg(atxdmac->dma.dev,
1074 "%s: chan%d: imr=0x%x, status=0x%x\n",
1075 __func__, i, chan_imr, chan_status);
1076 dev_vdbg(chan2dev(&atchan->chan),
1077 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1078 __func__,
1079 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1080 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1081 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1082 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1083 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1084 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1085
1086 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1087 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1088
1089 tasklet_schedule(&atchan->tasklet);
1090 ret = IRQ_HANDLED;
1091 }
1092
1093 } while (pending);
1094
1095 return ret;
1096}
1097
1098static void at_xdmac_issue_pending(struct dma_chan *chan)
1099{
1100 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1101
1102 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1103
1104 if (!at_xdmac_chan_is_cyclic(atchan))
1105 at_xdmac_advance_work(atchan);
1106
1107 return;
1108}
1109
Ludovic Desroches3d138872014-11-17 14:42:07 +01001110static int at_xdmac_device_config(struct dma_chan *chan,
1111 struct dma_slave_config *config)
1112{
1113 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1114 int ret;
1115
1116 dev_dbg(chan2dev(chan), "%s\n", __func__);
1117
1118 spin_lock_bh(&atchan->lock);
1119 ret = at_xdmac_set_slave_config(chan, config);
1120 spin_unlock_bh(&atchan->lock);
1121
1122 return ret;
1123}
1124
1125static int at_xdmac_device_pause(struct dma_chan *chan)
1126{
1127 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1128 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1129
1130 dev_dbg(chan2dev(chan), "%s\n", __func__);
1131
Cyrille Pitchencbb85e62015-01-27 16:30:29 +01001132 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1133 return 0;
1134
Ludovic Desroches3d138872014-11-17 14:42:07 +01001135 spin_lock_bh(&atchan->lock);
1136 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
Cyrille Pitchencbb85e62015-01-27 16:30:29 +01001137 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1138 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1139 cpu_relax();
Ludovic Desroches3d138872014-11-17 14:42:07 +01001140 spin_unlock_bh(&atchan->lock);
1141
1142 return 0;
1143}
1144
1145static int at_xdmac_device_resume(struct dma_chan *chan)
1146{
1147 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1148 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1149
1150 dev_dbg(chan2dev(chan), "%s\n", __func__);
1151
1152 spin_lock_bh(&atchan->lock);
1153 if (!at_xdmac_chan_is_paused(atchan))
1154 return 0;
1155
1156 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1157 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1158 spin_unlock_bh(&atchan->lock);
1159
1160 return 0;
1161}
1162
1163static int at_xdmac_device_terminate_all(struct dma_chan *chan)
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001164{
1165 struct at_xdmac_desc *desc, *_desc;
1166 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1167 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001168
Ludovic Desroches3d138872014-11-17 14:42:07 +01001169 dev_dbg(chan2dev(chan), "%s\n", __func__);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001170
1171 spin_lock_bh(&atchan->lock);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001172 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1173 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1174 cpu_relax();
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001175
Ludovic Desroches3d138872014-11-17 14:42:07 +01001176 /* Cancel all pending transfers. */
1177 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1178 at_xdmac_remove_xfer(atchan, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001179
Ludovic Desroches3d138872014-11-17 14:42:07 +01001180 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001181 spin_unlock_bh(&atchan->lock);
1182
Ludovic Desroches3d138872014-11-17 14:42:07 +01001183 return 0;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001184}
1185
1186static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1187{
1188 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1189 struct at_xdmac_desc *desc;
1190 int i;
1191
1192 spin_lock_bh(&atchan->lock);
1193
1194 if (at_xdmac_chan_is_enabled(atchan)) {
1195 dev_err(chan2dev(chan),
1196 "can't allocate channel resources (channel enabled)\n");
1197 i = -EIO;
1198 goto spin_unlock;
1199 }
1200
1201 if (!list_empty(&atchan->free_descs_list)) {
1202 dev_err(chan2dev(chan),
1203 "can't allocate channel resources (channel not free from a previous use)\n");
1204 i = -EIO;
1205 goto spin_unlock;
1206 }
1207
1208 for (i = 0; i < init_nr_desc_per_channel; i++) {
1209 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1210 if (!desc) {
1211 dev_warn(chan2dev(chan),
1212 "only %d descriptors have been allocated\n", i);
1213 break;
1214 }
1215 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1216 }
1217
1218 dma_cookie_init(chan);
1219
1220 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1221
1222spin_unlock:
1223 spin_unlock_bh(&atchan->lock);
1224 return i;
1225}
1226
1227static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1228{
1229 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1230 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1231 struct at_xdmac_desc *desc, *_desc;
1232
1233 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1234 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1235 list_del(&desc->desc_node);
1236 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1237 }
1238
1239 return;
1240}
1241
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001242#ifdef CONFIG_PM
1243static int atmel_xdmac_prepare(struct device *dev)
1244{
1245 struct platform_device *pdev = to_platform_device(dev);
1246 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1247 struct dma_chan *chan, *_chan;
1248
1249 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1250 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1251
1252 /* Wait for transfer completion, except in cyclic case. */
1253 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1254 return -EAGAIN;
1255 }
1256 return 0;
1257}
1258#else
1259# define atmel_xdmac_prepare NULL
1260#endif
1261
1262#ifdef CONFIG_PM_SLEEP
1263static int atmel_xdmac_suspend(struct device *dev)
1264{
1265 struct platform_device *pdev = to_platform_device(dev);
1266 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1267 struct dma_chan *chan, *_chan;
1268
1269 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1270 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1271
Ludovic Desroches734bb9a2015-01-27 16:30:30 +01001272 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001273 if (at_xdmac_chan_is_cyclic(atchan)) {
1274 if (!at_xdmac_chan_is_paused(atchan))
Ludovic Desroches3d138872014-11-17 14:42:07 +01001275 at_xdmac_device_pause(chan);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001276 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1277 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1278 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1279 }
1280 }
1281 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1282
1283 at_xdmac_off(atxdmac);
1284 clk_disable_unprepare(atxdmac->clk);
1285 return 0;
1286}
1287
1288static int atmel_xdmac_resume(struct device *dev)
1289{
1290 struct platform_device *pdev = to_platform_device(dev);
1291 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1292 struct at_xdmac_chan *atchan;
1293 struct dma_chan *chan, *_chan;
1294 int i;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001295
1296 clk_prepare_enable(atxdmac->clk);
1297
1298 /* Clear pending interrupts. */
1299 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1300 atchan = &atxdmac->chan[i];
1301 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1302 cpu_relax();
1303 }
1304
1305 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1306 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1307 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1308 atchan = to_at_xdmac_chan(chan);
Ludovic Desroches734bb9a2015-01-27 16:30:30 +01001309 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001310 if (at_xdmac_chan_is_cyclic(atchan)) {
1311 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1312 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1313 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1314 wmb();
1315 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1316 }
1317 }
1318 return 0;
1319}
1320#endif /* CONFIG_PM_SLEEP */
1321
1322static int at_xdmac_probe(struct platform_device *pdev)
1323{
1324 struct resource *res;
1325 struct at_xdmac *atxdmac;
1326 int irq, size, nr_channels, i, ret;
1327 void __iomem *base;
1328 u32 reg;
1329
1330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 if (!res)
1332 return -EINVAL;
1333
1334 irq = platform_get_irq(pdev, 0);
1335 if (irq < 0)
1336 return irq;
1337
1338 base = devm_ioremap_resource(&pdev->dev, res);
1339 if (IS_ERR(base))
1340 return PTR_ERR(base);
1341
1342 /*
1343 * Read number of xdmac channels, read helper function can't be used
1344 * since atxdmac is not yet allocated and we need to know the number
1345 * of channels to do the allocation.
1346 */
1347 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1348 nr_channels = AT_XDMAC_NB_CH(reg);
1349 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1350 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1351 nr_channels);
1352 return -EINVAL;
1353 }
1354
1355 size = sizeof(*atxdmac);
1356 size += nr_channels * sizeof(struct at_xdmac_chan);
1357 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1358 if (!atxdmac) {
1359 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1360 return -ENOMEM;
1361 }
1362
1363 atxdmac->regs = base;
1364 atxdmac->irq = irq;
1365
1366 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1367 if (IS_ERR(atxdmac->clk)) {
1368 dev_err(&pdev->dev, "can't get dma_clk\n");
1369 return PTR_ERR(atxdmac->clk);
1370 }
1371
1372 /* Do not use dev res to prevent races with tasklet */
1373 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1374 if (ret) {
1375 dev_err(&pdev->dev, "can't request irq\n");
1376 return ret;
1377 }
1378
1379 ret = clk_prepare_enable(atxdmac->clk);
1380 if (ret) {
1381 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1382 goto err_free_irq;
1383 }
1384
1385 atxdmac->at_xdmac_desc_pool =
1386 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1387 sizeof(struct at_xdmac_desc), 4, 0);
1388 if (!atxdmac->at_xdmac_desc_pool) {
1389 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1390 ret = -ENOMEM;
1391 goto err_clk_disable;
1392 }
1393
1394 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1395 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1396 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
Ludovic Desrochesfef4cbf2014-11-13 11:52:45 +01001397 /*
1398 * Without DMA_PRIVATE the driver is not able to allocate more than
1399 * one channel, second allocation fails in private_candidate.
1400 */
1401 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001402 atxdmac->dma.dev = &pdev->dev;
1403 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1404 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1405 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1406 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1407 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1408 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1409 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001410 atxdmac->dma.device_config = at_xdmac_device_config;
1411 atxdmac->dma.device_pause = at_xdmac_device_pause;
1412 atxdmac->dma.device_resume = at_xdmac_device_resume;
1413 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
Ludovic Desroches8ac82f82014-11-17 14:42:44 +01001414 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1415 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1416 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1417 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001418
1419 /* Disable all chans and interrupts. */
1420 at_xdmac_off(atxdmac);
1421
1422 /* Init channels. */
1423 INIT_LIST_HEAD(&atxdmac->dma.channels);
1424 for (i = 0; i < nr_channels; i++) {
1425 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1426
1427 atchan->chan.device = &atxdmac->dma;
1428 list_add_tail(&atchan->chan.device_node,
1429 &atxdmac->dma.channels);
1430
1431 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1432 atchan->mask = 1 << i;
1433
1434 spin_lock_init(&atchan->lock);
1435 INIT_LIST_HEAD(&atchan->xfers_list);
1436 INIT_LIST_HEAD(&atchan->free_descs_list);
1437 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1438 (unsigned long)atchan);
1439
1440 /* Clear pending interrupts. */
1441 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1442 cpu_relax();
1443 }
1444 platform_set_drvdata(pdev, atxdmac);
1445
1446 ret = dma_async_device_register(&atxdmac->dma);
1447 if (ret) {
1448 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1449 goto err_clk_disable;
1450 }
1451
1452 ret = of_dma_controller_register(pdev->dev.of_node,
1453 at_xdmac_xlate, atxdmac);
1454 if (ret) {
1455 dev_err(&pdev->dev, "could not register of dma controller\n");
1456 goto err_dma_unregister;
1457 }
1458
1459 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1460 nr_channels, atxdmac->regs);
1461
1462 return 0;
1463
1464err_dma_unregister:
1465 dma_async_device_unregister(&atxdmac->dma);
1466err_clk_disable:
1467 clk_disable_unprepare(atxdmac->clk);
1468err_free_irq:
1469 free_irq(atxdmac->irq, atxdmac->dma.dev);
1470 return ret;
1471}
1472
1473static int at_xdmac_remove(struct platform_device *pdev)
1474{
1475 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1476 int i;
1477
1478 at_xdmac_off(atxdmac);
1479 of_dma_controller_free(pdev->dev.of_node);
1480 dma_async_device_unregister(&atxdmac->dma);
1481 clk_disable_unprepare(atxdmac->clk);
1482
1483 synchronize_irq(atxdmac->irq);
1484
1485 free_irq(atxdmac->irq, atxdmac->dma.dev);
1486
1487 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1488 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1489
1490 tasklet_kill(&atchan->tasklet);
1491 at_xdmac_free_chan_resources(&atchan->chan);
1492 }
1493
1494 return 0;
1495}
1496
1497static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
1498 .prepare = atmel_xdmac_prepare,
1499 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
1500};
1501
1502static const struct of_device_id atmel_xdmac_dt_ids[] = {
1503 {
1504 .compatible = "atmel,sama5d4-dma",
1505 }, {
1506 /* sentinel */
1507 }
1508};
1509MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
1510
1511static struct platform_driver at_xdmac_driver = {
1512 .probe = at_xdmac_probe,
1513 .remove = at_xdmac_remove,
1514 .driver = {
1515 .name = "at_xdmac",
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001516 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
1517 .pm = &atmel_xdmac_dev_pm_ops,
1518 }
1519};
1520
1521static int __init at_xdmac_init(void)
1522{
1523 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
1524}
1525subsys_initcall(at_xdmac_init);
1526
1527MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
1528MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1529MODULE_LICENSE("GPL");