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Ivo van Doorn95ea3622007-09-25 17:57:13 -07001/*
Ivo van Doorn811aa9c2008-02-03 15:42:53 +01002 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
Ivo van Doorn95ea3622007-09-25 17:57:13 -07003 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
Ivo van Doorn95ea3622007-09-25 17:57:13 -070027#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
Adam Baker0e14f6d2007-10-27 13:41:25 +020052static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -070053{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
Adam Baker0e14f6d2007-10-27 13:41:25 +020067static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070068 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
Adam Baker0e14f6d2007-10-27 13:41:25 +020093static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070094 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
Adam Baker0e14f6d2007-10-27 13:41:25 +0200130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
Adam Baker0e14f6d2007-10-27 13:41:25 +0200193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
Adam Baker0e14f6d2007-10-27 13:41:25 +0200199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
Ivo van Doorn81873e92007-10-06 14:14:06 +0200242#else
243#define rt2400pci_rfkill_poll NULL
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700244#endif /* CONFIG_RT2400PCI_RFKILL */
245
Ivo van Doorna9450b72008-02-03 15:53:40 +0100246#ifdef CONFIG_RT2400PCI_LEDS
247static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2400pci_led_brightness NULL
268#endif /* CONFIG_RT2400PCI_LEDS */
269
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700270/*
271 * Configuration handlers.
272 */
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100273static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700277{
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100278 unsigned int bcn_preload;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700279 u32 reg;
280
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100281 if (flags & CONFIG_UPDATE_TYPE) {
282 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700283
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100284 /*
285 * Enable beacon config
286 */
287 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
288 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
289 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
290 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700291
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100292 /*
293 * Enable synchronisation.
294 */
295 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
296 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
297 rt2x00_set_field32(&reg, CSR14_TBCN,
298 (conf->sync == TSF_SYNC_BEACON));
299 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
300 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
301 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
302 }
303
304 if (flags & CONFIG_UPDATE_MAC)
305 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
306 conf->mac, sizeof(conf->mac));
307
308 if (flags & CONFIG_UPDATE_BSSID)
309 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
310 conf->bssid, sizeof(conf->bssid));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700311}
312
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100313static int rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
314 const int short_preamble,
315 const int ack_timeout,
316 const int ack_consume_time)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700317{
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200318 int preamble_mask;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700319 u32 reg;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700320
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200321 /*
322 * When short preamble is enabled, we should set bit 0x08
323 */
324 preamble_mask = short_preamble << 3;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700325
326 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200327 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
328 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700329 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
330
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700331 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200332 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700333 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
334 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
335 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
336
337 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200338 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700339 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
340 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
341 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
342
343 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200344 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700345 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
346 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
347 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
348
349 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200350 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700351 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
352 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
353 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100354
355 return 0;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700356}
357
358static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200359 const int basic_rate_mask)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700360{
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200361 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700362}
363
364static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200365 struct rf_channel *rf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700366{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700367 /*
368 * Switch on tuning bits.
369 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200370 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
371 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700372
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700376
377 /*
378 * RF2420 chipset don't need any additional actions.
379 */
380 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
381 return;
382
383 /*
384 * For the RT2421 chipsets we need to write an invalid
385 * reference clock rate to activate auto_tune.
386 * After that we set the value back to the correct channel.
387 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200388 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700389 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200390 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700391
392 msleep(1);
393
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200394 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
395 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
396 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700397
398 msleep(1);
399
400 /*
401 * Switch off tuning bits.
402 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700405
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200406 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700408
409 /*
410 * Clear false CRC during channel switch.
411 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200412 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700413}
414
415static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
416{
417 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
418}
419
420static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200421 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700422{
423 u8 r1;
424 u8 r4;
425
426 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
427 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
428
429 /*
430 * Configure the TX antenna.
431 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200432 switch (ant->tx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700433 case ANTENNA_HW_DIVERSITY:
434 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
435 break;
436 case ANTENNA_A:
437 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
438 break;
Ivo van Doorn39e75852007-10-13 16:26:27 +0200439 case ANTENNA_SW_DIVERSITY:
440 /*
441 * NOTE: We should never come here because rt2x00lib is
442 * supposed to catch this and send us the correct antenna
443 * explicitely. However we are nog going to bug about this.
444 * Instead, just default to antenna B.
445 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700446 case ANTENNA_B:
447 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
448 break;
449 }
450
451 /*
452 * Configure the RX antenna.
453 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200454 switch (ant->rx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700455 case ANTENNA_HW_DIVERSITY:
456 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
457 break;
458 case ANTENNA_A:
459 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
460 break;
Ivo van Doorn39e75852007-10-13 16:26:27 +0200461 case ANTENNA_SW_DIVERSITY:
462 /*
463 * NOTE: We should never come here because rt2x00lib is
464 * supposed to catch this and send us the correct antenna
465 * explicitely. However we are nog going to bug about this.
466 * Instead, just default to antenna B.
467 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700468 case ANTENNA_B:
469 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
470 break;
471 }
472
473 rt2400pci_bbp_write(rt2x00dev, 4, r4);
474 rt2400pci_bbp_write(rt2x00dev, 1, r1);
475}
476
477static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200478 struct rt2x00lib_conf *libconf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700479{
480 u32 reg;
481
482 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200483 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700484 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
485
486 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200487 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
488 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700489 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
490
491 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200492 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
493 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700494 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
495
496 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
497 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
498 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
499 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
500
501 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200502 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
503 libconf->conf->beacon_int * 16);
504 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
505 libconf->conf->beacon_int * 16);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700506 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
507}
508
509static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100510 struct rt2x00lib_conf *libconf,
511 const unsigned int flags)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700512{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700513 if (flags & CONFIG_UPDATE_PHYMODE)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200514 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700515 if (flags & CONFIG_UPDATE_CHANNEL)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200516 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700517 if (flags & CONFIG_UPDATE_TXPOWER)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200518 rt2400pci_config_txpower(rt2x00dev,
519 libconf->conf->power_level);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700520 if (flags & CONFIG_UPDATE_ANTENNA)
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200521 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700522 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200523 rt2400pci_config_duration(rt2x00dev, libconf);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700524}
525
526static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500527 const int cw_min, const int cw_max)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700528{
529 u32 reg;
530
531 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500532 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
533 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700534 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
535}
536
537/*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700538 * Link tuning
539 */
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200540static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
541 struct link_qual *qual)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700542{
543 u32 reg;
544 u8 bbp;
545
546 /*
547 * Update FCS error count from register.
548 */
549 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200550 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700551
552 /*
553 * Update False CCA count from register.
554 */
555 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200556 qual->false_cca = bbp;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700557}
558
559static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
560{
561 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
562 rt2x00dev->link.vgc_level = 0x08;
563}
564
565static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
566{
567 u8 reg;
568
569 /*
570 * The link tuner should not run longer then 60 seconds,
571 * and should run once every 2 seconds.
572 */
573 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
574 return;
575
576 /*
577 * Base r13 link tuning on the false cca count.
578 */
579 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
580
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200581 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700582 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
583 rt2x00dev->link.vgc_level = reg;
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200584 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700585 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
586 rt2x00dev->link.vgc_level = reg;
587 }
588}
589
590/*
591 * Initialization functions.
592 */
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100593static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500594 struct queue_entry *entry)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700595{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500596 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700597 u32 word;
598
Ivo van Doorn181d6902008-02-05 16:42:23 -0500599 rt2x00_desc_read(priv_rx->desc, 2, &word);
600 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size);
601 rt2x00_desc_write(priv_rx->desc, 2, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700602
Ivo van Doorn181d6902008-02-05 16:42:23 -0500603 rt2x00_desc_read(priv_rx->desc, 1, &word);
604 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
605 rt2x00_desc_write(priv_rx->desc, 1, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700606
Ivo van Doorn181d6902008-02-05 16:42:23 -0500607 rt2x00_desc_read(priv_rx->desc, 0, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100608 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500609 rt2x00_desc_write(priv_rx->desc, 0, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700610}
611
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100612static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500613 struct queue_entry *entry)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700614{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500615 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700616 u32 word;
617
Ivo van Doorn181d6902008-02-05 16:42:23 -0500618 rt2x00_desc_read(priv_tx->desc, 1, &word);
619 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
620 rt2x00_desc_write(priv_tx->desc, 1, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700621
Ivo van Doorn181d6902008-02-05 16:42:23 -0500622 rt2x00_desc_read(priv_tx->desc, 2, &word);
623 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
624 entry->queue->data_size);
625 rt2x00_desc_write(priv_tx->desc, 2, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700626
Ivo van Doorn181d6902008-02-05 16:42:23 -0500627 rt2x00_desc_read(priv_tx->desc, 0, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100628 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
629 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500630 rt2x00_desc_write(priv_tx->desc, 0, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700631}
632
Ivo van Doorn181d6902008-02-05 16:42:23 -0500633static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700634{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500635 struct queue_entry_priv_pci_rx *priv_rx;
636 struct queue_entry_priv_pci_tx *priv_tx;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700637 u32 reg;
638
639 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700640 * Initialize registers.
641 */
642 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500643 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
644 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
645 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
646 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700647 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
648
Ivo van Doorn181d6902008-02-05 16:42:23 -0500649 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700650 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500651 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700652 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
653
Ivo van Doorn181d6902008-02-05 16:42:23 -0500654 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700655 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500656 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700657 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
658
Ivo van Doorn181d6902008-02-05 16:42:23 -0500659 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700660 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500661 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700662 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
663
Ivo van Doorn181d6902008-02-05 16:42:23 -0500664 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700665 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500666 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700667 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
668
669 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
670 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500671 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700672 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
673
Ivo van Doorn181d6902008-02-05 16:42:23 -0500674 priv_rx = rt2x00dev->rx->entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700675 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500676 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700677 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
678
679 return 0;
680}
681
682static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
683{
684 u32 reg;
685
686 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
687 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
688 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
689 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
690
691 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
692 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
693 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
694 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
695 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
696
697 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
698 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
699 (rt2x00dev->rx->data_size / 128));
700 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
701
Ivo van Doorna9450b72008-02-03 15:53:40 +0100702 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
703 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
704 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
705 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
706
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700707 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
708
709 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
710 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
711 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
712 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
713 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
714 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
715
716 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
717 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
718 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
719 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
720 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
721 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
722 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
723 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
724
725 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
726
727 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
728 return -EBUSY;
729
730 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
731 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
732
733 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
734 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
735 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
736
737 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
738 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
739 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
740 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
741 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
742 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
743
744 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
745 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
746 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
747 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
748 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
749
750 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
751 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
752 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
753 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
754
755 /*
756 * We must clear the FCS and FIFO error count.
757 * These registers are cleared on read,
758 * so we may pass a useless variable to store the value.
759 */
760 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
761 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
762
763 return 0;
764}
765
766static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
767{
768 unsigned int i;
769 u16 eeprom;
770 u8 reg_id;
771 u8 value;
772
773 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
774 rt2400pci_bbp_read(rt2x00dev, 0, &value);
775 if ((value != 0xff) && (value != 0x00))
776 goto continue_csr_init;
777 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
778 udelay(REGISTER_BUSY_DELAY);
779 }
780
781 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
782 return -EACCES;
783
784continue_csr_init:
785 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
786 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
787 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
788 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
789 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
790 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
791 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
792 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
793 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
794 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
795 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
796 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
797 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
798 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
799
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700800 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
801 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
802
803 if (eeprom != 0xffff && eeprom != 0x0000) {
804 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
805 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700806 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
807 }
808 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700809
810 return 0;
811}
812
813/*
814 * Device state switch handlers.
815 */
816static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
817 enum dev_state state)
818{
819 u32 reg;
820
821 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
822 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
823 state == STATE_RADIO_RX_OFF);
824 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
825}
826
827static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
828 enum dev_state state)
829{
830 int mask = (state == STATE_RADIO_IRQ_OFF);
831 u32 reg;
832
833 /*
834 * When interrupts are being enabled, the interrupt registers
835 * should clear the register to assure a clean state.
836 */
837 if (state == STATE_RADIO_IRQ_ON) {
838 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
839 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
840 }
841
842 /*
843 * Only toggle the interrupts bits we are going to use.
844 * Non-checked interrupt bits are disabled by default.
845 */
846 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
847 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
848 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
849 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
850 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
851 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
852 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
853}
854
855static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
856{
857 /*
858 * Initialize all registers.
859 */
Ivo van Doorn181d6902008-02-05 16:42:23 -0500860 if (rt2400pci_init_queues(rt2x00dev) ||
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700861 rt2400pci_init_registers(rt2x00dev) ||
862 rt2400pci_init_bbp(rt2x00dev)) {
863 ERROR(rt2x00dev, "Register initialization failed.\n");
864 return -EIO;
865 }
866
867 /*
868 * Enable interrupts.
869 */
870 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
871
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700872 return 0;
873}
874
875static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
876{
877 u32 reg;
878
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700879 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
880
881 /*
882 * Disable synchronisation.
883 */
884 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
885
886 /*
887 * Cancel RX and TX.
888 */
889 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
890 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
891 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
892
893 /*
894 * Disable interrupts.
895 */
896 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
897}
898
899static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
900 enum dev_state state)
901{
902 u32 reg;
903 unsigned int i;
904 char put_to_sleep;
905 char bbp_state;
906 char rf_state;
907
908 put_to_sleep = (state != STATE_AWAKE);
909
910 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
911 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
912 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
913 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
914 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
915 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
916
917 /*
918 * Device is not guaranteed to be in the requested state yet.
919 * We must wait until the register indicates that the
920 * device has entered the correct state.
921 */
922 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
923 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
924 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
925 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
926 if (bbp_state == state && rf_state == state)
927 return 0;
928 msleep(10);
929 }
930
931 NOTICE(rt2x00dev, "Device failed to enter state %d, "
932 "current device state: bbp %d and rf %d.\n",
933 state, bbp_state, rf_state);
934
935 return -EBUSY;
936}
937
938static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
939 enum dev_state state)
940{
941 int retval = 0;
942
943 switch (state) {
944 case STATE_RADIO_ON:
945 retval = rt2400pci_enable_radio(rt2x00dev);
946 break;
947 case STATE_RADIO_OFF:
948 rt2400pci_disable_radio(rt2x00dev);
949 break;
950 case STATE_RADIO_RX_ON:
Ivo van Doorn61667d82008-02-25 23:15:05 +0100951 case STATE_RADIO_RX_ON_LINK:
952 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
953 break;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700954 case STATE_RADIO_RX_OFF:
Ivo van Doorn61667d82008-02-25 23:15:05 +0100955 case STATE_RADIO_RX_OFF_LINK:
956 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700957 break;
958 case STATE_DEEP_SLEEP:
959 case STATE_SLEEP:
960 case STATE_STANDBY:
961 case STATE_AWAKE:
962 retval = rt2400pci_set_state(rt2x00dev, state);
963 break;
964 default:
965 retval = -ENOTSUPP;
966 break;
967 }
968
969 return retval;
970}
971
972/*
973 * TX descriptor initialization
974 */
975static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
Ivo van Doorndd3193e2008-01-06 23:41:10 +0100976 struct sk_buff *skb,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500977 struct txentry_desc *txdesc,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700978 struct ieee80211_tx_control *control)
979{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500980 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
Ivo van Doorndd3193e2008-01-06 23:41:10 +0100981 __le32 *txd = skbdesc->desc;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700982 u32 word;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700983
984 /*
985 * Start writing the descriptor words.
986 */
987 rt2x00_desc_read(txd, 2, &word);
Ivo van Doorndd3193e2008-01-06 23:41:10 +0100988 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700989 rt2x00_desc_write(txd, 2, word);
990
991 rt2x00_desc_read(txd, 3, &word);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500992 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
Ivo van Doorn49da2602007-11-27 21:47:56 +0100993 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
994 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500995 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
Ivo van Doorn49da2602007-11-27 21:47:56 +0100996 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
997 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700998 rt2x00_desc_write(txd, 3, word);
999
1000 rt2x00_desc_read(txd, 4, &word);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001001 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
Ivo van Doorn49da2602007-11-27 21:47:56 +01001002 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1003 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001004 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
Ivo van Doorn49da2602007-11-27 21:47:56 +01001005 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1006 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001007 rt2x00_desc_write(txd, 4, word);
1008
1009 rt2x00_desc_read(txd, 0, &word);
1010 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1011 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1012 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001013 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001014 rt2x00_set_field32(&word, TXD_W0_ACK,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001015 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001016 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001017 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001018 rt2x00_set_field32(&word, TXD_W0_RTS,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001019 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1020 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001021 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1022 !!(control->flags &
1023 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1024 rt2x00_desc_write(txd, 0, word);
1025}
1026
1027/*
1028 * TX data initialization
1029 */
1030static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5957da42008-02-03 15:54:57 +01001031 const unsigned int queue)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001032{
1033 u32 reg;
1034
Ivo van Doorn5957da42008-02-03 15:54:57 +01001035 if (queue == RT2X00_BCN_QUEUE_BEACON) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001036 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1037 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1038 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1039 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1040 }
1041 return;
1042 }
1043
1044 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
Ivo van Doornddc827f2007-10-13 16:26:42 +02001045 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1046 (queue == IEEE80211_TX_QUEUE_DATA0));
1047 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1048 (queue == IEEE80211_TX_QUEUE_DATA1));
1049 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
Ivo van Doorn5957da42008-02-03 15:54:57 +01001050 (queue == RT2X00_BCN_QUEUE_ATIM));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001051 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1052}
1053
1054/*
1055 * RX control handlers
1056 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001057static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1058 struct rxdone_entry_desc *rxdesc)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001059{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001060 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001061 u32 word0;
1062 u32 word2;
1063
Ivo van Doorn181d6902008-02-05 16:42:23 -05001064 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1065 rt2x00_desc_read(priv_rx->desc, 2, &word2);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001066
Ivo van Doorn181d6902008-02-05 16:42:23 -05001067 rxdesc->flags = 0;
Johannes Berg4150c572007-09-17 01:29:23 -04001068 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
Ivo van Doorn181d6902008-02-05 16:42:23 -05001069 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
Johannes Berg4150c572007-09-17 01:29:23 -04001070 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
Ivo van Doorn181d6902008-02-05 16:42:23 -05001071 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001072
1073 /*
1074 * Obtain the status about this packet.
1075 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001076 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1077 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1078 entry->queue->rt2x00dev->rssi_offset;
1079 rxdesc->ofdm = 0;
1080 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1081 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001082}
1083
1084/*
1085 * Interrupt functions.
1086 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001087static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1088 const enum ieee80211_tx_queue queue_idx)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001089{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001090 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1091 struct queue_entry_priv_pci_tx *priv_tx;
1092 struct queue_entry *entry;
1093 struct txdone_entry_desc txdesc;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001094 u32 word;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001095
Ivo van Doorn181d6902008-02-05 16:42:23 -05001096 while (!rt2x00queue_empty(queue)) {
1097 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1098 priv_tx = entry->priv_data;
1099 rt2x00_desc_read(priv_tx->desc, 0, &word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001100
1101 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1102 !rt2x00_get_field32(word, TXD_W0_VALID))
1103 break;
1104
1105 /*
1106 * Obtain the status about this packet.
1107 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001108 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1109 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001110
Ivo van Doorn181d6902008-02-05 16:42:23 -05001111 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001112 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001113}
1114
1115static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1116{
1117 struct rt2x00_dev *rt2x00dev = dev_instance;
1118 u32 reg;
1119
1120 /*
1121 * Get the interrupt sources & saved to local variable.
1122 * Write register value back to clear pending interrupts.
1123 */
1124 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1125 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1126
1127 if (!reg)
1128 return IRQ_NONE;
1129
1130 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1131 return IRQ_HANDLED;
1132
1133 /*
1134 * Handle interrupts, walk through all bits
1135 * and run the tasks, the bits are checked in order of
1136 * priority.
1137 */
1138
1139 /*
1140 * 1 - Beacon timer expired interrupt.
1141 */
1142 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1143 rt2x00lib_beacondone(rt2x00dev);
1144
1145 /*
1146 * 2 - Rx ring done interrupt.
1147 */
1148 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1149 rt2x00pci_rxdone(rt2x00dev);
1150
1151 /*
1152 * 3 - Atim ring transmit done interrupt.
1153 */
1154 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
Ivo van Doorn5957da42008-02-03 15:54:57 +01001155 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001156
1157 /*
1158 * 4 - Priority ring transmit done interrupt.
1159 */
1160 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1161 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1162
1163 /*
1164 * 5 - Tx ring transmit done interrupt.
1165 */
1166 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1167 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1168
1169 return IRQ_HANDLED;
1170}
1171
1172/*
1173 * Device probe functions.
1174 */
1175static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1176{
1177 struct eeprom_93cx6 eeprom;
1178 u32 reg;
1179 u16 word;
1180 u8 *mac;
1181
1182 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1183
1184 eeprom.data = rt2x00dev;
1185 eeprom.register_read = rt2400pci_eepromregister_read;
1186 eeprom.register_write = rt2400pci_eepromregister_write;
1187 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1188 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1189 eeprom.reg_data_in = 0;
1190 eeprom.reg_data_out = 0;
1191 eeprom.reg_data_clock = 0;
1192 eeprom.reg_chip_select = 0;
1193
1194 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1195 EEPROM_SIZE / sizeof(u16));
1196
1197 /*
1198 * Start validation of the data that has been read.
1199 */
1200 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1201 if (!is_valid_ether_addr(mac)) {
Joe Perches0795af52007-10-03 17:59:30 -07001202 DECLARE_MAC_BUF(macbuf);
1203
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001204 random_ether_addr(mac);
Joe Perches0795af52007-10-03 17:59:30 -07001205 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001206 }
1207
1208 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1209 if (word == 0xffff) {
1210 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1211 return -EINVAL;
1212 }
1213
1214 return 0;
1215}
1216
1217static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1218{
1219 u32 reg;
1220 u16 value;
1221 u16 eeprom;
1222
1223 /*
1224 * Read EEPROM word for configuration.
1225 */
1226 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1227
1228 /*
1229 * Identify RF chipset.
1230 */
1231 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1232 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1233 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1234
1235 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1236 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1237 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1238 return -ENODEV;
1239 }
1240
1241 /*
1242 * Identify default antenna configuration.
1243 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001244 rt2x00dev->default_ant.tx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001245 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001246 rt2x00dev->default_ant.rx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001247 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1248
1249 /*
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001250 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1251 * I am not 100% sure about this, but the legacy drivers do not
1252 * indicate antenna swapping in software is required when
1253 * diversity is enabled.
1254 */
1255 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1256 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1257 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1258 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1259
1260 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001261 * Store led mode, for correct led behaviour.
1262 */
Ivo van Doorna9450b72008-02-03 15:53:40 +01001263#ifdef CONFIG_RT2400PCI_LEDS
1264 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1265
1266 switch (value) {
1267 case LED_MODE_ASUS:
1268 case LED_MODE_ALPHA:
1269 case LED_MODE_DEFAULT:
1270 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1271 break;
1272 case LED_MODE_TXRX_ACTIVITY:
1273 rt2x00dev->led_flags =
1274 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1275 break;
1276 case LED_MODE_SIGNAL_STRENGTH:
1277 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1278 break;
1279 }
1280#endif /* CONFIG_RT2400PCI_LEDS */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001281
1282 /*
1283 * Detect if this device has an hardware controlled radio.
1284 */
Ivo van Doorn81873e92007-10-06 14:14:06 +02001285#ifdef CONFIG_RT2400PCI_RFKILL
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001286 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
Ivo van Doorn066cb632007-09-25 20:55:39 +02001287 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
Ivo van Doorn81873e92007-10-06 14:14:06 +02001288#endif /* CONFIG_RT2400PCI_RFKILL */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001289
1290 /*
1291 * Check if the BBP tuning should be enabled.
1292 */
1293 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1294 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1295
1296 return 0;
1297}
1298
1299/*
1300 * RF value list for RF2420 & RF2421
1301 * Supports: 2.4 GHz
1302 */
1303static const struct rf_channel rf_vals_bg[] = {
1304 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1305 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1306 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1307 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1308 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1309 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1310 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1311 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1312 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1313 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1314 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1315 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1316 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1317 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1318};
1319
1320static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1321{
1322 struct hw_mode_spec *spec = &rt2x00dev->spec;
1323 u8 *txpower;
1324 unsigned int i;
1325
1326 /*
1327 * Initialize all hw fields.
1328 */
Johannes Berg4150c572007-09-17 01:29:23 -04001329 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001330 rt2x00dev->hw->extra_tx_headroom = 0;
1331 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1332 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1333 rt2x00dev->hw->queues = 2;
1334
1335 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1336 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1337 rt2x00_eeprom_addr(rt2x00dev,
1338 EEPROM_MAC_ADDR_0));
1339
1340 /*
1341 * Convert tx_power array in eeprom.
1342 */
1343 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1344 for (i = 0; i < 14; i++)
1345 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1346
1347 /*
1348 * Initialize hw_mode information.
1349 */
1350 spec->num_modes = 1;
1351 spec->num_rates = 4;
1352 spec->tx_power_a = NULL;
1353 spec->tx_power_bg = txpower;
1354 spec->tx_power_default = DEFAULT_TXPOWER;
1355
1356 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1357 spec->channels = rf_vals_bg;
1358}
1359
1360static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1361{
1362 int retval;
1363
1364 /*
1365 * Allocate eeprom data.
1366 */
1367 retval = rt2400pci_validate_eeprom(rt2x00dev);
1368 if (retval)
1369 return retval;
1370
1371 retval = rt2400pci_init_eeprom(rt2x00dev);
1372 if (retval)
1373 return retval;
1374
1375 /*
1376 * Initialize hw specifications.
1377 */
1378 rt2400pci_probe_hw_mode(rt2x00dev);
1379
1380 /*
Ivo van Doorn181d6902008-02-05 16:42:23 -05001381 * This device requires the atim queue
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001382 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001383 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001384
1385 /*
1386 * Set the rssi offset.
1387 */
1388 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1389
1390 return 0;
1391}
1392
1393/*
1394 * IEEE80211 stack callback functions.
1395 */
Johannes Berg4150c572007-09-17 01:29:23 -04001396static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1397 unsigned int changed_flags,
1398 unsigned int *total_flags,
1399 int mc_count,
1400 struct dev_addr_list *mc_list)
1401{
1402 struct rt2x00_dev *rt2x00dev = hw->priv;
Johannes Berg4150c572007-09-17 01:29:23 -04001403 u32 reg;
1404
1405 /*
1406 * Mask off any flags we are going to ignore from
1407 * the total_flags field.
1408 */
1409 *total_flags &=
1410 FIF_ALLMULTI |
1411 FIF_FCSFAIL |
1412 FIF_PLCPFAIL |
1413 FIF_CONTROL |
1414 FIF_OTHER_BSS |
1415 FIF_PROMISC_IN_BSS;
1416
1417 /*
1418 * Apply some rules to the filters:
1419 * - Some filters imply different filters to be set.
1420 * - Some things we can't filter out at all.
Johannes Berg4150c572007-09-17 01:29:23 -04001421 */
1422 *total_flags |= FIF_ALLMULTI;
Ivo van Doorn5886d0d2007-10-06 14:13:38 +02001423 if (*total_flags & FIF_OTHER_BSS ||
1424 *total_flags & FIF_PROMISC_IN_BSS)
Johannes Berg4150c572007-09-17 01:29:23 -04001425 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
Johannes Berg4150c572007-09-17 01:29:23 -04001426
1427 /*
1428 * Check if there is any work left for us.
1429 */
Ivo van Doorn3c4f2082008-01-06 23:40:49 +01001430 if (rt2x00dev->packet_filter == *total_flags)
Johannes Berg4150c572007-09-17 01:29:23 -04001431 return;
Ivo van Doorn3c4f2082008-01-06 23:40:49 +01001432 rt2x00dev->packet_filter = *total_flags;
Johannes Berg4150c572007-09-17 01:29:23 -04001433
1434 /*
1435 * Start configuration steps.
1436 * Note that the version error will always be dropped
1437 * since there is no filter for it at this time.
1438 */
1439 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1440 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1441 !(*total_flags & FIF_FCSFAIL));
1442 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1443 !(*total_flags & FIF_PLCPFAIL));
1444 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1445 !(*total_flags & FIF_CONTROL));
1446 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1447 !(*total_flags & FIF_PROMISC_IN_BSS));
1448 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1449 !(*total_flags & FIF_PROMISC_IN_BSS));
1450 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1451 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1452}
1453
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001454static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1455 u32 short_retry, u32 long_retry)
1456{
1457 struct rt2x00_dev *rt2x00dev = hw->priv;
1458 u32 reg;
1459
1460 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1461 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1462 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1463 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1464
1465 return 0;
1466}
1467
1468static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1469 int queue,
1470 const struct ieee80211_tx_queue_params *params)
1471{
1472 struct rt2x00_dev *rt2x00dev = hw->priv;
1473
1474 /*
1475 * We don't support variating cw_min and cw_max variables
1476 * per queue. So by default we only configure the TX queue,
1477 * and ignore all other configurations.
1478 */
1479 if (queue != IEEE80211_TX_QUEUE_DATA0)
1480 return -EINVAL;
1481
1482 if (rt2x00mac_conf_tx(hw, queue, params))
1483 return -EINVAL;
1484
1485 /*
1486 * Write configuration to register.
1487 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001488 rt2400pci_config_cw(rt2x00dev,
1489 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001490
1491 return 0;
1492}
1493
1494static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1495{
1496 struct rt2x00_dev *rt2x00dev = hw->priv;
1497 u64 tsf;
1498 u32 reg;
1499
1500 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1501 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1502 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1503 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1504
1505 return tsf;
1506}
1507
1508static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1509{
1510 struct rt2x00_dev *rt2x00dev = hw->priv;
1511
1512 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1513 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1514}
1515
Ivo van Doorn5957da42008-02-03 15:54:57 +01001516static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1517 struct ieee80211_tx_control *control)
1518{
1519 struct rt2x00_dev *rt2x00dev = hw->priv;
1520 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1521 struct queue_entry_priv_pci_tx *priv_tx;
1522 struct skb_frame_desc *skbdesc;
1523
1524 if (unlikely(!intf->beacon))
1525 return -ENOBUFS;
1526
1527 priv_tx = intf->beacon->priv_data;
1528
1529 /*
1530 * Fill in skb descriptor
1531 */
1532 skbdesc = get_skb_frame_desc(skb);
1533 memset(skbdesc, 0, sizeof(*skbdesc));
Ivo van Doornbaf26a72008-02-17 17:32:08 +01001534 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
Ivo van Doorn5957da42008-02-03 15:54:57 +01001535 skbdesc->data = skb->data;
1536 skbdesc->data_len = skb->len;
1537 skbdesc->desc = priv_tx->desc;
1538 skbdesc->desc_len = intf->beacon->queue->desc_size;
1539 skbdesc->entry = intf->beacon;
1540
1541 /*
1542 * mac80211 doesn't provide the control->queue variable
1543 * for beacons. Set our own queue identification so
1544 * it can be used during descriptor initialization.
1545 */
1546 control->queue = RT2X00_BCN_QUEUE_BEACON;
1547 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1548
1549 /*
1550 * Enable beacon generation.
1551 * Write entire beacon with descriptor to register,
1552 * and kick the beacon generator.
1553 */
1554 memcpy(priv_tx->data, skb->data, skb->len);
1555 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1556
1557 return 0;
1558}
1559
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001560static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1561{
1562 struct rt2x00_dev *rt2x00dev = hw->priv;
1563 u32 reg;
1564
1565 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1566 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1567}
1568
1569static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1570 .tx = rt2x00mac_tx,
Johannes Berg4150c572007-09-17 01:29:23 -04001571 .start = rt2x00mac_start,
1572 .stop = rt2x00mac_stop,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001573 .add_interface = rt2x00mac_add_interface,
1574 .remove_interface = rt2x00mac_remove_interface,
1575 .config = rt2x00mac_config,
1576 .config_interface = rt2x00mac_config_interface,
Johannes Berg4150c572007-09-17 01:29:23 -04001577 .configure_filter = rt2400pci_configure_filter,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001578 .get_stats = rt2x00mac_get_stats,
1579 .set_retry_limit = rt2400pci_set_retry_limit,
Johannes Berg471b3ef2007-12-28 14:32:58 +01001580 .bss_info_changed = rt2x00mac_bss_info_changed,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001581 .conf_tx = rt2400pci_conf_tx,
1582 .get_tx_stats = rt2x00mac_get_tx_stats,
1583 .get_tsf = rt2400pci_get_tsf,
1584 .reset_tsf = rt2400pci_reset_tsf,
Ivo van Doorn5957da42008-02-03 15:54:57 +01001585 .beacon_update = rt2400pci_beacon_update,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001586 .tx_last_beacon = rt2400pci_tx_last_beacon,
1587};
1588
1589static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1590 .irq_handler = rt2400pci_interrupt,
1591 .probe_hw = rt2400pci_probe_hw,
1592 .initialize = rt2x00pci_initialize,
1593 .uninitialize = rt2x00pci_uninitialize,
Ivo van Doorn837e7f22008-01-06 23:41:45 +01001594 .init_rxentry = rt2400pci_init_rxentry,
1595 .init_txentry = rt2400pci_init_txentry,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001596 .set_device_state = rt2400pci_set_device_state,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001597 .rfkill_poll = rt2400pci_rfkill_poll,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001598 .link_stats = rt2400pci_link_stats,
1599 .reset_tuner = rt2400pci_reset_tuner,
1600 .link_tuner = rt2400pci_link_tuner,
Ivo van Doorna9450b72008-02-03 15:53:40 +01001601 .led_brightness = rt2400pci_led_brightness,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001602 .write_tx_desc = rt2400pci_write_tx_desc,
1603 .write_tx_data = rt2x00pci_write_tx_data,
1604 .kick_tx_queue = rt2400pci_kick_tx_queue,
1605 .fill_rxdone = rt2400pci_fill_rxdone,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01001606 .config_intf = rt2400pci_config_intf,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +02001607 .config_preamble = rt2400pci_config_preamble,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001608 .config = rt2400pci_config,
1609};
1610
Ivo van Doorn181d6902008-02-05 16:42:23 -05001611static const struct data_queue_desc rt2400pci_queue_rx = {
1612 .entry_num = RX_ENTRIES,
1613 .data_size = DATA_FRAME_SIZE,
1614 .desc_size = RXD_DESC_SIZE,
1615 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1616};
1617
1618static const struct data_queue_desc rt2400pci_queue_tx = {
1619 .entry_num = TX_ENTRIES,
1620 .data_size = DATA_FRAME_SIZE,
1621 .desc_size = TXD_DESC_SIZE,
1622 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1623};
1624
1625static const struct data_queue_desc rt2400pci_queue_bcn = {
1626 .entry_num = BEACON_ENTRIES,
1627 .data_size = MGMT_FRAME_SIZE,
1628 .desc_size = TXD_DESC_SIZE,
1629 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1630};
1631
1632static const struct data_queue_desc rt2400pci_queue_atim = {
1633 .entry_num = ATIM_ENTRIES,
1634 .data_size = DATA_FRAME_SIZE,
1635 .desc_size = TXD_DESC_SIZE,
1636 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1637};
1638
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001639static const struct rt2x00_ops rt2400pci_ops = {
Ivo van Doorn23601572007-11-27 21:47:34 +01001640 .name = KBUILD_MODNAME,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01001641 .max_sta_intf = 1,
1642 .max_ap_intf = 1,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001643 .eeprom_size = EEPROM_SIZE,
1644 .rf_size = RF_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001645 .rx = &rt2400pci_queue_rx,
1646 .tx = &rt2400pci_queue_tx,
1647 .bcn = &rt2400pci_queue_bcn,
1648 .atim = &rt2400pci_queue_atim,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001649 .lib = &rt2400pci_rt2x00_ops,
1650 .hw = &rt2400pci_mac80211_ops,
1651#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1652 .debugfs = &rt2400pci_rt2x00debug,
1653#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1654};
1655
1656/*
1657 * RT2400pci module information.
1658 */
1659static struct pci_device_id rt2400pci_device_table[] = {
1660 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1661 { 0, }
1662};
1663
1664MODULE_AUTHOR(DRV_PROJECT);
1665MODULE_VERSION(DRV_VERSION);
1666MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1667MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1668MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1669MODULE_LICENSE("GPL");
1670
1671static struct pci_driver rt2400pci_driver = {
Ivo van Doorn23601572007-11-27 21:47:34 +01001672 .name = KBUILD_MODNAME,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001673 .id_table = rt2400pci_device_table,
1674 .probe = rt2x00pci_probe,
1675 .remove = __devexit_p(rt2x00pci_remove),
1676 .suspend = rt2x00pci_suspend,
1677 .resume = rt2x00pci_resume,
1678};
1679
1680static int __init rt2400pci_init(void)
1681{
1682 return pci_register_driver(&rt2400pci_driver);
1683}
1684
1685static void __exit rt2400pci_exit(void)
1686{
1687 pci_unregister_driver(&rt2400pci_driver);
1688}
1689
1690module_init(rt2400pci_init);
1691module_exit(rt2400pci_exit);