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Pierre Ossmand129bce2006-03-24 03:18:17 -08001/*
Pierre Ossman70f10482007-07-11 20:04:50 +02002 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
Pierre Ossmand129bce2006-03-24 03:18:17 -08003 *
Pierre Ossmanb69c9052008-03-08 23:44:25 +01004 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
Pierre Ossmand129bce2006-03-24 03:18:17 -08005 *
6 * This program is free software; you can redistribute it and/or modify
Pierre Ossman643f7202006-09-30 23:27:52 -07007 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
Pierre Ossman84c46a52007-12-02 19:58:16 +010010 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
Pierre Ossmand129bce2006-03-24 03:18:17 -080014 */
15
Pierre Ossmand129bce2006-03-24 03:18:17 -080016#include <linux/delay.h>
17#include <linux/highmem.h>
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +010018#include <linux/io.h>
Paul Gortmaker88b47672011-07-03 15:15:51 -040019#include <linux/module.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080020#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Ralf Baechle11763602007-10-23 20:42:11 +020022#include <linux/scatterlist.h>
Marek Szyprowski9bea3c82010-08-10 18:01:59 -070023#include <linux/regulator/consumer.h>
Adrian Hunter66fd8ad2011-10-03 15:33:34 +030024#include <linux/pm_runtime.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080025
Pierre Ossman2f730fe2008-03-17 10:29:38 +010026#include <linux/leds.h>
27
Aries Lee22113ef2010-12-15 08:14:24 +010028#include <linux/mmc/mmc.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080029#include <linux/mmc/host.h>
Aaron Lu473b0952012-07-03 17:27:49 +080030#include <linux/mmc/card.h>
Pierre Ossmand129bce2006-03-24 03:18:17 -080031
Pierre Ossmand129bce2006-03-24 03:18:17 -080032#include "sdhci.h"
33
34#define DRIVER_NAME "sdhci"
Pierre Ossmand129bce2006-03-24 03:18:17 -080035
Pierre Ossmand129bce2006-03-24 03:18:17 -080036#define DBG(f, x...) \
Russell Kingc6563172006-03-29 09:30:20 +010037 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
Pierre Ossmand129bce2006-03-24 03:18:17 -080038
Pierre Ossmanf9134312008-12-21 17:01:48 +010039#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40 defined(CONFIG_MMC_SDHCI_MODULE))
41#define SDHCI_USE_LEDS_CLASS
42#endif
43
Arindam Nathb513ea22011-05-05 12:19:04 +053044#define MAX_TUNING_LOOP 40
45
Pierre Ossmandf673b22006-06-30 02:22:31 -070046static unsigned int debug_quirks = 0;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +030047static unsigned int debug_quirks2;
Pierre Ossman67435272006-06-30 02:22:31 -070048
Pierre Ossmand129bce2006-03-24 03:18:17 -080049static void sdhci_finish_data(struct sdhci_host *);
50
51static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52static void sdhci_finish_command(struct sdhci_host *);
Girish K S069c9f12012-01-06 09:56:39 +053053static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +053054static void sdhci_tuning_timer(unsigned long data);
Pierre Ossmand129bce2006-03-24 03:18:17 -080055
Adrian Hunter66fd8ad2011-10-03 15:33:34 +030056#ifdef CONFIG_PM_RUNTIME
57static int sdhci_runtime_pm_get(struct sdhci_host *host);
58static int sdhci_runtime_pm_put(struct sdhci_host *host);
59#else
60static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
61{
62 return 0;
63}
64static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
65{
66 return 0;
67}
68#endif
69
Pierre Ossmand129bce2006-03-24 03:18:17 -080070static void sdhci_dumpregs(struct sdhci_host *host)
71{
Girish K Sa3c76eb2011-10-11 11:44:09 +053072 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
Philip Rakity412ab652010-09-22 15:25:13 -070073 mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -080074
Girish K Sa3c76eb2011-10-11 11:44:09 +053075 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030076 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
Girish K Sa3c76eb2011-10-11 11:44:09 +053078 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030079 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
Girish K Sa3c76eb2011-10-11 11:44:09 +053081 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030082 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
Girish K Sa3c76eb2011-10-11 11:44:09 +053084 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030085 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
Girish K Sa3c76eb2011-10-11 11:44:09 +053087 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030088 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
Girish K Sa3c76eb2011-10-11 11:44:09 +053090 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030091 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
Girish K Sa3c76eb2011-10-11 11:44:09 +053093 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030094 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
Girish K Sa3c76eb2011-10-11 11:44:09 +053096 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +030097 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
Girish K Sa3c76eb2011-10-11 11:44:09 +053099 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
Girish K Sa3c76eb2011-10-11 11:44:09 +0530102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300103 sdhci_readl(host, SDHCI_CAPABILITIES),
Philip Rakitye8120ad2010-11-30 00:55:23 -0500104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
Girish K Sa3c76eb2011-10-11 11:44:09 +0530105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
Philip Rakitye8120ad2010-11-30 00:55:23 -0500106 sdhci_readw(host, SDHCI_COMMAND),
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300107 sdhci_readl(host, SDHCI_MAX_CURRENT));
Girish K Sa3c76eb2011-10-11 11:44:09 +0530108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
Arindam Nathf2119df2011-05-05 12:18:57 +0530109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
Pierre Ossmand129bce2006-03-24 03:18:17 -0800110
Ben Dooksbe3f4ae2009-06-08 23:33:52 +0100111 if (host->flags & SDHCI_USE_ADMA)
Girish K Sa3c76eb2011-10-11 11:44:09 +0530112 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
Ben Dooksbe3f4ae2009-06-08 23:33:52 +0100113 readl(host->ioaddr + SDHCI_ADMA_ERROR),
114 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
115
Girish K Sa3c76eb2011-10-11 11:44:09 +0530116 pr_debug(DRIVER_NAME ": ===========================================\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800117}
118
119/*****************************************************************************\
120 * *
121 * Low level functions *
122 * *
123\*****************************************************************************/
124
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300125static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
126{
127 u32 ier;
128
129 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
130 ier &= ~clear;
131 ier |= set;
132 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
134}
135
136static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
137{
138 sdhci_clear_set_irqs(host, 0, irqs);
139}
140
141static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
142{
143 sdhci_clear_set_irqs(host, irqs, 0);
144}
145
146static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147{
Shawn Guod25928d2011-06-21 22:41:48 +0800148 u32 present, irqs;
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300149
Adrian Hunterc79396c2011-12-27 15:48:42 +0200150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
Daniel Drake87b87a32012-04-10 00:14:20 +0100151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
Adrian Hunter66fd8ad2011-10-03 15:33:34 +0300152 return;
153
Shawn Guod25928d2011-06-21 22:41:48 +0800154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
157
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300158 if (enable)
159 sdhci_unmask_irqs(host, irqs);
160 else
161 sdhci_mask_irqs(host, irqs);
162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
Pierre Ossmand129bce2006-03-24 03:18:17 -0800174static void sdhci_reset(struct sdhci_host *host, u8 mask)
175{
Pierre Ossmane16514d82006-06-30 02:22:24 -0700176 unsigned long timeout;
Anton Vorontsov063a9db2009-03-17 00:14:02 +0300177 u32 uninitialized_var(ier);
Pierre Ossmane16514d82006-06-30 02:22:24 -0700178
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +0100179 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300180 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
Pierre Ossman8a4da142006-10-04 02:15:40 -0700181 SDHCI_CARD_PRESENT))
182 return;
183 }
184
Anton Vorontsov063a9db2009-03-17 00:14:02 +0300185 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
187
Philip Rakity393c1a32011-01-21 11:26:40 -0800188 if (host->ops->platform_reset_enter)
189 host->ops->platform_reset_enter(host, mask);
190
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300191 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800192
Pierre Ossmane16514d82006-06-30 02:22:24 -0700193 if (mask & SDHCI_RESET_ALL)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800194 host->clock = 0;
195
Pierre Ossmane16514d82006-06-30 02:22:24 -0700196 /* Wait max 100 ms */
197 timeout = 100;
198
199 /* hw clears the bit when it's done */
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300200 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
Pierre Ossmane16514d82006-06-30 02:22:24 -0700201 if (timeout == 0) {
Girish K Sa3c76eb2011-10-11 11:44:09 +0530202 pr_err("%s: Reset 0x%x never completed.\n",
Pierre Ossmane16514d82006-06-30 02:22:24 -0700203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
205 return;
206 }
207 timeout--;
208 mdelay(1);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800209 }
Anton Vorontsov063a9db2009-03-17 00:14:02 +0300210
Philip Rakity393c1a32011-01-21 11:26:40 -0800211 if (host->ops->platform_reset_exit)
212 host->ops->platform_reset_exit(host, mask);
213
Anton Vorontsov063a9db2009-03-17 00:14:02 +0300214 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
Shaohui Xie3abc1e802011-12-29 16:33:00 +0800216
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219 host->ops->enable_dma(host);
220 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800221}
222
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800223static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
224
225static void sdhci_init(struct sdhci_host *host, int soft)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800226{
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800227 if (soft)
228 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
229 else
230 sdhci_reset(host, SDHCI_RESET_ALL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800231
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300232 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
Pierre Ossman3192a282006-06-30 02:22:26 -0700234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
Anton Vorontsov6aa943a2009-03-17 00:13:50 +0300236 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800237
238 if (soft) {
239 /* force clock reconfiguration */
240 host->clock = 0;
241 sdhci_set_ios(host->mmc, &host->mmc->ios);
242 }
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300243}
Pierre Ossmand129bce2006-03-24 03:18:17 -0800244
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300245static void sdhci_reinit(struct sdhci_host *host)
246{
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -0800247 sdhci_init(host, 0);
Aaron Lub67c6b42012-06-29 16:17:31 +0800248 /*
249 * Retuning stuffs are affected by different cards inserted and only
250 * applicable to UHS-I cards. So reset these fields to their initial
251 * value when card is removed.
252 */
253 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
254 host->tuning_mode == SDHCI_TUNING_MODE_1) {
255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
259 }
Anton Vorontsov7260cf52009-03-17 00:13:48 +0300260 sdhci_enable_card_detection(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800261}
262
263static void sdhci_activate_led(struct sdhci_host *host)
264{
265 u8 ctrl;
266
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800268 ctrl |= SDHCI_CTRL_LED;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800270}
271
272static void sdhci_deactivate_led(struct sdhci_host *host)
273{
274 u8 ctrl;
275
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800277 ctrl &= ~SDHCI_CTRL_LED;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800279}
280
Pierre Ossmanf9134312008-12-21 17:01:48 +0100281#ifdef SDHCI_USE_LEDS_CLASS
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100282static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
284{
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
286 unsigned long flags;
287
288 spin_lock_irqsave(&host->lock, flags);
289
Adrian Hunter66fd8ad2011-10-03 15:33:34 +0300290 if (host->runtime_suspended)
291 goto out;
292
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
295 else
296 sdhci_activate_led(host);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +0300297out:
Pierre Ossman2f730fe2008-03-17 10:29:38 +0100298 spin_unlock_irqrestore(&host->lock, flags);
299}
300#endif
301
Pierre Ossmand129bce2006-03-24 03:18:17 -0800302/*****************************************************************************\
303 * *
304 * Core functions *
305 * *
306\*****************************************************************************/
307
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100308static void sdhci_read_block_pio(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800309{
Pierre Ossman76591502008-07-21 00:32:11 +0200310 unsigned long flags;
311 size_t blksize, len, chunk;
Steven Noonan7244b852008-10-01 01:50:25 -0700312 u32 uninitialized_var(scratch);
Pierre Ossman76591502008-07-21 00:32:11 +0200313 u8 *buf;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800314
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100315 DBG("PIO reading\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800316
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100317 blksize = host->data->blksz;
Pierre Ossman76591502008-07-21 00:32:11 +0200318 chunk = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800319
Pierre Ossman76591502008-07-21 00:32:11 +0200320 local_irq_save(flags);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800321
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100322 while (blksize) {
Pierre Ossman76591502008-07-21 00:32:11 +0200323 if (!sg_miter_next(&host->sg_miter))
324 BUG();
Pierre Ossmand129bce2006-03-24 03:18:17 -0800325
Pierre Ossman76591502008-07-21 00:32:11 +0200326 len = min(host->sg_miter.length, blksize);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800327
Pierre Ossman76591502008-07-21 00:32:11 +0200328 blksize -= len;
329 host->sg_miter.consumed = len;
Alex Dubov14d836e2007-04-13 19:04:38 +0200330
Pierre Ossman76591502008-07-21 00:32:11 +0200331 buf = host->sg_miter.addr;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800332
Pierre Ossman76591502008-07-21 00:32:11 +0200333 while (len) {
334 if (chunk == 0) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300335 scratch = sdhci_readl(host, SDHCI_BUFFER);
Pierre Ossman76591502008-07-21 00:32:11 +0200336 chunk = 4;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800337 }
Pierre Ossman76591502008-07-21 00:32:11 +0200338
339 *buf = scratch & 0xFF;
340
341 buf++;
342 scratch >>= 8;
343 chunk--;
344 len--;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800345 }
346 }
Pierre Ossman76591502008-07-21 00:32:11 +0200347
348 sg_miter_stop(&host->sg_miter);
349
350 local_irq_restore(flags);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100351}
Pierre Ossmand129bce2006-03-24 03:18:17 -0800352
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100353static void sdhci_write_block_pio(struct sdhci_host *host)
354{
Pierre Ossman76591502008-07-21 00:32:11 +0200355 unsigned long flags;
356 size_t blksize, len, chunk;
357 u32 scratch;
358 u8 *buf;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100359
360 DBG("PIO writing\n");
361
362 blksize = host->data->blksz;
Pierre Ossman76591502008-07-21 00:32:11 +0200363 chunk = 0;
364 scratch = 0;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100365
Pierre Ossman76591502008-07-21 00:32:11 +0200366 local_irq_save(flags);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100367
368 while (blksize) {
Pierre Ossman76591502008-07-21 00:32:11 +0200369 if (!sg_miter_next(&host->sg_miter))
370 BUG();
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100371
Pierre Ossman76591502008-07-21 00:32:11 +0200372 len = min(host->sg_miter.length, blksize);
Alex Dubov14d836e2007-04-13 19:04:38 +0200373
Pierre Ossman76591502008-07-21 00:32:11 +0200374 blksize -= len;
375 host->sg_miter.consumed = len;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100376
Pierre Ossman76591502008-07-21 00:32:11 +0200377 buf = host->sg_miter.addr;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100378
Pierre Ossman76591502008-07-21 00:32:11 +0200379 while (len) {
380 scratch |= (u32)*buf << (chunk * 8);
381
382 buf++;
383 chunk++;
384 len--;
385
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300387 sdhci_writel(host, scratch, SDHCI_BUFFER);
Pierre Ossman76591502008-07-21 00:32:11 +0200388 chunk = 0;
389 scratch = 0;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100390 }
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100391 }
392 }
Pierre Ossman76591502008-07-21 00:32:11 +0200393
394 sg_miter_stop(&host->sg_miter);
395
396 local_irq_restore(flags);
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100397}
398
399static void sdhci_transfer_pio(struct sdhci_host *host)
400{
401 u32 mask;
402
403 BUG_ON(!host->data);
404
Pierre Ossman76591502008-07-21 00:32:11 +0200405 if (host->blocks == 0)
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100406 return;
407
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
410 else
411 mask = SDHCI_SPACE_AVAILABLE;
412
Pierre Ossman4a3cba32008-07-29 00:11:16 +0200413 /*
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
417 */
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
420 mask = ~0;
421
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Anton Vorontsov3e3bf202009-03-17 00:14:00 +0300423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
424 udelay(100);
425
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
428 else
429 sdhci_write_block_pio(host);
430
Pierre Ossman76591502008-07-21 00:32:11 +0200431 host->blocks--;
432 if (host->blocks == 0)
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100433 break;
Pierre Ossmana406f5a2006-07-02 16:50:59 +0100434 }
435
436 DBG("PIO transfer complete.\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -0800437}
438
Pierre Ossman2134a922008-06-28 18:28:51 +0200439static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
440{
441 local_irq_save(*flags);
Cong Wang482fce92011-11-27 13:27:00 +0800442 return kmap_atomic(sg_page(sg)) + sg->offset;
Pierre Ossman2134a922008-06-28 18:28:51 +0200443}
444
445static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446{
Cong Wang482fce92011-11-27 13:27:00 +0800447 kunmap_atomic(buffer);
Pierre Ossman2134a922008-06-28 18:28:51 +0200448 local_irq_restore(*flags);
449}
450
Ben Dooks118cd172010-03-05 13:43:26 -0800451static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
452{
Ben Dooks9e506f32010-03-05 13:43:29 -0800453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
Ben Dooks118cd172010-03-05 13:43:26 -0800455
Ben Dooks9e506f32010-03-05 13:43:29 -0800456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
Ben Dooks118cd172010-03-05 13:43:26 -0800458
Ben Dooks9e506f32010-03-05 13:43:29 -0800459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
461
462 dataddr[0] = cpu_to_le32(addr);
Ben Dooks118cd172010-03-05 13:43:26 -0800463}
464
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200465static int sdhci_adma_table_pre(struct sdhci_host *host,
Pierre Ossman2134a922008-06-28 18:28:51 +0200466 struct mmc_data *data)
467{
468 int direction;
469
470 u8 *desc;
471 u8 *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
491 /*
492 * The ADMA descriptor table is mapped further down as we
493 * need to fill it with data first.
494 */
495
496 host->align_addr = dma_map_single(mmc_dev(host->mmc),
497 host->align_buffer, 128 * 4, direction);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700498 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200499 goto fail;
Pierre Ossman2134a922008-06-28 18:28:51 +0200500 BUG_ON(host->align_addr & 0x3);
501
502 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
503 data->sg, data->sg_len, direction);
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200504 if (host->sg_count == 0)
505 goto unmap_align;
Pierre Ossman2134a922008-06-28 18:28:51 +0200506
507 desc = host->adma_desc;
508 align = host->align_buffer;
509
510 align_addr = host->align_addr;
511
512 for_each_sg(data->sg, sg, host->sg_count, i) {
513 addr = sg_dma_address(sg);
514 len = sg_dma_len(sg);
515
516 /*
517 * The SDHCI specification states that ADMA
518 * addresses must be 32-bit aligned. If they
519 * aren't, then we use a bounce buffer for
520 * the (up to three) bytes that screw up the
521 * alignment.
522 */
523 offset = (4 - (addr & 0x3)) & 0x3;
524 if (offset) {
525 if (data->flags & MMC_DATA_WRITE) {
526 buffer = sdhci_kmap_atomic(sg, &flags);
Pierre Ossman6cefd052008-07-21 00:45:15 +0200527 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
Pierre Ossman2134a922008-06-28 18:28:51 +0200528 memcpy(align, buffer, offset);
529 sdhci_kunmap_atomic(buffer, &flags);
530 }
531
Ben Dooks118cd172010-03-05 13:43:26 -0800532 /* tran, valid */
533 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
Pierre Ossman2134a922008-06-28 18:28:51 +0200534
535 BUG_ON(offset > 65536);
536
Pierre Ossman2134a922008-06-28 18:28:51 +0200537 align += 4;
538 align_addr += 4;
539
540 desc += 8;
541
542 addr += offset;
543 len -= offset;
544 }
545
Pierre Ossman2134a922008-06-28 18:28:51 +0200546 BUG_ON(len > 65536);
547
Ben Dooks118cd172010-03-05 13:43:26 -0800548 /* tran, valid */
549 sdhci_set_adma_desc(desc, addr, len, 0x21);
Pierre Ossman2134a922008-06-28 18:28:51 +0200550 desc += 8;
551
552 /*
553 * If this triggers then we have a calculation bug
554 * somewhere. :/
555 */
556 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
557 }
558
Thomas Abraham70764a92010-05-26 14:42:04 -0700559 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
560 /*
561 * Mark the last descriptor as the terminating descriptor
562 */
563 if (desc != host->adma_desc) {
564 desc -= 8;
565 desc[0] |= 0x2; /* end */
566 }
567 } else {
568 /*
569 * Add a terminating entry.
570 */
Pierre Ossman2134a922008-06-28 18:28:51 +0200571
Thomas Abraham70764a92010-05-26 14:42:04 -0700572 /* nop, end, valid */
573 sdhci_set_adma_desc(desc, 0, 0, 0x3);
574 }
Pierre Ossman2134a922008-06-28 18:28:51 +0200575
576 /*
577 * Resync align buffer as we might have changed it.
578 */
579 if (data->flags & MMC_DATA_WRITE) {
580 dma_sync_single_for_device(mmc_dev(host->mmc),
581 host->align_addr, 128 * 4, direction);
582 }
583
584 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
585 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
Pierre Ossman980167b2008-07-29 00:53:20 +0200586 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200587 goto unmap_entries;
Pierre Ossman2134a922008-06-28 18:28:51 +0200588 BUG_ON(host->adma_addr & 0x3);
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200589
590 return 0;
591
592unmap_entries:
593 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
594 data->sg_len, direction);
595unmap_align:
596 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
597 128 * 4, direction);
598fail:
599 return -EINVAL;
Pierre Ossman2134a922008-06-28 18:28:51 +0200600}
601
602static void sdhci_adma_table_post(struct sdhci_host *host,
603 struct mmc_data *data)
604{
605 int direction;
606
607 struct scatterlist *sg;
608 int i, size;
609 u8 *align;
610 char *buffer;
611 unsigned long flags;
612
613 if (data->flags & MMC_DATA_READ)
614 direction = DMA_FROM_DEVICE;
615 else
616 direction = DMA_TO_DEVICE;
617
618 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
619 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
620
621 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
622 128 * 4, direction);
623
624 if (data->flags & MMC_DATA_READ) {
625 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
626 data->sg_len, direction);
627
628 align = host->align_buffer;
629
630 for_each_sg(data->sg, sg, host->sg_count, i) {
631 if (sg_dma_address(sg) & 0x3) {
632 size = 4 - (sg_dma_address(sg) & 0x3);
633
634 buffer = sdhci_kmap_atomic(sg, &flags);
Pierre Ossman6cefd052008-07-21 00:45:15 +0200635 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
Pierre Ossman2134a922008-06-28 18:28:51 +0200636 memcpy(buffer, align, size);
637 sdhci_kunmap_atomic(buffer, &flags);
638
639 align += 4;
640 }
641 }
642 }
643
644 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
645 data->sg_len, direction);
646}
647
Andrei Warkentina3c77782011-04-11 16:13:42 -0500648static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
Pierre Ossmand129bce2006-03-24 03:18:17 -0800649{
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700650 u8 count;
Andrei Warkentina3c77782011-04-11 16:13:42 -0500651 struct mmc_data *data = cmd->data;
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700652 unsigned target_timeout, current_timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800653
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200654 /*
655 * If the host controller provides us with an incorrect timeout
656 * value, just skip the check and use 0xE. The hardware may take
657 * longer to time out, but that's much better than having a too-short
658 * timeout value.
659 */
Pierre Ossman11a2f1b2009-06-21 20:59:33 +0200660 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200661 return 0xE;
Pierre Ossmane538fbe2007-08-12 16:46:32 +0200662
Andrei Warkentina3c77782011-04-11 16:13:42 -0500663 /* Unspecified timeout, assume max */
664 if (!data && !cmd->cmd_timeout_ms)
665 return 0xE;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800666
Andrei Warkentina3c77782011-04-11 16:13:42 -0500667 /* timeout in us */
668 if (!data)
669 target_timeout = cmd->cmd_timeout_ms * 1000;
Andy Shevchenko78a2ca22011-08-03 18:35:59 +0300670 else {
671 target_timeout = data->timeout_ns / 1000;
672 if (host->clock)
673 target_timeout += data->timeout_clks / host->clock;
674 }
Anton Vorontsov81b39802009-09-22 16:45:13 -0700675
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700676 /*
677 * Figure out needed cycles.
678 * We do this in steps in order to fit inside a 32 bit int.
679 * The first step is the minimum timeout, which will have a
680 * minimum resolution of 6 bits:
681 * (1) 2^13*1000 > 2^22,
682 * (2) host->timeout_clk < 2^16
683 * =>
684 * (1) / (2) > 2^6
685 */
686 count = 0;
687 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
688 while (current_timeout < target_timeout) {
689 count++;
690 current_timeout <<= 1;
691 if (count >= 0xF)
692 break;
693 }
694
695 if (count >= 0xF) {
Chris Ball09eeff52012-06-01 10:39:45 -0400696 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
697 mmc_hostname(host->mmc), count, cmd->opcode);
Pierre Ossman1c8cde92006-06-30 02:22:25 -0700698 count = 0xE;
699 }
700
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200701 return count;
702}
703
Anton Vorontsov6aa943a2009-03-17 00:13:50 +0300704static void sdhci_set_transfer_irqs(struct sdhci_host *host)
705{
706 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
707 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
708
709 if (host->flags & SDHCI_REQ_USE_DMA)
710 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
711 else
712 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
713}
714
Andrei Warkentina3c77782011-04-11 16:13:42 -0500715static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200716{
717 u8 count;
Pierre Ossman2134a922008-06-28 18:28:51 +0200718 u8 ctrl;
Andrei Warkentina3c77782011-04-11 16:13:42 -0500719 struct mmc_data *data = cmd->data;
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200720 int ret;
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200721
722 WARN_ON(host->data);
723
Andrei Warkentina3c77782011-04-11 16:13:42 -0500724 if (data || (cmd->flags & MMC_RSP_BUSY)) {
725 count = sdhci_calc_timeout(host, cmd);
726 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
727 }
728
729 if (!data)
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200730 return;
731
732 /* Sanity checks */
733 BUG_ON(data->blksz * data->blocks > 524288);
734 BUG_ON(data->blksz > host->mmc->max_blk_size);
735 BUG_ON(data->blocks > 65535);
736
737 host->data = data;
738 host->data_early = 0;
Mikko Vinnif6a03cb2011-04-12 09:36:18 -0400739 host->data->bytes_xfered = 0;
Pierre Ossmanee53ab52008-07-05 00:25:15 +0200740
Richard Röjforsa13abc72009-09-22 16:45:30 -0700741 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +0100742 host->flags |= SDHCI_REQ_USE_DMA;
743
Pierre Ossman2134a922008-06-28 18:28:51 +0200744 /*
745 * FIXME: This doesn't account for merging when mapping the
746 * scatterlist.
747 */
748 if (host->flags & SDHCI_REQ_USE_DMA) {
749 int broken, i;
750 struct scatterlist *sg;
751
752 broken = 0;
753 if (host->flags & SDHCI_USE_ADMA) {
754 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
755 broken = 1;
756 } else {
757 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
758 broken = 1;
759 }
760
761 if (unlikely(broken)) {
762 for_each_sg(data->sg, sg, data->sg_len, i) {
763 if (sg->length & 0x3) {
764 DBG("Reverting to PIO because of "
765 "transfer size (%d)\n",
766 sg->length);
767 host->flags &= ~SDHCI_REQ_USE_DMA;
768 break;
769 }
770 }
771 }
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +0100772 }
773
774 /*
775 * The assumption here being that alignment is the same after
776 * translation to device address space.
777 */
Pierre Ossman2134a922008-06-28 18:28:51 +0200778 if (host->flags & SDHCI_REQ_USE_DMA) {
779 int broken, i;
780 struct scatterlist *sg;
781
782 broken = 0;
783 if (host->flags & SDHCI_USE_ADMA) {
784 /*
785 * As we use 3 byte chunks to work around
786 * alignment problems, we need to check this
787 * quirk.
788 */
789 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
790 broken = 1;
791 } else {
792 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
793 broken = 1;
794 }
795
796 if (unlikely(broken)) {
797 for_each_sg(data->sg, sg, data->sg_len, i) {
798 if (sg->offset & 0x3) {
799 DBG("Reverting to PIO because of "
800 "bad alignment\n");
801 host->flags &= ~SDHCI_REQ_USE_DMA;
802 break;
803 }
804 }
805 }
806 }
807
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200808 if (host->flags & SDHCI_REQ_USE_DMA) {
809 if (host->flags & SDHCI_USE_ADMA) {
810 ret = sdhci_adma_table_pre(host, data);
811 if (ret) {
812 /*
813 * This only happens when someone fed
814 * us an invalid request.
815 */
816 WARN_ON(1);
Pierre Ossmanebd6d352008-07-29 00:45:51 +0200817 host->flags &= ~SDHCI_REQ_USE_DMA;
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200818 } else {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300819 sdhci_writel(host, host->adma_addr,
820 SDHCI_ADMA_ADDRESS);
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200821 }
822 } else {
Tomas Winklerc8b3e022008-07-05 19:52:04 +0300823 int sg_cnt;
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200824
Tomas Winklerc8b3e022008-07-05 19:52:04 +0300825 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200826 data->sg, data->sg_len,
827 (data->flags & MMC_DATA_READ) ?
828 DMA_FROM_DEVICE :
829 DMA_TO_DEVICE);
Tomas Winklerc8b3e022008-07-05 19:52:04 +0300830 if (sg_cnt == 0) {
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200831 /*
832 * This only happens when someone fed
833 * us an invalid request.
834 */
835 WARN_ON(1);
Pierre Ossmanebd6d352008-07-29 00:45:51 +0200836 host->flags &= ~SDHCI_REQ_USE_DMA;
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200837 } else {
Pierre Ossman719a61b2008-07-22 13:23:23 +0200838 WARN_ON(sg_cnt != 1);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300839 sdhci_writel(host, sg_dma_address(data->sg),
840 SDHCI_DMA_ADDRESS);
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200841 }
842 }
843 }
844
Pierre Ossman2134a922008-06-28 18:28:51 +0200845 /*
846 * Always adjust the DMA selection as some controllers
847 * (e.g. JMicron) can't do PIO properly when the selection
848 * is ADMA.
849 */
850 if (host->version >= SDHCI_SPEC_200) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300851 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossman2134a922008-06-28 18:28:51 +0200852 ctrl &= ~SDHCI_CTRL_DMA_MASK;
853 if ((host->flags & SDHCI_REQ_USE_DMA) &&
854 (host->flags & SDHCI_USE_ADMA))
855 ctrl |= SDHCI_CTRL_ADMA32;
856 else
857 ctrl |= SDHCI_CTRL_SDMA;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300858 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +0100859 }
860
Pierre Ossman8f1934ce2008-06-30 21:15:49 +0200861 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
Sebastian Andrzej Siewiorda60a912009-06-18 09:33:32 +0200862 int flags;
863
864 flags = SG_MITER_ATOMIC;
865 if (host->data->flags & MMC_DATA_READ)
866 flags |= SG_MITER_TO_SG;
867 else
868 flags |= SG_MITER_FROM_SG;
869 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
Pierre Ossman76591502008-07-21 00:32:11 +0200870 host->blocks = data->blocks;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800871 }
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700872
Anton Vorontsov6aa943a2009-03-17 00:13:50 +0300873 sdhci_set_transfer_irqs(host);
874
Mikko Vinnif6a03cb2011-04-12 09:36:18 -0400875 /* Set the DMA boundary value and block size */
876 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
877 data->blksz), SDHCI_BLOCK_SIZE);
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300878 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700879}
880
881static void sdhci_set_transfer_mode(struct sdhci_host *host,
Andrei Warkentine89d4562011-05-23 15:06:37 -0500882 struct mmc_command *cmd)
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700883{
884 u16 mode;
Andrei Warkentine89d4562011-05-23 15:06:37 -0500885 struct mmc_data *data = cmd->data;
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700886
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700887 if (data == NULL)
888 return;
889
Pierre Ossmane538fbe2007-08-12 16:46:32 +0200890 WARN_ON(!host->data);
891
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700892 mode = SDHCI_TRNS_BLK_CNT_EN;
Andrei Warkentine89d4562011-05-23 15:06:37 -0500893 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
894 mode |= SDHCI_TRNS_MULTI;
895 /*
896 * If we are sending CMD23, CMD12 never gets sent
897 * on successful completion (so no Auto-CMD12).
898 */
899 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
900 mode |= SDHCI_TRNS_AUTO_CMD12;
Andrei Warkentin8edf63712011-05-23 15:06:39 -0500901 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
902 mode |= SDHCI_TRNS_AUTO_CMD23;
903 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
904 }
Jerry Huangc4512f72010-08-10 18:01:59 -0700905 }
Andrei Warkentin8edf63712011-05-23 15:06:39 -0500906
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700907 if (data->flags & MMC_DATA_READ)
908 mode |= SDHCI_TRNS_READ;
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +0100909 if (host->flags & SDHCI_REQ_USE_DMA)
Pierre Ossmanc7fa9962006-06-30 02:22:25 -0700910 mode |= SDHCI_TRNS_DMA;
911
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300912 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Pierre Ossmand129bce2006-03-24 03:18:17 -0800913}
914
915static void sdhci_finish_data(struct sdhci_host *host)
916{
917 struct mmc_data *data;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800918
919 BUG_ON(!host->data);
920
921 data = host->data;
922 host->data = NULL;
923
Pierre Ossmanc9fddbc2007-12-02 19:52:11 +0100924 if (host->flags & SDHCI_REQ_USE_DMA) {
Pierre Ossman2134a922008-06-28 18:28:51 +0200925 if (host->flags & SDHCI_USE_ADMA)
926 sdhci_adma_table_post(host, data);
927 else {
928 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
929 data->sg_len, (data->flags & MMC_DATA_READ) ?
930 DMA_FROM_DEVICE : DMA_TO_DEVICE);
931 }
Pierre Ossmand129bce2006-03-24 03:18:17 -0800932 }
933
934 /*
Pierre Ossmanc9b74c52008-04-18 20:41:49 +0200935 * The specification states that the block count register must
936 * be updated, but it does not specify at what point in the
937 * data flow. That makes the register entirely useless to read
938 * back so we have to assume that nothing made it to the card
939 * in the event of an error.
Pierre Ossmand129bce2006-03-24 03:18:17 -0800940 */
Pierre Ossmanc9b74c52008-04-18 20:41:49 +0200941 if (data->error)
942 data->bytes_xfered = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800943 else
Pierre Ossmanc9b74c52008-04-18 20:41:49 +0200944 data->bytes_xfered = data->blksz * data->blocks;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800945
Andrei Warkentine89d4562011-05-23 15:06:37 -0500946 /*
947 * Need to send CMD12 if -
948 * a) open-ended multiblock transfer (no CMD23)
949 * b) error in multiblock transfer
950 */
951 if (data->stop &&
952 (data->error ||
953 !host->mrq->sbc)) {
954
Pierre Ossmand129bce2006-03-24 03:18:17 -0800955 /*
956 * The controller needs a reset of internal state machines
957 * upon error conditions.
958 */
Pierre Ossman17b04292007-07-22 22:18:46 +0200959 if (data->error) {
Pierre Ossmand129bce2006-03-24 03:18:17 -0800960 sdhci_reset(host, SDHCI_RESET_CMD);
961 sdhci_reset(host, SDHCI_RESET_DATA);
962 }
963
964 sdhci_send_command(host, data->stop);
965 } else
966 tasklet_schedule(&host->finish_tasklet);
967}
968
969static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
970{
971 int flags;
Pierre Ossmanfd2208d2006-06-30 02:22:28 -0700972 u32 mask;
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700973 unsigned long timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800974
975 WARN_ON(host->cmd);
976
Pierre Ossmand129bce2006-03-24 03:18:17 -0800977 /* Wait max 10 ms */
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700978 timeout = 10;
Pierre Ossmanfd2208d2006-06-30 02:22:28 -0700979
980 mask = SDHCI_CMD_INHIBIT;
981 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
982 mask |= SDHCI_DATA_INHIBIT;
983
984 /* We shouldn't wait for data inihibit for stop commands, even
985 though they might use busy signaling */
986 if (host->mrq->data && (cmd == host->mrq->data->stop))
987 mask &= ~SDHCI_DATA_INHIBIT;
988
Anton Vorontsov4e4141a2009-03-17 00:13:46 +0300989 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700990 if (timeout == 0) {
Girish K Sa3c76eb2011-10-11 11:44:09 +0530991 pr_err("%s: Controller never released "
Pierre Ossmanacf1da42007-02-09 08:29:19 +0100992 "inhibit bit(s).\n", mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -0800993 sdhci_dumpregs(host);
Pierre Ossman17b04292007-07-22 22:18:46 +0200994 cmd->error = -EIO;
Pierre Ossmand129bce2006-03-24 03:18:17 -0800995 tasklet_schedule(&host->finish_tasklet);
996 return;
997 }
Pierre Ossman7cb2c762006-06-30 02:22:23 -0700998 timeout--;
999 mdelay(1);
1000 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001001
1002 mod_timer(&host->timer, jiffies + 10 * HZ);
1003
1004 host->cmd = cmd;
1005
Andrei Warkentina3c77782011-04-11 16:13:42 -05001006 sdhci_prepare_data(host, cmd);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001007
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001008 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001009
Andrei Warkentine89d4562011-05-23 15:06:37 -05001010 sdhci_set_transfer_mode(host, cmd);
Pierre Ossmanc7fa9962006-06-30 02:22:25 -07001011
Pierre Ossmand129bce2006-03-24 03:18:17 -08001012 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05301013 pr_err("%s: Unsupported response type!\n",
Pierre Ossmand129bce2006-03-24 03:18:17 -08001014 mmc_hostname(host->mmc));
Pierre Ossman17b04292007-07-22 22:18:46 +02001015 cmd->error = -EINVAL;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001016 tasklet_schedule(&host->finish_tasklet);
1017 return;
1018 }
1019
1020 if (!(cmd->flags & MMC_RSP_PRESENT))
1021 flags = SDHCI_CMD_RESP_NONE;
1022 else if (cmd->flags & MMC_RSP_136)
1023 flags = SDHCI_CMD_RESP_LONG;
1024 else if (cmd->flags & MMC_RSP_BUSY)
1025 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1026 else
1027 flags = SDHCI_CMD_RESP_SHORT;
1028
1029 if (cmd->flags & MMC_RSP_CRC)
1030 flags |= SDHCI_CMD_CRC;
1031 if (cmd->flags & MMC_RSP_OPCODE)
1032 flags |= SDHCI_CMD_INDEX;
Arindam Nathb513ea22011-05-05 12:19:04 +05301033
1034 /* CMD19 is special in that the Data Present Select should be set */
Girish K S069c9f12012-01-06 09:56:39 +05301035 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1036 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001037 flags |= SDHCI_CMD_DATA;
1038
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001039 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001040}
1041
1042static void sdhci_finish_command(struct sdhci_host *host)
1043{
1044 int i;
1045
1046 BUG_ON(host->cmd == NULL);
1047
1048 if (host->cmd->flags & MMC_RSP_PRESENT) {
1049 if (host->cmd->flags & MMC_RSP_136) {
1050 /* CRC is stripped so we need to do some shifting. */
1051 for (i = 0;i < 4;i++) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001052 host->cmd->resp[i] = sdhci_readl(host,
Pierre Ossmand129bce2006-03-24 03:18:17 -08001053 SDHCI_RESPONSE + (3-i)*4) << 8;
1054 if (i != 3)
1055 host->cmd->resp[i] |=
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001056 sdhci_readb(host,
Pierre Ossmand129bce2006-03-24 03:18:17 -08001057 SDHCI_RESPONSE + (3-i)*4-1);
1058 }
1059 } else {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001060 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001061 }
1062 }
1063
Pierre Ossman17b04292007-07-22 22:18:46 +02001064 host->cmd->error = 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001065
Andrei Warkentine89d4562011-05-23 15:06:37 -05001066 /* Finished CMD23, now send actual command. */
1067 if (host->cmd == host->mrq->sbc) {
1068 host->cmd = NULL;
1069 sdhci_send_command(host, host->mrq->cmd);
1070 } else {
Pierre Ossmane538fbe2007-08-12 16:46:32 +02001071
Andrei Warkentine89d4562011-05-23 15:06:37 -05001072 /* Processed actual command. */
1073 if (host->data && host->data_early)
1074 sdhci_finish_data(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001075
Andrei Warkentine89d4562011-05-23 15:06:37 -05001076 if (!host->cmd->data)
1077 tasklet_schedule(&host->finish_tasklet);
1078
1079 host->cmd = NULL;
1080 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001081}
1082
1083static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1084{
Arindam Nathc3ed3872011-05-05 12:19:06 +05301085 int div = 0; /* Initialized for compiler warning */
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001086 int real_div = div, clk_mul = 1;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301087 u16 clk = 0;
Pierre Ossman7cb2c762006-06-30 02:22:23 -07001088 unsigned long timeout;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001089
Todd Poynor30832ab2011-12-27 15:48:46 +02001090 if (clock && clock == host->clock)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001091 return;
1092
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001093 host->mmc->actual_clock = 0;
1094
Anton Vorontsov81146342009-03-17 00:13:59 +03001095 if (host->ops->set_clock) {
1096 host->ops->set_clock(host, clock);
1097 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1098 return;
1099 }
1100
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001101 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001102
1103 if (clock == 0)
1104 goto out;
1105
Zhangfei Gao85105c52010-08-06 07:10:01 +08001106 if (host->version >= SDHCI_SPEC_300) {
Arindam Nathc3ed3872011-05-05 12:19:06 +05301107 /*
1108 * Check if the Host Controller supports Programmable Clock
1109 * Mode.
1110 */
1111 if (host->clk_mul) {
1112 u16 ctrl;
1113
1114 /*
1115 * We need to figure out whether the Host Driver needs
1116 * to select Programmable Clock Mode, or the value can
1117 * be set automatically by the Host Controller based on
1118 * the Preset Value registers.
1119 */
1120 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1121 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1122 for (div = 1; div <= 1024; div++) {
1123 if (((host->max_clk * host->clk_mul) /
1124 div) <= clock)
1125 break;
1126 }
1127 /*
1128 * Set Programmable Clock Mode in the Clock
1129 * Control register.
1130 */
1131 clk = SDHCI_PROG_CLOCK_MODE;
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001132 real_div = div;
1133 clk_mul = host->clk_mul;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301134 div--;
Zhangfei Gao85105c52010-08-06 07:10:01 +08001135 }
Arindam Nathc3ed3872011-05-05 12:19:06 +05301136 } else {
1137 /* Version 3.00 divisors must be a multiple of 2. */
1138 if (host->max_clk <= clock)
1139 div = 1;
1140 else {
1141 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1142 div += 2) {
1143 if ((host->max_clk / div) <= clock)
1144 break;
1145 }
1146 }
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001147 real_div = div;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301148 div >>= 1;
Zhangfei Gao85105c52010-08-06 07:10:01 +08001149 }
1150 } else {
1151 /* Version 2.00 divisors must be a power of 2. */
Zhangfei Gao03975262010-09-20 15:15:18 -04001152 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Zhangfei Gao85105c52010-08-06 07:10:01 +08001153 if ((host->max_clk / div) <= clock)
1154 break;
1155 }
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001156 real_div = div;
Arindam Nathc3ed3872011-05-05 12:19:06 +05301157 div >>= 1;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001158 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001159
Giuseppe CAVALLAROdf162192011-11-04 13:53:19 +01001160 if (real_div)
1161 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1162
Arindam Nathc3ed3872011-05-05 12:19:06 +05301163 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Zhangfei Gao85105c52010-08-06 07:10:01 +08001164 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1165 << SDHCI_DIVIDER_HI_SHIFT;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001166 clk |= SDHCI_CLOCK_INT_EN;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001167 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001168
Chris Ball27f6cb12009-09-22 16:45:31 -07001169 /* Wait max 20 ms */
1170 timeout = 20;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001171 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
Pierre Ossman7cb2c762006-06-30 02:22:23 -07001172 & SDHCI_CLOCK_INT_STABLE)) {
1173 if (timeout == 0) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05301174 pr_err("%s: Internal clock never "
Pierre Ossmanacf1da42007-02-09 08:29:19 +01001175 "stabilised.\n", mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -08001176 sdhci_dumpregs(host);
1177 return;
1178 }
Pierre Ossman7cb2c762006-06-30 02:22:23 -07001179 timeout--;
1180 mdelay(1);
1181 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001182
1183 clk |= SDHCI_CLOCK_CARD_EN;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001184 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001185
1186out:
1187 host->clock = clock;
1188}
1189
Adrian Hunterceb61432011-12-27 15:48:41 +02001190static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
Pierre Ossman146ad662006-06-30 02:22:23 -07001191{
Giuseppe Cavallaro83642482010-09-28 10:41:28 +02001192 u8 pwr = 0;
Pierre Ossman146ad662006-06-30 02:22:23 -07001193
Giuseppe Cavallaro83642482010-09-28 10:41:28 +02001194 if (power != (unsigned short)-1) {
Pierre Ossmanae628902009-05-03 20:45:03 +02001195 switch (1 << power) {
1196 case MMC_VDD_165_195:
1197 pwr = SDHCI_POWER_180;
1198 break;
1199 case MMC_VDD_29_30:
1200 case MMC_VDD_30_31:
1201 pwr = SDHCI_POWER_300;
1202 break;
1203 case MMC_VDD_32_33:
1204 case MMC_VDD_33_34:
1205 pwr = SDHCI_POWER_330;
1206 break;
1207 default:
1208 BUG();
1209 }
1210 }
1211
1212 if (host->pwr == pwr)
Adrian Hunterceb61432011-12-27 15:48:41 +02001213 return -1;
Pierre Ossman146ad662006-06-30 02:22:23 -07001214
Pierre Ossmanae628902009-05-03 20:45:03 +02001215 host->pwr = pwr;
1216
1217 if (pwr == 0) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001218 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
Adrian Hunterceb61432011-12-27 15:48:41 +02001219 return 0;
Darren Salt9e9dc5f2007-01-27 15:32:31 +01001220 }
1221
1222 /*
1223 * Spec says that we should clear the power reg before setting
1224 * a new value. Some controllers don't seem to like this though.
1225 */
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01001226 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001227 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
Pierre Ossman146ad662006-06-30 02:22:23 -07001228
Andres Salomone08c1692008-07-04 10:00:03 -07001229 /*
Andres Salomonc71f6512008-07-07 17:25:56 -04001230 * At least the Marvell CaFe chip gets confused if we set the voltage
Andres Salomone08c1692008-07-04 10:00:03 -07001231 * and set turn on power at the same time, so set the voltage first.
1232 */
Pierre Ossman11a2f1b2009-06-21 20:59:33 +02001233 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
Pierre Ossmanae628902009-05-03 20:45:03 +02001234 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1235
1236 pwr |= SDHCI_POWER_ON;
Andres Salomone08c1692008-07-04 10:00:03 -07001237
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001238 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
Harald Welte557b0692009-06-18 16:53:38 +02001239
1240 /*
1241 * Some controllers need an extra 10ms delay of 10ms before they
1242 * can apply clock after applying power
1243 */
Pierre Ossman11a2f1b2009-06-21 20:59:33 +02001244 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
Harald Welte557b0692009-06-18 16:53:38 +02001245 mdelay(10);
Adrian Hunterceb61432011-12-27 15:48:41 +02001246
1247 return power;
Pierre Ossman146ad662006-06-30 02:22:23 -07001248}
1249
Pierre Ossmand129bce2006-03-24 03:18:17 -08001250/*****************************************************************************\
1251 * *
1252 * MMC callbacks *
1253 * *
1254\*****************************************************************************/
1255
1256static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1257{
1258 struct sdhci_host *host;
Anton Vorontsov68d1fb72009-03-17 00:13:52 +03001259 bool present;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001260 unsigned long flags;
Aaron Lu473b0952012-07-03 17:27:49 +08001261 u32 tuning_opcode;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001262
1263 host = mmc_priv(mmc);
1264
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001265 sdhci_runtime_pm_get(host);
1266
Pierre Ossmand129bce2006-03-24 03:18:17 -08001267 spin_lock_irqsave(&host->lock, flags);
1268
1269 WARN_ON(host->mrq != NULL);
1270
Pierre Ossmanf9134312008-12-21 17:01:48 +01001271#ifndef SDHCI_USE_LEDS_CLASS
Pierre Ossmand129bce2006-03-24 03:18:17 -08001272 sdhci_activate_led(host);
Pierre Ossman2f730fe2008-03-17 10:29:38 +01001273#endif
Andrei Warkentine89d4562011-05-23 15:06:37 -05001274
1275 /*
1276 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1277 * requests if Auto-CMD12 is enabled.
1278 */
1279 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
Jerry Huangc4512f72010-08-10 18:01:59 -07001280 if (mrq->stop) {
1281 mrq->data->stop = NULL;
1282 mrq->stop = NULL;
1283 }
1284 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001285
1286 host->mrq = mrq;
1287
Anton Vorontsov68d1fb72009-03-17 00:13:52 +03001288 /* If polling, assume that the card is always present. */
1289 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1290 present = true;
1291 else
1292 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1293 SDHCI_CARD_PRESENT;
1294
1295 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001296 host->mrq->cmd->error = -ENOMEDIUM;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001297 tasklet_schedule(&host->finish_tasklet);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05301298 } else {
1299 u32 present_state;
1300
1301 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1302 /*
1303 * Check if the re-tuning timer has already expired and there
1304 * is no on-going data transfer. If so, we need to execute
1305 * tuning procedure before sending command.
1306 */
1307 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1308 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
Aaron Lu473b0952012-07-03 17:27:49 +08001309 /* eMMC uses cmd21 while sd and sdio use cmd19 */
1310 tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1311 MMC_SEND_TUNING_BLOCK_HS200 :
1312 MMC_SEND_TUNING_BLOCK;
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05301313 spin_unlock_irqrestore(&host->lock, flags);
Aaron Lu473b0952012-07-03 17:27:49 +08001314 sdhci_execute_tuning(mmc, tuning_opcode);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05301315 spin_lock_irqsave(&host->lock, flags);
1316
1317 /* Restore original mmc_request structure */
1318 host->mrq = mrq;
1319 }
1320
Andrei Warkentin8edf63712011-05-23 15:06:39 -05001321 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
Andrei Warkentine89d4562011-05-23 15:06:37 -05001322 sdhci_send_command(host, mrq->sbc);
1323 else
1324 sdhci_send_command(host, mrq->cmd);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05301325 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001326
Pierre Ossman5f25a662006-10-04 02:15:39 -07001327 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -08001328 spin_unlock_irqrestore(&host->lock, flags);
1329}
1330
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001331static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001332{
Pierre Ossmand129bce2006-03-24 03:18:17 -08001333 unsigned long flags;
Adrian Hunterceb61432011-12-27 15:48:41 +02001334 int vdd_bit = -1;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001335 u8 ctrl;
1336
Pierre Ossmand129bce2006-03-24 03:18:17 -08001337 spin_lock_irqsave(&host->lock, flags);
1338
Adrian Hunterceb61432011-12-27 15:48:41 +02001339 if (host->flags & SDHCI_DEVICE_DEAD) {
1340 spin_unlock_irqrestore(&host->lock, flags);
1341 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1342 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1343 return;
1344 }
Pierre Ossman1e728592008-04-16 19:13:13 +02001345
Pierre Ossmand129bce2006-03-24 03:18:17 -08001346 /*
1347 * Reset the chip on each power off.
1348 * Should clear out any weird states.
1349 */
1350 if (ios->power_mode == MMC_POWER_OFF) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001351 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
Anton Vorontsov7260cf52009-03-17 00:13:48 +03001352 sdhci_reinit(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001353 }
1354
1355 sdhci_set_clock(host, ios->clock);
1356
1357 if (ios->power_mode == MMC_POWER_OFF)
Adrian Hunterceb61432011-12-27 15:48:41 +02001358 vdd_bit = sdhci_set_power(host, -1);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001359 else
Adrian Hunterceb61432011-12-27 15:48:41 +02001360 vdd_bit = sdhci_set_power(host, ios->vdd);
1361
1362 if (host->vmmc && vdd_bit != -1) {
1363 spin_unlock_irqrestore(&host->lock, flags);
1364 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1365 spin_lock_irqsave(&host->lock, flags);
1366 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08001367
Philip Rakity643a81f2010-09-23 08:24:32 -07001368 if (host->ops->platform_send_init_74_clocks)
1369 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1370
Philip Rakity15ec4462010-11-19 16:48:39 -05001371 /*
1372 * If your platform has 8-bit width support but is not a v3 controller,
1373 * or if it requires special setup code, you should implement that in
1374 * platform_8bit_width().
1375 */
1376 if (host->ops->platform_8bit_width)
1377 host->ops->platform_8bit_width(host, ios->bus_width);
1378 else {
1379 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1380 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1381 ctrl &= ~SDHCI_CTRL_4BITBUS;
1382 if (host->version >= SDHCI_SPEC_300)
1383 ctrl |= SDHCI_CTRL_8BITBUS;
1384 } else {
1385 if (host->version >= SDHCI_SPEC_300)
1386 ctrl &= ~SDHCI_CTRL_8BITBUS;
1387 if (ios->bus_width == MMC_BUS_WIDTH_4)
1388 ctrl |= SDHCI_CTRL_4BITBUS;
1389 else
1390 ctrl &= ~SDHCI_CTRL_4BITBUS;
1391 }
1392 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1393 }
1394
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03001395 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Pierre Ossmancd9277c2007-02-18 12:07:47 +01001396
Philip Rakity3ab9c8d2010-10-06 11:57:23 -07001397 if ((ios->timing == MMC_TIMING_SD_HS ||
1398 ios->timing == MMC_TIMING_MMC_HS)
1399 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
Pierre Ossmancd9277c2007-02-18 12:07:47 +01001400 ctrl |= SDHCI_CTRL_HISPD;
1401 else
1402 ctrl &= ~SDHCI_CTRL_HISPD;
1403
Arindam Nathd6d50a12011-05-05 12:18:59 +05301404 if (host->version >= SDHCI_SPEC_300) {
Arindam Nath49c468f2011-05-05 12:19:01 +05301405 u16 clk, ctrl_2;
1406 unsigned int clock;
1407
1408 /* In case of UHS-I modes, set High Speed Enable */
Girish K S069c9f12012-01-06 09:56:39 +05301409 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1410 (ios->timing == MMC_TIMING_UHS_SDR50) ||
Arindam Nath49c468f2011-05-05 12:19:01 +05301411 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1412 (ios->timing == MMC_TIMING_UHS_DDR50) ||
Alexander Elbsdd8df172012-01-03 23:26:53 -05001413 (ios->timing == MMC_TIMING_UHS_SDR25))
Arindam Nath49c468f2011-05-05 12:19:01 +05301414 ctrl |= SDHCI_CTRL_HISPD;
Arindam Nathd6d50a12011-05-05 12:18:59 +05301415
1416 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1417 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
Arindam Nath758535c2011-05-05 12:19:00 +05301418 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Arindam Nathd6d50a12011-05-05 12:18:59 +05301419 /*
1420 * We only need to set Driver Strength if the
1421 * preset value enable is not set.
1422 */
1423 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1424 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1425 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1426 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1427 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1428
1429 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
Arindam Nath758535c2011-05-05 12:19:00 +05301430 } else {
1431 /*
1432 * According to SDHC Spec v3.00, if the Preset Value
1433 * Enable in the Host Control 2 register is set, we
1434 * need to reset SD Clock Enable before changing High
1435 * Speed Enable to avoid generating clock gliches.
1436 */
Arindam Nath758535c2011-05-05 12:19:00 +05301437
1438 /* Reset SD Clock Enable */
1439 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1440 clk &= ~SDHCI_CLOCK_CARD_EN;
1441 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1442
1443 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1444
1445 /* Re-enable SD Clock */
1446 clock = host->clock;
1447 host->clock = 0;
1448 sdhci_set_clock(host, clock);
Arindam Nathd6d50a12011-05-05 12:18:59 +05301449 }
Arindam Nath49c468f2011-05-05 12:19:01 +05301450
Arindam Nath49c468f2011-05-05 12:19:01 +05301451
1452 /* Reset SD Clock Enable */
1453 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1454 clk &= ~SDHCI_CLOCK_CARD_EN;
1455 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1456
Philip Rakity6322cdd2011-05-13 11:17:15 +05301457 if (host->ops->set_uhs_signaling)
1458 host->ops->set_uhs_signaling(host, ios->timing);
1459 else {
1460 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1461 /* Select Bus Speed Mode for host */
1462 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
Girish K S069c9f12012-01-06 09:56:39 +05301463 if (ios->timing == MMC_TIMING_MMC_HS200)
1464 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1465 else if (ios->timing == MMC_TIMING_UHS_SDR12)
Philip Rakity6322cdd2011-05-13 11:17:15 +05301466 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1467 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1468 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1469 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1470 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1471 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1472 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1473 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1474 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1475 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1476 }
Arindam Nath49c468f2011-05-05 12:19:01 +05301477
1478 /* Re-enable SD Clock */
1479 clock = host->clock;
1480 host->clock = 0;
1481 sdhci_set_clock(host, clock);
Arindam Nath758535c2011-05-05 12:19:00 +05301482 } else
1483 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Arindam Nathd6d50a12011-05-05 12:18:59 +05301484
Leandro Dorileob8352262007-07-25 23:47:04 +02001485 /*
1486 * Some (ENE) controllers go apeshit on some ios operation,
1487 * signalling timeout and CRC errors even on CMD0. Resetting
1488 * it on each ios seems to solve the problem.
1489 */
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01001490 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
Leandro Dorileob8352262007-07-25 23:47:04 +02001491 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1492
Pierre Ossman5f25a662006-10-04 02:15:39 -07001493 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -08001494 spin_unlock_irqrestore(&host->lock, flags);
1495}
1496
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001497static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1498{
1499 struct sdhci_host *host = mmc_priv(mmc);
1500
1501 sdhci_runtime_pm_get(host);
1502 sdhci_do_set_ios(host, ios);
1503 sdhci_runtime_pm_put(host);
1504}
1505
1506static int sdhci_check_ro(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08001507{
Pierre Ossmand129bce2006-03-24 03:18:17 -08001508 unsigned long flags;
Wolfram Sang2dfb5792010-10-15 12:21:01 +02001509 int is_readonly;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001510
Pierre Ossmand129bce2006-03-24 03:18:17 -08001511 spin_lock_irqsave(&host->lock, flags);
1512
Pierre Ossman1e728592008-04-16 19:13:13 +02001513 if (host->flags & SDHCI_DEVICE_DEAD)
Wolfram Sang2dfb5792010-10-15 12:21:01 +02001514 is_readonly = 0;
1515 else if (host->ops->get_ro)
1516 is_readonly = host->ops->get_ro(host);
Pierre Ossman1e728592008-04-16 19:13:13 +02001517 else
Wolfram Sang2dfb5792010-10-15 12:21:01 +02001518 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1519 & SDHCI_WRITE_PROTECT);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001520
1521 spin_unlock_irqrestore(&host->lock, flags);
1522
Wolfram Sang2dfb5792010-10-15 12:21:01 +02001523 /* This quirk needs to be replaced by a callback-function later */
1524 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1525 !is_readonly : is_readonly;
Pierre Ossmand129bce2006-03-24 03:18:17 -08001526}
1527
Takashi Iwai82b0e232011-04-21 20:26:38 +02001528#define SAMPLE_COUNT 5
1529
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001530static int sdhci_do_get_ro(struct sdhci_host *host)
Takashi Iwai82b0e232011-04-21 20:26:38 +02001531{
Takashi Iwai82b0e232011-04-21 20:26:38 +02001532 int i, ro_count;
1533
Takashi Iwai82b0e232011-04-21 20:26:38 +02001534 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001535 return sdhci_check_ro(host);
Takashi Iwai82b0e232011-04-21 20:26:38 +02001536
1537 ro_count = 0;
1538 for (i = 0; i < SAMPLE_COUNT; i++) {
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001539 if (sdhci_check_ro(host)) {
Takashi Iwai82b0e232011-04-21 20:26:38 +02001540 if (++ro_count > SAMPLE_COUNT / 2)
1541 return 1;
1542 }
1543 msleep(30);
1544 }
1545 return 0;
1546}
1547
Adrian Hunter20758b62011-08-29 16:42:12 +03001548static void sdhci_hw_reset(struct mmc_host *mmc)
1549{
1550 struct sdhci_host *host = mmc_priv(mmc);
1551
1552 if (host->ops && host->ops->hw_reset)
1553 host->ops->hw_reset(host);
1554}
1555
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001556static int sdhci_get_ro(struct mmc_host *mmc)
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001557{
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001558 struct sdhci_host *host = mmc_priv(mmc);
1559 int ret;
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001560
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001561 sdhci_runtime_pm_get(host);
1562 ret = sdhci_do_get_ro(host);
1563 sdhci_runtime_pm_put(host);
1564 return ret;
1565}
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001566
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001567static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1568{
Pierre Ossman1e728592008-04-16 19:13:13 +02001569 if (host->flags & SDHCI_DEVICE_DEAD)
1570 goto out;
1571
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001572 if (enable)
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001573 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1574 else
1575 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1576
1577 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1578 if (host->runtime_suspended)
1579 goto out;
1580
1581 if (enable)
Anton Vorontsov7260cf52009-03-17 00:13:48 +03001582 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1583 else
1584 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
Pierre Ossman1e728592008-04-16 19:13:13 +02001585out:
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001586 mmiowb();
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001587}
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001588
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001589static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1590{
1591 struct sdhci_host *host = mmc_priv(mmc);
1592 unsigned long flags;
1593
1594 spin_lock_irqsave(&host->lock, flags);
1595 sdhci_enable_sdio_irq_nolock(host, enable);
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001596 spin_unlock_irqrestore(&host->lock, flags);
1597}
1598
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001599static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1600 struct mmc_ios *ios)
Arindam Nathf2119df2011-05-05 12:18:57 +05301601{
Arindam Nathf2119df2011-05-05 12:18:57 +05301602 u8 pwr;
1603 u16 clk, ctrl;
1604 u32 present_state;
1605
Arindam Nathf2119df2011-05-05 12:18:57 +05301606 /*
1607 * Signal Voltage Switching is only applicable for Host Controllers
1608 * v3.00 and above.
1609 */
1610 if (host->version < SDHCI_SPEC_300)
1611 return 0;
1612
1613 /*
1614 * We first check whether the request is to set signalling voltage
1615 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1616 */
1617 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1618 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1619 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1620 ctrl &= ~SDHCI_CTRL_VDD_180;
1621 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1622
1623 /* Wait for 5ms */
1624 usleep_range(5000, 5500);
1625
1626 /* 3.3V regulator output should be stable within 5 ms */
1627 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1628 if (!(ctrl & SDHCI_CTRL_VDD_180))
1629 return 0;
1630 else {
Girish K Sa3c76eb2011-10-11 11:44:09 +05301631 pr_info(DRIVER_NAME ": Switching to 3.3V "
Arindam Nathf2119df2011-05-05 12:18:57 +05301632 "signalling voltage failed\n");
1633 return -EIO;
1634 }
1635 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1636 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1637 /* Stop SDCLK */
1638 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1639 clk &= ~SDHCI_CLOCK_CARD_EN;
1640 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1641
1642 /* Check whether DAT[3:0] is 0000 */
1643 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1644 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1645 SDHCI_DATA_LVL_SHIFT)) {
1646 /*
1647 * Enable 1.8V Signal Enable in the Host Control2
1648 * register
1649 */
1650 ctrl |= SDHCI_CTRL_VDD_180;
1651 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1652
1653 /* Wait for 5ms */
1654 usleep_range(5000, 5500);
1655
1656 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1657 if (ctrl & SDHCI_CTRL_VDD_180) {
1658 /* Provide SDCLK again and wait for 1ms*/
1659 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1660 clk |= SDHCI_CLOCK_CARD_EN;
1661 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1662 usleep_range(1000, 1500);
1663
1664 /*
1665 * If DAT[3:0] level is 1111b, then the card
1666 * was successfully switched to 1.8V signaling.
1667 */
1668 present_state = sdhci_readl(host,
1669 SDHCI_PRESENT_STATE);
1670 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1671 SDHCI_DATA_LVL_MASK)
1672 return 0;
1673 }
1674 }
1675
1676 /*
1677 * If we are here, that means the switch to 1.8V signaling
1678 * failed. We power cycle the card, and retry initialization
1679 * sequence by setting S18R to 0.
1680 */
1681 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1682 pwr &= ~SDHCI_POWER_ON;
1683 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1684
1685 /* Wait for 1ms as per the spec */
1686 usleep_range(1000, 1500);
1687 pwr |= SDHCI_POWER_ON;
1688 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1689
Girish K Sa3c76eb2011-10-11 11:44:09 +05301690 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
Arindam Nathf2119df2011-05-05 12:18:57 +05301691 "voltage failed, retrying with S18R set to 0\n");
1692 return -EAGAIN;
1693 } else
1694 /* No signal voltage switch required */
1695 return 0;
1696}
1697
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001698static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1699 struct mmc_ios *ios)
1700{
1701 struct sdhci_host *host = mmc_priv(mmc);
1702 int err;
1703
1704 if (host->version < SDHCI_SPEC_300)
1705 return 0;
1706 sdhci_runtime_pm_get(host);
1707 err = sdhci_do_start_signal_voltage_switch(host, ios);
1708 sdhci_runtime_pm_put(host);
1709 return err;
1710}
1711
Girish K S069c9f12012-01-06 09:56:39 +05301712static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
Arindam Nathb513ea22011-05-05 12:19:04 +05301713{
1714 struct sdhci_host *host;
1715 u16 ctrl;
1716 u32 ier;
1717 int tuning_loop_counter = MAX_TUNING_LOOP;
1718 unsigned long timeout;
1719 int err = 0;
Girish K S069c9f12012-01-06 09:56:39 +05301720 bool requires_tuning_nonuhs = false;
Arindam Nathb513ea22011-05-05 12:19:04 +05301721
1722 host = mmc_priv(mmc);
1723
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001724 sdhci_runtime_pm_get(host);
Arindam Nathb513ea22011-05-05 12:19:04 +05301725 disable_irq(host->irq);
1726 spin_lock(&host->lock);
1727
1728 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1729
1730 /*
Girish K S069c9f12012-01-06 09:56:39 +05301731 * The Host Controller needs tuning only in case of SDR104 mode
1732 * and for SDR50 mode when Use Tuning for SDR50 is set in the
Arindam Nathb513ea22011-05-05 12:19:04 +05301733 * Capabilities register.
Girish K S069c9f12012-01-06 09:56:39 +05301734 * If the Host Controller supports the HS200 mode then the
1735 * tuning function has to be executed.
Arindam Nathb513ea22011-05-05 12:19:04 +05301736 */
Girish K S069c9f12012-01-06 09:56:39 +05301737 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1738 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1739 host->flags & SDHCI_HS200_NEEDS_TUNING))
1740 requires_tuning_nonuhs = true;
1741
Arindam Nathb513ea22011-05-05 12:19:04 +05301742 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
Girish K S069c9f12012-01-06 09:56:39 +05301743 requires_tuning_nonuhs)
Arindam Nathb513ea22011-05-05 12:19:04 +05301744 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1745 else {
1746 spin_unlock(&host->lock);
1747 enable_irq(host->irq);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001748 sdhci_runtime_pm_put(host);
Arindam Nathb513ea22011-05-05 12:19:04 +05301749 return 0;
1750 }
1751
1752 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1753
1754 /*
1755 * As per the Host Controller spec v3.00, tuning command
1756 * generates Buffer Read Ready interrupt, so enable that.
1757 *
1758 * Note: The spec clearly says that when tuning sequence
1759 * is being performed, the controller does not generate
1760 * interrupts other than Buffer Read Ready interrupt. But
1761 * to make sure we don't hit a controller bug, we _only_
1762 * enable Buffer Read Ready interrupt here.
1763 */
1764 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1765 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1766
1767 /*
1768 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1769 * of loops reaches 40 times or a timeout of 150ms occurs.
1770 */
1771 timeout = 150;
1772 do {
1773 struct mmc_command cmd = {0};
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001774 struct mmc_request mrq = {NULL};
Arindam Nathb513ea22011-05-05 12:19:04 +05301775
1776 if (!tuning_loop_counter && !timeout)
1777 break;
1778
Girish K S069c9f12012-01-06 09:56:39 +05301779 cmd.opcode = opcode;
Arindam Nathb513ea22011-05-05 12:19:04 +05301780 cmd.arg = 0;
1781 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1782 cmd.retries = 0;
1783 cmd.data = NULL;
1784 cmd.error = 0;
1785
1786 mrq.cmd = &cmd;
1787 host->mrq = &mrq;
1788
1789 /*
1790 * In response to CMD19, the card sends 64 bytes of tuning
1791 * block to the Host Controller. So we set the block size
1792 * to 64 here.
1793 */
Girish K S069c9f12012-01-06 09:56:39 +05301794 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1795 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1796 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1797 SDHCI_BLOCK_SIZE);
1798 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1799 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1800 SDHCI_BLOCK_SIZE);
1801 } else {
1802 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1803 SDHCI_BLOCK_SIZE);
1804 }
Arindam Nathb513ea22011-05-05 12:19:04 +05301805
1806 /*
1807 * The tuning block is sent by the card to the host controller.
1808 * So we set the TRNS_READ bit in the Transfer Mode register.
1809 * This also takes care of setting DMA Enable and Multi Block
1810 * Select in the same register to 0.
1811 */
1812 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1813
1814 sdhci_send_command(host, &cmd);
1815
1816 host->cmd = NULL;
1817 host->mrq = NULL;
1818
1819 spin_unlock(&host->lock);
1820 enable_irq(host->irq);
1821
1822 /* Wait for Buffer Read Ready interrupt */
1823 wait_event_interruptible_timeout(host->buf_ready_int,
1824 (host->tuning_done == 1),
1825 msecs_to_jiffies(50));
1826 disable_irq(host->irq);
1827 spin_lock(&host->lock);
1828
1829 if (!host->tuning_done) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05301830 pr_info(DRIVER_NAME ": Timeout waiting for "
Arindam Nathb513ea22011-05-05 12:19:04 +05301831 "Buffer Read Ready interrupt during tuning "
1832 "procedure, falling back to fixed sampling "
1833 "clock\n");
1834 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1835 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1836 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1837 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1838
1839 err = -EIO;
1840 goto out;
1841 }
1842
1843 host->tuning_done = 0;
1844
1845 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1846 tuning_loop_counter--;
1847 timeout--;
1848 mdelay(1);
1849 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1850
1851 /*
1852 * The Host Driver has exhausted the maximum number of loops allowed,
1853 * so use fixed sampling frequency.
1854 */
1855 if (!tuning_loop_counter || !timeout) {
1856 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1857 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1858 } else {
1859 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05301860 pr_info(DRIVER_NAME ": Tuning procedure"
Arindam Nathb513ea22011-05-05 12:19:04 +05301861 " failed, falling back to fixed sampling"
1862 " clock\n");
1863 err = -EIO;
1864 }
1865 }
1866
1867out:
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05301868 /*
1869 * If this is the very first time we are here, we start the retuning
1870 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1871 * flag won't be set, we check this condition before actually starting
1872 * the timer.
1873 */
1874 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1875 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1876 mod_timer(&host->tuning_timer, jiffies +
1877 host->tuning_count * HZ);
1878 /* Tuning mode 1 limits the maximum data length to 4MB */
1879 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1880 } else {
1881 host->flags &= ~SDHCI_NEEDS_RETUNING;
1882 /* Reload the new initial value for timer */
1883 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1884 mod_timer(&host->tuning_timer, jiffies +
1885 host->tuning_count * HZ);
1886 }
1887
1888 /*
1889 * In case tuning fails, host controllers which support re-tuning can
1890 * try tuning again at a later time, when the re-tuning timer expires.
1891 * So for these controllers, we return 0. Since there might be other
1892 * controllers who do not have this capability, we return error for
1893 * them.
1894 */
1895 if (err && host->tuning_count &&
1896 host->tuning_mode == SDHCI_TUNING_MODE_1)
1897 err = 0;
1898
Arindam Nathb513ea22011-05-05 12:19:04 +05301899 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1900 spin_unlock(&host->lock);
1901 enable_irq(host->irq);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001902 sdhci_runtime_pm_put(host);
Arindam Nathb513ea22011-05-05 12:19:04 +05301903
1904 return err;
1905}
1906
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001907static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
Arindam Nath4d55c5a2011-05-05 12:19:05 +05301908{
Arindam Nath4d55c5a2011-05-05 12:19:05 +05301909 u16 ctrl;
1910 unsigned long flags;
1911
Arindam Nath4d55c5a2011-05-05 12:19:05 +05301912 /* Host Controller v3.00 defines preset value registers */
1913 if (host->version < SDHCI_SPEC_300)
1914 return;
1915
1916 spin_lock_irqsave(&host->lock, flags);
1917
1918 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1919
1920 /*
1921 * We only enable or disable Preset Value if they are not already
1922 * enabled or disabled respectively. Otherwise, we bail out.
1923 */
1924 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1925 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1926 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001927 host->flags |= SDHCI_PV_ENABLED;
Arindam Nath4d55c5a2011-05-05 12:19:05 +05301928 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1929 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1930 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001931 host->flags &= ~SDHCI_PV_ENABLED;
Arindam Nath4d55c5a2011-05-05 12:19:05 +05301932 }
1933
1934 spin_unlock_irqrestore(&host->lock, flags);
1935}
1936
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001937static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1938{
1939 struct sdhci_host *host = mmc_priv(mmc);
1940
1941 sdhci_runtime_pm_get(host);
1942 sdhci_do_enable_preset_value(host, enable);
1943 sdhci_runtime_pm_put(host);
1944}
1945
David Brownellab7aefd2006-11-12 17:55:30 -08001946static const struct mmc_host_ops sdhci_ops = {
Pierre Ossmand129bce2006-03-24 03:18:17 -08001947 .request = sdhci_request,
1948 .set_ios = sdhci_set_ios,
1949 .get_ro = sdhci_get_ro,
Adrian Hunter20758b62011-08-29 16:42:12 +03001950 .hw_reset = sdhci_hw_reset,
Pierre Ossmanf75979b2007-09-04 07:59:18 +02001951 .enable_sdio_irq = sdhci_enable_sdio_irq,
Arindam Nathf2119df2011-05-05 12:18:57 +05301952 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
Arindam Nathb513ea22011-05-05 12:19:04 +05301953 .execute_tuning = sdhci_execute_tuning,
Arindam Nath4d55c5a2011-05-05 12:19:05 +05301954 .enable_preset_value = sdhci_enable_preset_value,
Pierre Ossmand129bce2006-03-24 03:18:17 -08001955};
1956
1957/*****************************************************************************\
1958 * *
1959 * Tasklets *
1960 * *
1961\*****************************************************************************/
1962
1963static void sdhci_tasklet_card(unsigned long param)
1964{
1965 struct sdhci_host *host;
1966 unsigned long flags;
1967
1968 host = (struct sdhci_host*)param;
1969
1970 spin_lock_irqsave(&host->lock, flags);
1971
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001972 /* Check host->mrq first in case we are runtime suspended */
1973 if (host->mrq &&
1974 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05301975 pr_err("%s: Card removed during transfer!\n",
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001976 mmc_hostname(host->mmc));
Girish K Sa3c76eb2011-10-11 11:44:09 +05301977 pr_err("%s: Resetting controller.\n",
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001978 mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -08001979
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001980 sdhci_reset(host, SDHCI_RESET_CMD);
1981 sdhci_reset(host, SDHCI_RESET_DATA);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001982
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03001983 host->mrq->cmd->error = -ENOMEDIUM;
1984 tasklet_schedule(&host->finish_tasklet);
Pierre Ossmand129bce2006-03-24 03:18:17 -08001985 }
1986
1987 spin_unlock_irqrestore(&host->lock, flags);
1988
Pierre Ossman04cf5852008-08-18 22:18:14 +02001989 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
Pierre Ossmand129bce2006-03-24 03:18:17 -08001990}
1991
1992static void sdhci_tasklet_finish(unsigned long param)
1993{
1994 struct sdhci_host *host;
1995 unsigned long flags;
1996 struct mmc_request *mrq;
1997
1998 host = (struct sdhci_host*)param;
1999
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002000 spin_lock_irqsave(&host->lock, flags);
2001
Chris Ball0c9c99a2011-04-27 17:35:31 -04002002 /*
2003 * If this tasklet gets rescheduled while running, it will
2004 * be run again afterwards but without any active request.
2005 */
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002006 if (!host->mrq) {
2007 spin_unlock_irqrestore(&host->lock, flags);
Chris Ball0c9c99a2011-04-27 17:35:31 -04002008 return;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002009 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002010
2011 del_timer(&host->timer);
2012
2013 mrq = host->mrq;
2014
Pierre Ossmand129bce2006-03-24 03:18:17 -08002015 /*
2016 * The controller needs a reset of internal state machines
2017 * upon error conditions.
2018 */
Pierre Ossman1e728592008-04-16 19:13:13 +02002019 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
Ben Dooksb7b4d342011-04-27 14:24:19 +01002020 ((mrq->cmd && mrq->cmd->error) ||
Pierre Ossman1e728592008-04-16 19:13:13 +02002021 (mrq->data && (mrq->data->error ||
2022 (mrq->data->stop && mrq->data->stop->error))) ||
2023 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
Pierre Ossman645289d2006-06-30 02:22:33 -07002024
2025 /* Some controllers need this kick or reset won't work here */
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002026 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
Pierre Ossman645289d2006-06-30 02:22:33 -07002027 unsigned int clock;
2028
2029 /* This is to force an update */
2030 clock = host->clock;
2031 host->clock = 0;
2032 sdhci_set_clock(host, clock);
2033 }
2034
2035 /* Spec says we should do both at the same time, but Ricoh
2036 controllers do not like that. */
Pierre Ossmand129bce2006-03-24 03:18:17 -08002037 sdhci_reset(host, SDHCI_RESET_CMD);
2038 sdhci_reset(host, SDHCI_RESET_DATA);
2039 }
2040
2041 host->mrq = NULL;
2042 host->cmd = NULL;
2043 host->data = NULL;
2044
Pierre Ossmanf9134312008-12-21 17:01:48 +01002045#ifndef SDHCI_USE_LEDS_CLASS
Pierre Ossmand129bce2006-03-24 03:18:17 -08002046 sdhci_deactivate_led(host);
Pierre Ossman2f730fe2008-03-17 10:29:38 +01002047#endif
Pierre Ossmand129bce2006-03-24 03:18:17 -08002048
Pierre Ossman5f25a662006-10-04 02:15:39 -07002049 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -08002050 spin_unlock_irqrestore(&host->lock, flags);
2051
2052 mmc_request_done(host->mmc, mrq);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002053 sdhci_runtime_pm_put(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002054}
2055
2056static void sdhci_timeout_timer(unsigned long data)
2057{
2058 struct sdhci_host *host;
2059 unsigned long flags;
2060
2061 host = (struct sdhci_host*)data;
2062
2063 spin_lock_irqsave(&host->lock, flags);
2064
2065 if (host->mrq) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302066 pr_err("%s: Timeout waiting for hardware "
Pierre Ossmanacf1da42007-02-09 08:29:19 +01002067 "interrupt.\n", mmc_hostname(host->mmc));
Pierre Ossmand129bce2006-03-24 03:18:17 -08002068 sdhci_dumpregs(host);
2069
2070 if (host->data) {
Pierre Ossman17b04292007-07-22 22:18:46 +02002071 host->data->error = -ETIMEDOUT;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002072 sdhci_finish_data(host);
2073 } else {
2074 if (host->cmd)
Pierre Ossman17b04292007-07-22 22:18:46 +02002075 host->cmd->error = -ETIMEDOUT;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002076 else
Pierre Ossman17b04292007-07-22 22:18:46 +02002077 host->mrq->cmd->error = -ETIMEDOUT;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002078
2079 tasklet_schedule(&host->finish_tasklet);
2080 }
2081 }
2082
Pierre Ossman5f25a662006-10-04 02:15:39 -07002083 mmiowb();
Pierre Ossmand129bce2006-03-24 03:18:17 -08002084 spin_unlock_irqrestore(&host->lock, flags);
2085}
2086
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302087static void sdhci_tuning_timer(unsigned long data)
2088{
2089 struct sdhci_host *host;
2090 unsigned long flags;
2091
2092 host = (struct sdhci_host *)data;
2093
2094 spin_lock_irqsave(&host->lock, flags);
2095
2096 host->flags |= SDHCI_NEEDS_RETUNING;
2097
2098 spin_unlock_irqrestore(&host->lock, flags);
2099}
2100
Pierre Ossmand129bce2006-03-24 03:18:17 -08002101/*****************************************************************************\
2102 * *
2103 * Interrupt handling *
2104 * *
2105\*****************************************************************************/
2106
2107static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2108{
2109 BUG_ON(intmask == 0);
2110
2111 if (!host->cmd) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302112 pr_err("%s: Got command interrupt 0x%08x even "
Pierre Ossmanb67ac3f2007-08-12 17:29:47 +02002113 "though no command operation was in progress.\n",
2114 mmc_hostname(host->mmc), (unsigned)intmask);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002115 sdhci_dumpregs(host);
2116 return;
2117 }
2118
Pierre Ossman43b58b32007-07-25 23:15:27 +02002119 if (intmask & SDHCI_INT_TIMEOUT)
Pierre Ossman17b04292007-07-22 22:18:46 +02002120 host->cmd->error = -ETIMEDOUT;
2121 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2122 SDHCI_INT_INDEX))
2123 host->cmd->error = -EILSEQ;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002124
Pierre Ossmane8095172008-07-25 01:09:08 +02002125 if (host->cmd->error) {
Pierre Ossmand129bce2006-03-24 03:18:17 -08002126 tasklet_schedule(&host->finish_tasklet);
Pierre Ossmane8095172008-07-25 01:09:08 +02002127 return;
2128 }
2129
2130 /*
2131 * The host can send and interrupt when the busy state has
2132 * ended, allowing us to wait without wasting CPU cycles.
2133 * Unfortunately this is overloaded on the "data complete"
2134 * interrupt, so we need to take some care when handling
2135 * it.
2136 *
2137 * Note: The 1.0 specification is a bit ambiguous about this
2138 * feature so there might be some problems with older
2139 * controllers.
2140 */
2141 if (host->cmd->flags & MMC_RSP_BUSY) {
2142 if (host->cmd->data)
2143 DBG("Cannot wait for busy signal when also "
2144 "doing a data transfer");
Ben Dooksf9454052009-02-20 20:33:08 +03002145 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
Pierre Ossmane8095172008-07-25 01:09:08 +02002146 return;
Ben Dooksf9454052009-02-20 20:33:08 +03002147
2148 /* The controller does not support the end-of-busy IRQ,
2149 * fall through and take the SDHCI_INT_RESPONSE */
Pierre Ossmane8095172008-07-25 01:09:08 +02002150 }
2151
2152 if (intmask & SDHCI_INT_RESPONSE)
Pierre Ossman43b58b32007-07-25 23:15:27 +02002153 sdhci_finish_command(host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002154}
2155
George G. Davis0957c332010-02-18 12:32:12 -05002156#ifdef CONFIG_MMC_DEBUG
Ben Dooks6882a8c2009-06-14 13:52:38 +01002157static void sdhci_show_adma_error(struct sdhci_host *host)
2158{
2159 const char *name = mmc_hostname(host->mmc);
2160 u8 *desc = host->adma_desc;
2161 __le32 *dma;
2162 __le16 *len;
2163 u8 attr;
2164
2165 sdhci_dumpregs(host);
2166
2167 while (true) {
2168 dma = (__le32 *)(desc + 4);
2169 len = (__le16 *)(desc + 2);
2170 attr = *desc;
2171
2172 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2173 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2174
2175 desc += 8;
2176
2177 if (attr & 2)
2178 break;
2179 }
2180}
2181#else
2182static void sdhci_show_adma_error(struct sdhci_host *host) { }
2183#endif
2184
Pierre Ossmand129bce2006-03-24 03:18:17 -08002185static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2186{
Girish K S069c9f12012-01-06 09:56:39 +05302187 u32 command;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002188 BUG_ON(intmask == 0);
2189
Arindam Nathb513ea22011-05-05 12:19:04 +05302190 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2191 if (intmask & SDHCI_INT_DATA_AVAIL) {
Girish K S069c9f12012-01-06 09:56:39 +05302192 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2193 if (command == MMC_SEND_TUNING_BLOCK ||
2194 command == MMC_SEND_TUNING_BLOCK_HS200) {
Arindam Nathb513ea22011-05-05 12:19:04 +05302195 host->tuning_done = 1;
2196 wake_up(&host->buf_ready_int);
2197 return;
2198 }
2199 }
2200
Pierre Ossmand129bce2006-03-24 03:18:17 -08002201 if (!host->data) {
2202 /*
Pierre Ossmane8095172008-07-25 01:09:08 +02002203 * The "data complete" interrupt is also used to
2204 * indicate that a busy state has ended. See comment
2205 * above in sdhci_cmd_irq().
Pierre Ossmand129bce2006-03-24 03:18:17 -08002206 */
Pierre Ossmane8095172008-07-25 01:09:08 +02002207 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2208 if (intmask & SDHCI_INT_DATA_END) {
2209 sdhci_finish_command(host);
2210 return;
2211 }
2212 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002213
Girish K Sa3c76eb2011-10-11 11:44:09 +05302214 pr_err("%s: Got data interrupt 0x%08x even "
Pierre Ossmanb67ac3f2007-08-12 17:29:47 +02002215 "though no data operation was in progress.\n",
2216 mmc_hostname(host->mmc), (unsigned)intmask);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002217 sdhci_dumpregs(host);
2218
2219 return;
2220 }
2221
2222 if (intmask & SDHCI_INT_DATA_TIMEOUT)
Pierre Ossman17b04292007-07-22 22:18:46 +02002223 host->data->error = -ETIMEDOUT;
Aries Lee22113ef2010-12-15 08:14:24 +01002224 else if (intmask & SDHCI_INT_DATA_END_BIT)
2225 host->data->error = -EILSEQ;
2226 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2227 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2228 != MMC_BUS_TEST_R)
Pierre Ossman17b04292007-07-22 22:18:46 +02002229 host->data->error = -EILSEQ;
Ben Dooks6882a8c2009-06-14 13:52:38 +01002230 else if (intmask & SDHCI_INT_ADMA_ERROR) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302231 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
Ben Dooks6882a8c2009-06-14 13:52:38 +01002232 sdhci_show_adma_error(host);
Pierre Ossman2134a922008-06-28 18:28:51 +02002233 host->data->error = -EIO;
Ben Dooks6882a8c2009-06-14 13:52:38 +01002234 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002235
Pierre Ossman17b04292007-07-22 22:18:46 +02002236 if (host->data->error)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002237 sdhci_finish_data(host);
2238 else {
Pierre Ossmana406f5a2006-07-02 16:50:59 +01002239 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
Pierre Ossmand129bce2006-03-24 03:18:17 -08002240 sdhci_transfer_pio(host);
2241
Pierre Ossman6ba736a2007-05-13 22:39:23 +02002242 /*
2243 * We currently don't do anything fancy with DMA
2244 * boundaries, but as we can't disable the feature
2245 * we need to at least restart the transfer.
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04002246 *
2247 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2248 * should return a valid address to continue from, but as
2249 * some controllers are faulty, don't trust them.
Pierre Ossman6ba736a2007-05-13 22:39:23 +02002250 */
Mikko Vinnif6a03cb2011-04-12 09:36:18 -04002251 if (intmask & SDHCI_INT_DMA_END) {
2252 u32 dmastart, dmanow;
2253 dmastart = sg_dma_address(host->data->sg);
2254 dmanow = dmastart + host->data->bytes_xfered;
2255 /*
2256 * Force update to the next DMA block boundary.
2257 */
2258 dmanow = (dmanow &
2259 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2260 SDHCI_DEFAULT_BOUNDARY_SIZE;
2261 host->data->bytes_xfered = dmanow - dmastart;
2262 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2263 " next 0x%08x\n",
2264 mmc_hostname(host->mmc), dmastart,
2265 host->data->bytes_xfered, dmanow);
2266 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2267 }
Pierre Ossman6ba736a2007-05-13 22:39:23 +02002268
Pierre Ossmane538fbe2007-08-12 16:46:32 +02002269 if (intmask & SDHCI_INT_DATA_END) {
2270 if (host->cmd) {
2271 /*
2272 * Data managed to finish before the
2273 * command completed. Make sure we do
2274 * things in the proper order.
2275 */
2276 host->data_early = 1;
2277 } else {
2278 sdhci_finish_data(host);
2279 }
2280 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002281 }
2282}
2283
David Howells7d12e782006-10-05 14:55:46 +01002284static irqreturn_t sdhci_irq(int irq, void *dev_id)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002285{
2286 irqreturn_t result;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002287 struct sdhci_host *host = dev_id;
Alexander Stein6379b232012-03-14 09:52:10 +01002288 u32 intmask, unexpected = 0;
2289 int cardint = 0, max_loops = 16;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002290
2291 spin_lock(&host->lock);
2292
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002293 if (host->runtime_suspended) {
2294 spin_unlock(&host->lock);
Girish K Sa3c76eb2011-10-11 11:44:09 +05302295 pr_warning("%s: got irq while runtime suspended\n",
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002296 mmc_hostname(host->mmc));
2297 return IRQ_HANDLED;
2298 }
2299
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002300 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002301
Mark Lord62df67a52007-03-06 13:30:13 +01002302 if (!intmask || intmask == 0xffffffff) {
Pierre Ossmand129bce2006-03-24 03:18:17 -08002303 result = IRQ_NONE;
2304 goto out;
2305 }
2306
Alexander Stein6379b232012-03-14 09:52:10 +01002307again:
Pierre Ossmanb69c9052008-03-08 23:44:25 +01002308 DBG("*** %s got interrupt: 0x%08x\n",
2309 mmc_hostname(host->mmc), intmask);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002310
Pierre Ossman3192a282006-06-30 02:22:26 -07002311 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
Shawn Guod25928d2011-06-21 22:41:48 +08002312 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2313 SDHCI_CARD_PRESENT;
2314
2315 /*
2316 * There is a observation on i.mx esdhc. INSERT bit will be
2317 * immediately set again when it gets cleared, if a card is
2318 * inserted. We have to mask the irq to prevent interrupt
2319 * storm which will freeze the system. And the REMOVE gets
2320 * the same situation.
2321 *
2322 * More testing are needed here to ensure it works for other
2323 * platforms though.
2324 */
2325 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2326 SDHCI_INT_CARD_REMOVE);
2327 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2328 SDHCI_INT_CARD_INSERT);
2329
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002330 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
Shawn Guod25928d2011-06-21 22:41:48 +08002331 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2332 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002333 tasklet_schedule(&host->card_tasklet);
Pierre Ossman3192a282006-06-30 02:22:26 -07002334 }
2335
Pierre Ossmand129bce2006-03-24 03:18:17 -08002336 if (intmask & SDHCI_INT_CMD_MASK) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002337 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2338 SDHCI_INT_STATUS);
Pierre Ossman3192a282006-06-30 02:22:26 -07002339 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002340 }
2341
2342 if (intmask & SDHCI_INT_DATA_MASK) {
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002343 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2344 SDHCI_INT_STATUS);
Pierre Ossman3192a282006-06-30 02:22:26 -07002345 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002346 }
2347
2348 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2349
Pierre Ossman964f9ce2007-07-20 18:20:36 +02002350 intmask &= ~SDHCI_INT_ERROR;
2351
Pierre Ossmand129bce2006-03-24 03:18:17 -08002352 if (intmask & SDHCI_INT_BUS_POWER) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302353 pr_err("%s: Card is consuming too much power!\n",
Pierre Ossmand129bce2006-03-24 03:18:17 -08002354 mmc_hostname(host->mmc));
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002355 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002356 }
2357
Rolf Eike Beer9d26a5d2007-06-26 13:31:16 +02002358 intmask &= ~SDHCI_INT_BUS_POWER;
Pierre Ossman3192a282006-06-30 02:22:26 -07002359
Pierre Ossmanf75979b2007-09-04 07:59:18 +02002360 if (intmask & SDHCI_INT_CARD_INT)
2361 cardint = 1;
2362
2363 intmask &= ~SDHCI_INT_CARD_INT;
2364
Pierre Ossman3192a282006-06-30 02:22:26 -07002365 if (intmask) {
Alexander Stein6379b232012-03-14 09:52:10 +01002366 unexpected |= intmask;
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002367 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
Pierre Ossman3192a282006-06-30 02:22:26 -07002368 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002369
2370 result = IRQ_HANDLED;
2371
Alexander Stein6379b232012-03-14 09:52:10 +01002372 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2373 if (intmask && --max_loops)
2374 goto again;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002375out:
2376 spin_unlock(&host->lock);
2377
Alexander Stein6379b232012-03-14 09:52:10 +01002378 if (unexpected) {
2379 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2380 mmc_hostname(host->mmc), unexpected);
2381 sdhci_dumpregs(host);
2382 }
Pierre Ossmanf75979b2007-09-04 07:59:18 +02002383 /*
2384 * We have to delay this as it calls back into the driver.
2385 */
2386 if (cardint)
2387 mmc_signal_sdio_irq(host->mmc);
2388
Pierre Ossmand129bce2006-03-24 03:18:17 -08002389 return result;
2390}
2391
2392/*****************************************************************************\
2393 * *
2394 * Suspend/resume *
2395 * *
2396\*****************************************************************************/
2397
2398#ifdef CONFIG_PM
2399
Manuel Lauss29495aa2011-11-03 11:09:45 +01002400int sdhci_suspend_host(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002401{
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002402 int ret;
Aaron Lu38a60ea2012-01-04 10:07:43 +08002403 bool has_tuning_timer;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002404
Chris Balla1b13b42012-02-06 00:43:59 -05002405 if (host->ops->platform_suspend)
2406 host->ops->platform_suspend(host);
2407
Anton Vorontsov7260cf52009-03-17 00:13:48 +03002408 sdhci_disable_card_detection(host);
2409
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302410 /* Disable tuning since we are suspending */
Aaron Lu38a60ea2012-01-04 10:07:43 +08002411 has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2412 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2413 if (has_tuning_timer) {
Aaron Luc6ced0d2011-12-28 11:11:12 +08002414 del_timer_sync(&host->tuning_timer);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302415 host->flags &= ~SDHCI_NEEDS_RETUNING;
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302416 }
2417
Matt Fleming1a13f8f2010-05-26 14:42:08 -07002418 ret = mmc_suspend_host(host->mmc);
Aaron Lu38a60ea2012-01-04 10:07:43 +08002419 if (ret) {
2420 if (has_tuning_timer) {
2421 host->flags |= SDHCI_NEEDS_RETUNING;
2422 mod_timer(&host->tuning_timer, jiffies +
2423 host->tuning_count * HZ);
2424 }
2425
2426 sdhci_enable_card_detection(host);
2427
Pierre Ossmandf1c4b72007-01-30 07:55:15 +01002428 return ret;
Aaron Lu38a60ea2012-01-04 10:07:43 +08002429 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002430
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002431 free_irq(host->irq, host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002432
Marek Szyprowski9bea3c82010-08-10 18:01:59 -07002433 return ret;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002434}
2435
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002436EXPORT_SYMBOL_GPL(sdhci_suspend_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002437
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002438int sdhci_resume_host(struct sdhci_host *host)
2439{
2440 int ret;
2441
Richard Röjforsa13abc72009-09-22 16:45:30 -07002442 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002443 if (host->ops->enable_dma)
2444 host->ops->enable_dma(host);
2445 }
2446
2447 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2448 mmc_hostname(host->mmc), host);
2449 if (ret)
2450 return ret;
2451
Adrian Hunter6308d292012-02-07 14:48:54 +02002452 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2453 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2454 /* Card keeps power but host controller does not */
2455 sdhci_init(host, 0);
2456 host->pwr = 0;
2457 host->clock = 0;
2458 sdhci_do_set_ios(host, &host->mmc->ios);
2459 } else {
2460 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2461 mmiowb();
2462 }
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002463
2464 ret = mmc_resume_host(host->mmc);
Anton Vorontsov7260cf52009-03-17 00:13:48 +03002465 sdhci_enable_card_detection(host);
2466
Chris Balla1b13b42012-02-06 00:43:59 -05002467 if (host->ops->platform_resume)
2468 host->ops->platform_resume(host);
2469
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302470 /* Set the re-tuning expiration flag */
2471 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2472 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2473 host->flags |= SDHCI_NEEDS_RETUNING;
2474
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -08002475 return ret;
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002476}
2477
2478EXPORT_SYMBOL_GPL(sdhci_resume_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002479
Daniel Drake5f619702010-11-04 22:20:39 +00002480void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2481{
2482 u8 val;
2483 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2484 val |= SDHCI_WAKE_ON_INT;
2485 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2486}
2487
2488EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2489
Pierre Ossmand129bce2006-03-24 03:18:17 -08002490#endif /* CONFIG_PM */
2491
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002492#ifdef CONFIG_PM_RUNTIME
2493
2494static int sdhci_runtime_pm_get(struct sdhci_host *host)
2495{
2496 return pm_runtime_get_sync(host->mmc->parent);
2497}
2498
2499static int sdhci_runtime_pm_put(struct sdhci_host *host)
2500{
2501 pm_runtime_mark_last_busy(host->mmc->parent);
2502 return pm_runtime_put_autosuspend(host->mmc->parent);
2503}
2504
2505int sdhci_runtime_suspend_host(struct sdhci_host *host)
2506{
2507 unsigned long flags;
2508 int ret = 0;
2509
2510 /* Disable tuning since we are suspending */
2511 if (host->version >= SDHCI_SPEC_300 &&
2512 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2513 del_timer_sync(&host->tuning_timer);
2514 host->flags &= ~SDHCI_NEEDS_RETUNING;
2515 }
2516
2517 spin_lock_irqsave(&host->lock, flags);
2518 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2519 spin_unlock_irqrestore(&host->lock, flags);
2520
2521 synchronize_irq(host->irq);
2522
2523 spin_lock_irqsave(&host->lock, flags);
2524 host->runtime_suspended = true;
2525 spin_unlock_irqrestore(&host->lock, flags);
2526
2527 return ret;
2528}
2529EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2530
2531int sdhci_runtime_resume_host(struct sdhci_host *host)
2532{
2533 unsigned long flags;
2534 int ret = 0, host_flags = host->flags;
2535
2536 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2537 if (host->ops->enable_dma)
2538 host->ops->enable_dma(host);
2539 }
2540
2541 sdhci_init(host, 0);
2542
2543 /* Force clock and power re-program */
2544 host->pwr = 0;
2545 host->clock = 0;
2546 sdhci_do_set_ios(host, &host->mmc->ios);
2547
2548 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2549 if (host_flags & SDHCI_PV_ENABLED)
2550 sdhci_do_enable_preset_value(host, true);
2551
2552 /* Set the re-tuning expiration flag */
2553 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2554 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2555 host->flags |= SDHCI_NEEDS_RETUNING;
2556
2557 spin_lock_irqsave(&host->lock, flags);
2558
2559 host->runtime_suspended = false;
2560
2561 /* Enable SDIO IRQ */
2562 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2563 sdhci_enable_sdio_irq_nolock(host, true);
2564
2565 /* Enable Card Detection */
2566 sdhci_enable_card_detection(host);
2567
2568 spin_unlock_irqrestore(&host->lock, flags);
2569
2570 return ret;
2571}
2572EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2573
2574#endif
2575
Pierre Ossmand129bce2006-03-24 03:18:17 -08002576/*****************************************************************************\
2577 * *
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002578 * Device allocation/registration *
Pierre Ossmand129bce2006-03-24 03:18:17 -08002579 * *
2580\*****************************************************************************/
2581
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002582struct sdhci_host *sdhci_alloc_host(struct device *dev,
2583 size_t priv_size)
Pierre Ossmand129bce2006-03-24 03:18:17 -08002584{
Pierre Ossmand129bce2006-03-24 03:18:17 -08002585 struct mmc_host *mmc;
2586 struct sdhci_host *host;
2587
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002588 WARN_ON(dev == NULL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002589
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002590 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002591 if (!mmc)
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002592 return ERR_PTR(-ENOMEM);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002593
2594 host = mmc_priv(mmc);
2595 host->mmc = mmc;
2596
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002597 return host;
2598}
Pierre Ossman8a4da142006-10-04 02:15:40 -07002599
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002600EXPORT_SYMBOL_GPL(sdhci_alloc_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002601
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002602int sdhci_add_host(struct sdhci_host *host)
2603{
2604 struct mmc_host *mmc;
Philip Rakitybd6a8c32012-06-27 21:49:27 -07002605 u32 caps[2] = {0, 0};
Arindam Nathf2119df2011-05-05 12:18:57 +05302606 u32 max_current_caps;
2607 unsigned int ocr_avail;
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002608 int ret;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002609
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002610 WARN_ON(host == NULL);
2611 if (host == NULL)
2612 return -EINVAL;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002613
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002614 mmc = host->mmc;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002615
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002616 if (debug_quirks)
2617 host->quirks = debug_quirks;
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03002618 if (debug_quirks2)
2619 host->quirks2 = debug_quirks2;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002620
Pierre Ossmand96649e2006-06-30 02:22:30 -07002621 sdhci_reset(host, SDHCI_RESET_ALL);
2622
Anton Vorontsov4e4141a2009-03-17 00:13:46 +03002623 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Pierre Ossman2134a922008-06-28 18:28:51 +02002624 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2625 >> SDHCI_SPEC_VER_SHIFT;
Zhangfei Gao85105c52010-08-06 07:10:01 +08002626 if (host->version > SDHCI_SPEC_300) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302627 pr_err("%s: Unknown controller version (%d). "
Pierre Ossmanb69c9052008-03-08 23:44:25 +01002628 "You may experience problems.\n", mmc_hostname(mmc),
Pierre Ossman2134a922008-06-28 18:28:51 +02002629 host->version);
Pierre Ossman4a965502006-06-30 02:22:29 -07002630 }
2631
Arindam Nathf2119df2011-05-05 12:18:57 +05302632 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
Maxim Levitskyccc92c22010-08-10 18:01:42 -07002633 sdhci_readl(host, SDHCI_CAPABILITIES);
Pierre Ossmand129bce2006-03-24 03:18:17 -08002634
Philip Rakitybd6a8c32012-06-27 21:49:27 -07002635 if (host->version >= SDHCI_SPEC_300)
2636 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2637 host->caps1 :
2638 sdhci_readl(host, SDHCI_CAPABILITIES_1);
Arindam Nathf2119df2011-05-05 12:18:57 +05302639
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002640 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
Richard Röjforsa13abc72009-09-22 16:45:30 -07002641 host->flags |= SDHCI_USE_SDMA;
Arindam Nathf2119df2011-05-05 12:18:57 +05302642 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
Richard Röjforsa13abc72009-09-22 16:45:30 -07002643 DBG("Controller doesn't have SDMA capability\n");
Pierre Ossman67435272006-06-30 02:22:31 -07002644 else
Richard Röjforsa13abc72009-09-22 16:45:30 -07002645 host->flags |= SDHCI_USE_SDMA;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002646
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002647 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
Richard Röjforsa13abc72009-09-22 16:45:30 -07002648 (host->flags & SDHCI_USE_SDMA)) {
Rolf Eike Beercee687c2007-11-02 15:22:30 +01002649 DBG("Disabling DMA as it is marked broken\n");
Richard Röjforsa13abc72009-09-22 16:45:30 -07002650 host->flags &= ~SDHCI_USE_SDMA;
Feng Tang7c168e32007-09-30 12:44:18 +02002651 }
2652
Arindam Nathf2119df2011-05-05 12:18:57 +05302653 if ((host->version >= SDHCI_SPEC_200) &&
2654 (caps[0] & SDHCI_CAN_DO_ADMA2))
Richard Röjforsa13abc72009-09-22 16:45:30 -07002655 host->flags |= SDHCI_USE_ADMA;
Pierre Ossman2134a922008-06-28 18:28:51 +02002656
2657 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2658 (host->flags & SDHCI_USE_ADMA)) {
2659 DBG("Disabling ADMA as it is marked broken\n");
2660 host->flags &= ~SDHCI_USE_ADMA;
2661 }
2662
Richard Röjforsa13abc72009-09-22 16:45:30 -07002663 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002664 if (host->ops->enable_dma) {
2665 if (host->ops->enable_dma(host)) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302666 pr_warning("%s: No suitable DMA "
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002667 "available. Falling back to PIO.\n",
2668 mmc_hostname(mmc));
Richard Röjforsa13abc72009-09-22 16:45:30 -07002669 host->flags &=
2670 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002671 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002672 }
2673 }
2674
Pierre Ossman2134a922008-06-28 18:28:51 +02002675 if (host->flags & SDHCI_USE_ADMA) {
2676 /*
2677 * We need to allocate descriptors for all sg entries
2678 * (128) and potentially one alignment transfer for
2679 * each of those entries.
2680 */
2681 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2682 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2683 if (!host->adma_desc || !host->align_buffer) {
2684 kfree(host->adma_desc);
2685 kfree(host->align_buffer);
Girish K Sa3c76eb2011-10-11 11:44:09 +05302686 pr_warning("%s: Unable to allocate ADMA "
Pierre Ossman2134a922008-06-28 18:28:51 +02002687 "buffers. Falling back to standard DMA.\n",
2688 mmc_hostname(mmc));
2689 host->flags &= ~SDHCI_USE_ADMA;
2690 }
2691 }
2692
Pierre Ossman76591502008-07-21 00:32:11 +02002693 /*
2694 * If we use DMA, then it's up to the caller to set the DMA
2695 * mask, but PIO does not need the hw shim so we set a new
2696 * mask here in that case.
2697 */
Richard Röjforsa13abc72009-09-22 16:45:30 -07002698 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
Pierre Ossman76591502008-07-21 00:32:11 +02002699 host->dma_mask = DMA_BIT_MASK(64);
2700 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2701 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002702
Zhangfei Gaoc4687d52010-08-20 14:02:36 -04002703 if (host->version >= SDHCI_SPEC_300)
Arindam Nathf2119df2011-05-05 12:18:57 +05302704 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
Zhangfei Gaoc4687d52010-08-20 14:02:36 -04002705 >> SDHCI_CLOCK_BASE_SHIFT;
2706 else
Arindam Nathf2119df2011-05-05 12:18:57 +05302707 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
Zhangfei Gaoc4687d52010-08-20 14:02:36 -04002708 >> SDHCI_CLOCK_BASE_SHIFT;
2709
Pierre Ossmand129bce2006-03-24 03:18:17 -08002710 host->max_clk *= 1000000;
Anton Vorontsovf27f47e2010-05-26 14:41:53 -07002711 if (host->max_clk == 0 || host->quirks &
2712 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
Ben Dooks4240ff02009-03-17 00:13:57 +03002713 if (!host->ops->get_max_clock) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302714 pr_err("%s: Hardware doesn't specify base clock "
Ben Dooks4240ff02009-03-17 00:13:57 +03002715 "frequency.\n", mmc_hostname(mmc));
2716 return -ENODEV;
2717 }
2718 host->max_clk = host->ops->get_max_clock(host);
2719 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08002720
2721 /*
Arindam Nathc3ed3872011-05-05 12:19:06 +05302722 * In case of Host Controller v3.00, find out whether clock
2723 * multiplier is supported.
2724 */
2725 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2726 SDHCI_CLOCK_MUL_SHIFT;
2727
2728 /*
2729 * In case the value in Clock Multiplier is 0, then programmable
2730 * clock mode is not supported, otherwise the actual clock
2731 * multiplier is one more than the value of Clock Multiplier
2732 * in the Capabilities Register.
2733 */
2734 if (host->clk_mul)
2735 host->clk_mul += 1;
2736
2737 /*
Pierre Ossmand129bce2006-03-24 03:18:17 -08002738 * Set host parameters.
2739 */
2740 mmc->ops = &sdhci_ops;
Arindam Nathc3ed3872011-05-05 12:19:06 +05302741 mmc->f_max = host->max_clk;
Marek Szyprowskice5f0362010-08-10 18:01:56 -07002742 if (host->ops->get_min_clock)
Anton Vorontsova9e58f22009-07-29 15:04:16 -07002743 mmc->f_min = host->ops->get_min_clock(host);
Arindam Nathc3ed3872011-05-05 12:19:06 +05302744 else if (host->version >= SDHCI_SPEC_300) {
2745 if (host->clk_mul) {
2746 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2747 mmc->f_max = host->max_clk * host->clk_mul;
2748 } else
2749 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2750 } else
Zhangfei Gao03975262010-09-20 15:15:18 -04002751 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
Philip Rakity15ec4462010-11-19 16:48:39 -05002752
Andy Shevchenko272308c2011-08-03 18:36:00 +03002753 host->timeout_clk =
2754 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2755 if (host->timeout_clk == 0) {
2756 if (host->ops->get_timeout_clock) {
2757 host->timeout_clk = host->ops->get_timeout_clock(host);
2758 } else if (!(host->quirks &
2759 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302760 pr_err("%s: Hardware doesn't specify timeout clock "
Andy Shevchenko272308c2011-08-03 18:36:00 +03002761 "frequency.\n", mmc_hostname(mmc));
2762 return -ENODEV;
2763 }
2764 }
2765 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2766 host->timeout_clk *= 1000;
2767
2768 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
Andy Shevchenko65be3fe2011-08-03 18:36:01 +03002769 host->timeout_clk = mmc->f_max / 1000;
Andy Shevchenko272308c2011-08-03 18:36:00 +03002770
Andy Shevchenko65be3fe2011-08-03 18:36:01 +03002771 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
Adrian Hunter58d12462011-06-28 17:16:03 +03002772
Andrei Warkentine89d4562011-05-23 15:06:37 -05002773 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2774
2775 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2776 host->flags |= SDHCI_AUTO_CMD12;
Anton Vorontsov5fe23c72009-06-18 00:14:08 +04002777
Andrei Warkentin8edf63712011-05-23 15:06:39 -05002778 /* Auto-CMD23 stuff only works in ADMA or PIO. */
Andrei Warkentin4f3d3e92011-05-25 10:42:50 -04002779 if ((host->version >= SDHCI_SPEC_300) &&
Andrei Warkentin8edf63712011-05-23 15:06:39 -05002780 ((host->flags & SDHCI_USE_ADMA) ||
Andrei Warkentin4f3d3e92011-05-25 10:42:50 -04002781 !(host->flags & SDHCI_USE_SDMA))) {
Andrei Warkentin8edf63712011-05-23 15:06:39 -05002782 host->flags |= SDHCI_AUTO_CMD23;
2783 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2784 } else {
2785 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2786 }
2787
Philip Rakity15ec4462010-11-19 16:48:39 -05002788 /*
2789 * A controller may support 8-bit width, but the board itself
2790 * might not have the pins brought out. Boards that support
2791 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2792 * their platform code before calling sdhci_add_host(), and we
2793 * won't assume 8-bit width for hosts without that CAP.
2794 */
Anton Vorontsov5fe23c72009-06-18 00:14:08 +04002795 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
Philip Rakity15ec4462010-11-19 16:48:39 -05002796 mmc->caps |= MMC_CAP_4_BIT_DATA;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002797
Arindam Nathf2119df2011-05-05 12:18:57 +05302798 if (caps[0] & SDHCI_CAN_DO_HISPD)
Zhangfei Gaoa29e7e12010-08-16 21:15:32 -04002799 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
Pierre Ossmancd9277c2007-02-18 12:07:47 +01002800
Jaehoon Chung176d1ed2010-09-27 09:42:20 +01002801 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2802 mmc_card_is_removable(mmc))
Anton Vorontsov68d1fb72009-03-17 00:13:52 +03002803 mmc->caps |= MMC_CAP_NEEDS_POLL;
2804
Al Cooper4188bba2012-03-16 15:54:17 -04002805 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2806 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2807 SDHCI_SUPPORT_DDR50))
Arindam Nathf2119df2011-05-05 12:18:57 +05302808 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2809
2810 /* SDR104 supports also implies SDR50 support */
2811 if (caps[1] & SDHCI_SUPPORT_SDR104)
2812 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2813 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2814 mmc->caps |= MMC_CAP_UHS_SDR50;
2815
2816 if (caps[1] & SDHCI_SUPPORT_DDR50)
2817 mmc->caps |= MMC_CAP_UHS_DDR50;
2818
Girish K S069c9f12012-01-06 09:56:39 +05302819 /* Does the host need tuning for SDR50? */
Arindam Nathb513ea22011-05-05 12:19:04 +05302820 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2821 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2822
Girish K S069c9f12012-01-06 09:56:39 +05302823 /* Does the host need tuning for HS200? */
2824 if (mmc->caps2 & MMC_CAP2_HS200)
2825 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2826
Arindam Nathd6d50a12011-05-05 12:18:59 +05302827 /* Driver Type(s) (A, C, D) supported by the host */
2828 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2829 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2830 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2831 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2832 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2833 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2834
Girish K Sbec87262011-10-13 12:04:16 +05302835 /*
2836 * If Power Off Notify capability is enabled by the host,
2837 * set notify to short power off notify timeout value.
2838 */
2839 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2840 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2841 else
2842 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2843
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05302844 /* Initial value for re-tuning timer count */
2845 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2846 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2847
2848 /*
2849 * In case Re-tuning Timer is not disabled, the actual value of
2850 * re-tuning timer will be 2 ^ (n - 1).
2851 */
2852 if (host->tuning_count)
2853 host->tuning_count = 1 << (host->tuning_count - 1);
2854
2855 /* Re-tuning mode supported by the Host Controller */
2856 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2857 SDHCI_RETUNING_MODE_SHIFT;
2858
Takashi Iwai8f230f42010-12-08 10:04:30 +01002859 ocr_avail = 0;
Philip Rakitybad37e12012-05-27 18:36:44 -07002860
2861 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2862 if (IS_ERR(host->vmmc)) {
2863 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2864 host->vmmc = NULL;
2865 }
2866
Philip Rakity68737042012-06-08 12:26:13 -07002867#ifdef CONFIG_REGULATOR
2868 if (host->vmmc) {
2869 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2870 3300000);
2871 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2872 caps[0] &= ~SDHCI_CAN_VDD_330;
2873 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2874 3000000);
2875 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2876 caps[0] &= ~SDHCI_CAN_VDD_300;
2877 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2878 1800000);
2879 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2880 caps[0] &= ~SDHCI_CAN_VDD_180;
2881 }
2882#endif /* CONFIG_REGULATOR */
2883
Arindam Nathf2119df2011-05-05 12:18:57 +05302884 /*
2885 * According to SD Host Controller spec v3.00, if the Host System
2886 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2887 * the value is meaningful only if Voltage Support in the Capabilities
2888 * register is set. The actual current value is 4 times the register
2889 * value.
2890 */
2891 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
Philip Rakitybad37e12012-05-27 18:36:44 -07002892 if (!max_current_caps && host->vmmc) {
2893 u32 curr = regulator_get_current_limit(host->vmmc);
2894 if (curr > 0) {
2895
2896 /* convert to SDHCI_MAX_CURRENT format */
2897 curr = curr/1000; /* convert to mA */
2898 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2899
2900 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2901 max_current_caps =
2902 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2903 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2904 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2905 }
2906 }
Arindam Nathf2119df2011-05-05 12:18:57 +05302907
2908 if (caps[0] & SDHCI_CAN_VDD_330) {
2909 int max_current_330;
2910
Takashi Iwai8f230f42010-12-08 10:04:30 +01002911 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
Arindam Nathf2119df2011-05-05 12:18:57 +05302912
2913 max_current_330 = ((max_current_caps &
2914 SDHCI_MAX_CURRENT_330_MASK) >>
2915 SDHCI_MAX_CURRENT_330_SHIFT) *
2916 SDHCI_MAX_CURRENT_MULTIPLIER;
2917
2918 if (max_current_330 > 150)
2919 mmc->caps |= MMC_CAP_SET_XPC_330;
2920 }
2921 if (caps[0] & SDHCI_CAN_VDD_300) {
2922 int max_current_300;
2923
Takashi Iwai8f230f42010-12-08 10:04:30 +01002924 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
Arindam Nathf2119df2011-05-05 12:18:57 +05302925
2926 max_current_300 = ((max_current_caps &
2927 SDHCI_MAX_CURRENT_300_MASK) >>
2928 SDHCI_MAX_CURRENT_300_SHIFT) *
2929 SDHCI_MAX_CURRENT_MULTIPLIER;
2930
2931 if (max_current_300 > 150)
2932 mmc->caps |= MMC_CAP_SET_XPC_300;
2933 }
2934 if (caps[0] & SDHCI_CAN_VDD_180) {
2935 int max_current_180;
2936
Takashi Iwai8f230f42010-12-08 10:04:30 +01002937 ocr_avail |= MMC_VDD_165_195;
2938
Arindam Nathf2119df2011-05-05 12:18:57 +05302939 max_current_180 = ((max_current_caps &
2940 SDHCI_MAX_CURRENT_180_MASK) >>
2941 SDHCI_MAX_CURRENT_180_SHIFT) *
2942 SDHCI_MAX_CURRENT_MULTIPLIER;
2943
2944 if (max_current_180 > 150)
2945 mmc->caps |= MMC_CAP_SET_XPC_180;
Arindam Nath5371c922011-05-05 12:19:02 +05302946
2947 /* Maximum current capabilities of the host at 1.8V */
2948 if (max_current_180 >= 800)
2949 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2950 else if (max_current_180 >= 600)
2951 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2952 else if (max_current_180 >= 400)
2953 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
Philip Rakity0aa67702012-05-27 18:36:33 -07002954 else if (max_current_180 >= 200)
Arindam Nath5371c922011-05-05 12:19:02 +05302955 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
Arindam Nathf2119df2011-05-05 12:18:57 +05302956 }
2957
Takashi Iwai8f230f42010-12-08 10:04:30 +01002958 mmc->ocr_avail = ocr_avail;
2959 mmc->ocr_avail_sdio = ocr_avail;
2960 if (host->ocr_avail_sdio)
2961 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2962 mmc->ocr_avail_sd = ocr_avail;
2963 if (host->ocr_avail_sd)
2964 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2965 else /* normal SD controllers don't support 1.8V */
2966 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2967 mmc->ocr_avail_mmc = ocr_avail;
2968 if (host->ocr_avail_mmc)
2969 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
Pierre Ossman146ad662006-06-30 02:22:23 -07002970
2971 if (mmc->ocr_avail == 0) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05302972 pr_err("%s: Hardware doesn't report any "
Pierre Ossmanb69c9052008-03-08 23:44:25 +01002973 "support voltages.\n", mmc_hostname(mmc));
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01002974 return -ENODEV;
Pierre Ossman146ad662006-06-30 02:22:23 -07002975 }
2976
Pierre Ossmand129bce2006-03-24 03:18:17 -08002977 spin_lock_init(&host->lock);
2978
2979 /*
Pierre Ossman2134a922008-06-28 18:28:51 +02002980 * Maximum number of segments. Depends on if the hardware
2981 * can do scatter/gather or not.
Pierre Ossmand129bce2006-03-24 03:18:17 -08002982 */
Pierre Ossman2134a922008-06-28 18:28:51 +02002983 if (host->flags & SDHCI_USE_ADMA)
Martin K. Petersena36274e2010-09-10 01:33:59 -04002984 mmc->max_segs = 128;
Richard Röjforsa13abc72009-09-22 16:45:30 -07002985 else if (host->flags & SDHCI_USE_SDMA)
Martin K. Petersena36274e2010-09-10 01:33:59 -04002986 mmc->max_segs = 1;
Pierre Ossman2134a922008-06-28 18:28:51 +02002987 else /* PIO */
Martin K. Petersena36274e2010-09-10 01:33:59 -04002988 mmc->max_segs = 128;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002989
2990 /*
Pierre Ossmanbab76962006-07-02 16:51:35 +01002991 * Maximum number of sectors in one transfer. Limited by DMA boundary
Pierre Ossman55db8902006-11-21 17:55:45 +01002992 * size (512KiB).
Pierre Ossmand129bce2006-03-24 03:18:17 -08002993 */
Pierre Ossman55db8902006-11-21 17:55:45 +01002994 mmc->max_req_size = 524288;
Pierre Ossmand129bce2006-03-24 03:18:17 -08002995
2996 /*
2997 * Maximum segment size. Could be one segment with the maximum number
Pierre Ossman2134a922008-06-28 18:28:51 +02002998 * of bytes. When doing hardware scatter/gather, each entry cannot
2999 * be larger than 64 KiB though.
Pierre Ossmand129bce2006-03-24 03:18:17 -08003000 */
Olof Johansson30652aa2011-01-01 18:37:32 -06003001 if (host->flags & SDHCI_USE_ADMA) {
3002 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3003 mmc->max_seg_size = 65535;
3004 else
3005 mmc->max_seg_size = 65536;
3006 } else {
Pierre Ossman2134a922008-06-28 18:28:51 +02003007 mmc->max_seg_size = mmc->max_req_size;
Olof Johansson30652aa2011-01-01 18:37:32 -06003008 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08003009
3010 /*
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01003011 * Maximum block size. This varies from controller to controller and
3012 * is specified in the capabilities register.
3013 */
Anton Vorontsov0633f652009-03-17 00:14:03 +03003014 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3015 mmc->max_blk_size = 2;
3016 } else {
Arindam Nathf2119df2011-05-05 12:18:57 +05303017 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
Anton Vorontsov0633f652009-03-17 00:14:03 +03003018 SDHCI_MAX_BLOCK_SHIFT;
3019 if (mmc->max_blk_size >= 3) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05303020 pr_warning("%s: Invalid maximum block size, "
Anton Vorontsov0633f652009-03-17 00:14:03 +03003021 "assuming 512 bytes\n", mmc_hostname(mmc));
3022 mmc->max_blk_size = 0;
3023 }
3024 }
3025
3026 mmc->max_blk_size = 512 << mmc->max_blk_size;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01003027
3028 /*
Pierre Ossman55db8902006-11-21 17:55:45 +01003029 * Maximum block count.
3030 */
Ben Dooks1388eef2009-06-14 12:40:53 +01003031 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
Pierre Ossman55db8902006-11-21 17:55:45 +01003032
3033 /*
Pierre Ossmand129bce2006-03-24 03:18:17 -08003034 * Init tasklets.
3035 */
3036 tasklet_init(&host->card_tasklet,
3037 sdhci_tasklet_card, (unsigned long)host);
3038 tasklet_init(&host->finish_tasklet,
3039 sdhci_tasklet_finish, (unsigned long)host);
3040
Al Viroe4cad1b2006-10-10 22:47:07 +01003041 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003042
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05303043 if (host->version >= SDHCI_SPEC_300) {
Arindam Nathb513ea22011-05-05 12:19:04 +05303044 init_waitqueue_head(&host->buf_ready_int);
3045
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05303046 /* Initialize re-tuning timer */
3047 init_timer(&host->tuning_timer);
3048 host->tuning_timer.data = (unsigned long)host;
3049 host->tuning_timer.function = sdhci_tuning_timer;
3050 }
3051
Thomas Gleixnerdace1452006-07-01 19:29:38 -07003052 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
Pierre Ossmanb69c9052008-03-08 23:44:25 +01003053 mmc_hostname(mmc), host);
Mark Brown0fc81ee2012-07-02 14:26:15 +01003054 if (ret) {
3055 pr_err("%s: Failed to request IRQ %d: %d\n",
3056 mmc_hostname(mmc), host->irq, ret);
Pierre Ossman8ef1a142006-06-30 02:22:21 -07003057 goto untasklet;
Mark Brown0fc81ee2012-07-02 14:26:15 +01003058 }
Pierre Ossmand129bce2006-03-24 03:18:17 -08003059
Nicolas Pitre2f4cbb32010-03-05 13:43:32 -08003060 sdhci_init(host, 0);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003061
3062#ifdef CONFIG_MMC_DEBUG
3063 sdhci_dumpregs(host);
3064#endif
3065
Pierre Ossmanf9134312008-12-21 17:01:48 +01003066#ifdef SDHCI_USE_LEDS_CLASS
Helmut Schaa5dbace02009-02-14 16:22:39 +01003067 snprintf(host->led_name, sizeof(host->led_name),
3068 "%s::", mmc_hostname(mmc));
3069 host->led.name = host->led_name;
Pierre Ossman2f730fe2008-03-17 10:29:38 +01003070 host->led.brightness = LED_OFF;
3071 host->led.default_trigger = mmc_hostname(mmc);
3072 host->led.brightness_set = sdhci_led_control;
3073
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003074 ret = led_classdev_register(mmc_dev(mmc), &host->led);
Mark Brown0fc81ee2012-07-02 14:26:15 +01003075 if (ret) {
3076 pr_err("%s: Failed to register LED device: %d\n",
3077 mmc_hostname(mmc), ret);
Pierre Ossman2f730fe2008-03-17 10:29:38 +01003078 goto reset;
Mark Brown0fc81ee2012-07-02 14:26:15 +01003079 }
Pierre Ossman2f730fe2008-03-17 10:29:38 +01003080#endif
3081
Pierre Ossman5f25a662006-10-04 02:15:39 -07003082 mmiowb();
3083
Pierre Ossmand129bce2006-03-24 03:18:17 -08003084 mmc_add_host(mmc);
3085
Girish K Sa3c76eb2011-10-11 11:44:09 +05303086 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
Kay Sieversd1b26862008-11-08 21:37:46 +01003087 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
Richard Röjforsa13abc72009-09-22 16:45:30 -07003088 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3089 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
Pierre Ossmand129bce2006-03-24 03:18:17 -08003090
Anton Vorontsov7260cf52009-03-17 00:13:48 +03003091 sdhci_enable_card_detection(host);
3092
Pierre Ossmand129bce2006-03-24 03:18:17 -08003093 return 0;
3094
Pierre Ossmanf9134312008-12-21 17:01:48 +01003095#ifdef SDHCI_USE_LEDS_CLASS
Pierre Ossman2f730fe2008-03-17 10:29:38 +01003096reset:
3097 sdhci_reset(host, SDHCI_RESET_ALL);
3098 free_irq(host->irq, host);
3099#endif
Pierre Ossman8ef1a142006-06-30 02:22:21 -07003100untasklet:
Pierre Ossmand129bce2006-03-24 03:18:17 -08003101 tasklet_kill(&host->card_tasklet);
3102 tasklet_kill(&host->finish_tasklet);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003103
3104 return ret;
3105}
3106
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003107EXPORT_SYMBOL_GPL(sdhci_add_host);
3108
Pierre Ossman1e728592008-04-16 19:13:13 +02003109void sdhci_remove_host(struct sdhci_host *host, int dead)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003110{
Pierre Ossman1e728592008-04-16 19:13:13 +02003111 unsigned long flags;
3112
3113 if (dead) {
3114 spin_lock_irqsave(&host->lock, flags);
3115
3116 host->flags |= SDHCI_DEVICE_DEAD;
3117
3118 if (host->mrq) {
Girish K Sa3c76eb2011-10-11 11:44:09 +05303119 pr_err("%s: Controller removed during "
Pierre Ossman1e728592008-04-16 19:13:13 +02003120 " transfer!\n", mmc_hostname(host->mmc));
3121
3122 host->mrq->cmd->error = -ENOMEDIUM;
3123 tasklet_schedule(&host->finish_tasklet);
3124 }
3125
3126 spin_unlock_irqrestore(&host->lock, flags);
3127 }
3128
Anton Vorontsov7260cf52009-03-17 00:13:48 +03003129 sdhci_disable_card_detection(host);
3130
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003131 mmc_remove_host(host->mmc);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003132
Pierre Ossmanf9134312008-12-21 17:01:48 +01003133#ifdef SDHCI_USE_LEDS_CLASS
Pierre Ossman2f730fe2008-03-17 10:29:38 +01003134 led_classdev_unregister(&host->led);
3135#endif
3136
Pierre Ossman1e728592008-04-16 19:13:13 +02003137 if (!dead)
3138 sdhci_reset(host, SDHCI_RESET_ALL);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003139
3140 free_irq(host->irq, host);
3141
3142 del_timer_sync(&host->timer);
Arindam Nathcf2b5ee2011-05-05 12:19:07 +05303143 if (host->version >= SDHCI_SPEC_300)
3144 del_timer_sync(&host->tuning_timer);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003145
3146 tasklet_kill(&host->card_tasklet);
3147 tasklet_kill(&host->finish_tasklet);
Pierre Ossman2134a922008-06-28 18:28:51 +02003148
Adrian Hunterceb61432011-12-27 15:48:41 +02003149 if (host->vmmc)
Marek Szyprowski9bea3c82010-08-10 18:01:59 -07003150 regulator_put(host->vmmc);
Marek Szyprowski9bea3c82010-08-10 18:01:59 -07003151
Pierre Ossman2134a922008-06-28 18:28:51 +02003152 kfree(host->adma_desc);
3153 kfree(host->align_buffer);
3154
3155 host->adma_desc = NULL;
3156 host->align_buffer = NULL;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003157}
3158
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003159EXPORT_SYMBOL_GPL(sdhci_remove_host);
3160
3161void sdhci_free_host(struct sdhci_host *host)
Pierre Ossmand129bce2006-03-24 03:18:17 -08003162{
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003163 mmc_free_host(host->mmc);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003164}
3165
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003166EXPORT_SYMBOL_GPL(sdhci_free_host);
Pierre Ossmand129bce2006-03-24 03:18:17 -08003167
3168/*****************************************************************************\
3169 * *
3170 * Driver init/exit *
3171 * *
3172\*****************************************************************************/
3173
3174static int __init sdhci_drv_init(void)
3175{
Girish K Sa3c76eb2011-10-11 11:44:09 +05303176 pr_info(DRIVER_NAME
Pierre Ossman52fbf9c2007-02-09 08:23:41 +01003177 ": Secure Digital Host Controller Interface driver\n");
Girish K Sa3c76eb2011-10-11 11:44:09 +05303178 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
Pierre Ossmand129bce2006-03-24 03:18:17 -08003179
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003180 return 0;
Pierre Ossmand129bce2006-03-24 03:18:17 -08003181}
3182
3183static void __exit sdhci_drv_exit(void)
3184{
Pierre Ossmand129bce2006-03-24 03:18:17 -08003185}
3186
3187module_init(sdhci_drv_init);
3188module_exit(sdhci_drv_exit);
3189
Pierre Ossmandf673b22006-06-30 02:22:31 -07003190module_param(debug_quirks, uint, 0444);
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003191module_param(debug_quirks2, uint, 0444);
Pierre Ossman67435272006-06-30 02:22:31 -07003192
Pierre Ossman32710e82009-04-08 20:14:54 +02003193MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
Pierre Ossmanb8c86fc2008-03-18 17:35:49 +01003194MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
Pierre Ossmand129bce2006-03-24 03:18:17 -08003195MODULE_LICENSE("GPL");
Pierre Ossman67435272006-06-30 02:22:31 -07003196
Pierre Ossmandf673b22006-06-30 02:22:31 -07003197MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Adrian Hunter66fd8ad2011-10-03 15:33:34 +03003198MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");