blob: 97341aa4025c3d152d6c6c75a3e457bfdc3ec610 [file] [log] [blame]
Linus Walleije3726fc2010-08-19 12:36:01 +01001/*
Martin Perssone0befb22010-12-08 15:13:28 +01002 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
Linus Walleije3726fc2010-08-19 12:36:01 +01004 *
5 * License Terms: GNU General Public License v2
Martin Perssone0befb22010-12-08 15:13:28 +01006 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
Linus Walleije3726fc2010-08-19 12:36:01 +01008 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
Martin Perssone0befb22010-12-08 15:13:28 +010010 * U8500 PRCM Unit interface driver
11 *
Linus Walleije3726fc2010-08-19 12:36:01 +010012 */
Linus Walleije3726fc2010-08-19 12:36:01 +010013#include <linux/module.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020014#include <linux/kernel.h>
15#include <linux/delay.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010016#include <linux/errno.h>
17#include <linux/err.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020018#include <linux/spinlock.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010019#include <linux/io.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020020#include <linux/slab.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010021#include <linux/mutex.h>
22#include <linux/completion.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020023#include <linux/irq.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010024#include <linux/jiffies.h>
25#include <linux/bitops.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020026#include <linux/fs.h>
27#include <linux/platform_device.h>
28#include <linux/uaccess.h>
29#include <linux/mfd/core.h>
Mattias Nilsson73180f82011-08-12 10:28:10 +020030#include <linux/mfd/dbx500-prcmu.h>
Bengt Jonsson1032fbf2011-04-01 14:43:33 +020031#include <linux/regulator/db8500-prcmu.h>
32#include <linux/regulator/machine.h>
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +010033#include <asm/hardware/gic.h>
Linus Walleije3726fc2010-08-19 12:36:01 +010034#include <mach/hardware.h>
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020035#include <mach/irqs.h>
36#include <mach/db8500-regs.h>
37#include <mach/id.h>
Mattias Nilsson73180f82011-08-12 10:28:10 +020038#include "dbx500-prcmu-regs.h"
Linus Walleije3726fc2010-08-19 12:36:01 +010039
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020040/* Offset for the firmware version within the TCPM */
41#define PRCMU_FW_VERSION_OFFSET 0xA4
Linus Walleije3726fc2010-08-19 12:36:01 +010042
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020043/* Index of different voltages to be used when accessing AVSData */
44#define PRCM_AVS_BASE 0x2FC
45#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
46#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
47#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
48#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
49#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
50#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
51#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
52#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
53#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
54#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
55#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
56#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
57#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
Martin Perssone0befb22010-12-08 15:13:28 +010058
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020059#define PRCM_AVS_VOLTAGE 0
60#define PRCM_AVS_VOLTAGE_MASK 0x3f
61#define PRCM_AVS_ISSLOWSTARTUP 6
62#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
Martin Perssone0befb22010-12-08 15:13:28 +010063#define PRCM_AVS_ISMODEENABLE 7
64#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
65
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020066#define PRCM_BOOT_STATUS 0xFFF
67#define PRCM_ROMCODE_A2P 0xFFE
68#define PRCM_ROMCODE_P2A 0xFFD
69#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
Linus Walleije3726fc2010-08-19 12:36:01 +010070
Mattias Nilsson3df57bc2011-05-16 00:15:05 +020071#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
72
73#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
74#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
75#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
76#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
77#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
78#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
79#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
80#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
81
82/* Req Mailboxes */
83#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
84#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
85#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
86#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
87#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
88#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
89
90/* Ack Mailboxes */
91#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
92#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
93#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
94#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
95#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
96#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
97
98/* Mailbox 0 headers */
99#define MB0H_POWER_STATE_TRANS 0
100#define MB0H_CONFIG_WAKEUPS_EXE 1
101#define MB0H_READ_WAKEUP_ACK 3
102#define MB0H_CONFIG_WAKEUPS_SLEEP 4
103
104#define MB0H_WAKEUP_EXE 2
105#define MB0H_WAKEUP_SLEEP 5
106
107/* Mailbox 0 REQs */
108#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
109#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
110#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
111#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
112#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
113#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
114
115/* Mailbox 0 ACKs */
116#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
117#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
118#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
119#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
120#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
121#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
122#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
123
124/* Mailbox 1 headers */
125#define MB1H_ARM_APE_OPP 0x0
126#define MB1H_RESET_MODEM 0x2
127#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
128#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
129#define MB1H_RELEASE_USB_WAKEUP 0x5
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200130#define MB1H_PLL_ON_OFF 0x6
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200131
132/* Mailbox 1 Requests */
133#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
134#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200135#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100136#define PLL_SOC0_OFF 0x1
137#define PLL_SOC0_ON 0x2
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200138#define PLL_SOC1_OFF 0x4
139#define PLL_SOC1_ON 0x8
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200140
141/* Mailbox 1 ACKs */
142#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
143#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
144#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
145#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
146
147/* Mailbox 2 headers */
148#define MB2H_DPS 0x0
149#define MB2H_AUTO_PWR 0x1
150
151/* Mailbox 2 REQs */
152#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
153#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
154#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
155#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
156#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
157#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
158#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
159#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
160#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
161#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
162
163/* Mailbox 2 ACKs */
164#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
165#define HWACC_PWR_ST_OK 0xFE
166
167/* Mailbox 3 headers */
168#define MB3H_ANC 0x0
169#define MB3H_SIDETONE 0x1
170#define MB3H_SYSCLK 0xE
171
172/* Mailbox 3 Requests */
173#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
174#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
175#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
176#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
177#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
178#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
179#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
180
181/* Mailbox 4 headers */
182#define MB4H_DDR_INIT 0x0
183#define MB4H_MEM_ST 0x1
184#define MB4H_HOTDOG 0x12
185#define MB4H_HOTMON 0x13
186#define MB4H_HOT_PERIOD 0x14
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200187#define MB4H_A9WDOG_CONF 0x16
188#define MB4H_A9WDOG_EN 0x17
189#define MB4H_A9WDOG_DIS 0x18
190#define MB4H_A9WDOG_LOAD 0x19
191#define MB4H_A9WDOG_KICK 0x20
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200192
193/* Mailbox 4 Requests */
194#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
195#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
196#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
197#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
198#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
199#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
200#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
201#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
202#define HOTMON_CONFIG_LOW BIT(0)
203#define HOTMON_CONFIG_HIGH BIT(1)
Mattias Nilssona592c2e2011-08-12 10:27:41 +0200204#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
205#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
206#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
207#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
208#define A9WDOG_AUTO_OFF_EN BIT(7)
209#define A9WDOG_AUTO_OFF_DIS 0
210#define A9WDOG_ID_MASK 0xf
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200211
212/* Mailbox 5 Requests */
213#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
214#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
215#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
216#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
217#define PRCMU_I2C_WRITE(slave) \
218 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
219#define PRCMU_I2C_READ(slave) \
220 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
221#define PRCMU_I2C_STOP_EN BIT(3)
222
223/* Mailbox 5 ACKs */
224#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
225#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
226#define I2C_WR_OK 0x1
227#define I2C_RD_OK 0x2
228
229#define NUM_MB 8
230#define MBOX_BIT BIT
231#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
232
233/*
234 * Wakeups/IRQs
235 */
236
237#define WAKEUP_BIT_RTC BIT(0)
238#define WAKEUP_BIT_RTT0 BIT(1)
239#define WAKEUP_BIT_RTT1 BIT(2)
240#define WAKEUP_BIT_HSI0 BIT(3)
241#define WAKEUP_BIT_HSI1 BIT(4)
242#define WAKEUP_BIT_CA_WAKE BIT(5)
243#define WAKEUP_BIT_USB BIT(6)
244#define WAKEUP_BIT_ABB BIT(7)
245#define WAKEUP_BIT_ABB_FIFO BIT(8)
246#define WAKEUP_BIT_SYSCLK_OK BIT(9)
247#define WAKEUP_BIT_CA_SLEEP BIT(10)
248#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
249#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
250#define WAKEUP_BIT_ANC_OK BIT(13)
251#define WAKEUP_BIT_SW_ERROR BIT(14)
252#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
253#define WAKEUP_BIT_ARM BIT(17)
254#define WAKEUP_BIT_HOTMON_LOW BIT(18)
255#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
256#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
257#define WAKEUP_BIT_GPIO0 BIT(23)
258#define WAKEUP_BIT_GPIO1 BIT(24)
259#define WAKEUP_BIT_GPIO2 BIT(25)
260#define WAKEUP_BIT_GPIO3 BIT(26)
261#define WAKEUP_BIT_GPIO4 BIT(27)
262#define WAKEUP_BIT_GPIO5 BIT(28)
263#define WAKEUP_BIT_GPIO6 BIT(29)
264#define WAKEUP_BIT_GPIO7 BIT(30)
265#define WAKEUP_BIT_GPIO8 BIT(31)
266
Mattias Nilssonb58d12f2012-01-13 16:20:10 +0100267static struct {
268 bool valid;
269 struct prcmu_fw_version version;
270} fw_info;
271
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200272/*
273 * This vector maps irq numbers to the bits in the bit field used in
274 * communication with the PRCMU firmware.
275 *
276 * The reason for having this is to keep the irq numbers contiguous even though
277 * the bits in the bit field are not. (The bits also have a tendency to move
278 * around, to further complicate matters.)
279 */
280#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
281#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
282static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
283 IRQ_ENTRY(RTC),
284 IRQ_ENTRY(RTT0),
285 IRQ_ENTRY(RTT1),
286 IRQ_ENTRY(HSI0),
287 IRQ_ENTRY(HSI1),
288 IRQ_ENTRY(CA_WAKE),
289 IRQ_ENTRY(USB),
290 IRQ_ENTRY(ABB),
291 IRQ_ENTRY(ABB_FIFO),
292 IRQ_ENTRY(CA_SLEEP),
293 IRQ_ENTRY(ARM),
294 IRQ_ENTRY(HOTMON_LOW),
295 IRQ_ENTRY(HOTMON_HIGH),
296 IRQ_ENTRY(MODEM_SW_RESET_REQ),
297 IRQ_ENTRY(GPIO0),
298 IRQ_ENTRY(GPIO1),
299 IRQ_ENTRY(GPIO2),
300 IRQ_ENTRY(GPIO3),
301 IRQ_ENTRY(GPIO4),
302 IRQ_ENTRY(GPIO5),
303 IRQ_ENTRY(GPIO6),
304 IRQ_ENTRY(GPIO7),
305 IRQ_ENTRY(GPIO8)
Martin Perssone0befb22010-12-08 15:13:28 +0100306};
307
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200308#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
309#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
310static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
311 WAKEUP_ENTRY(RTC),
312 WAKEUP_ENTRY(RTT0),
313 WAKEUP_ENTRY(RTT1),
314 WAKEUP_ENTRY(HSI0),
315 WAKEUP_ENTRY(HSI1),
316 WAKEUP_ENTRY(USB),
317 WAKEUP_ENTRY(ABB),
318 WAKEUP_ENTRY(ABB_FIFO),
319 WAKEUP_ENTRY(ARM)
320};
321
322/*
323 * mb0_transfer - state needed for mailbox 0 communication.
324 * @lock: The transaction lock.
325 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
326 * the request data.
327 * @mask_work: Work structure used for (un)masking wakeup interrupts.
328 * @req: Request data that need to persist between requests.
329 */
330static struct {
331 spinlock_t lock;
332 spinlock_t dbb_irqs_lock;
333 struct work_struct mask_work;
334 struct mutex ac_wake_lock;
335 struct completion ac_wake_work;
336 struct {
337 u32 dbb_irqs;
338 u32 dbb_wakeups;
339 u32 abb_events;
340 } req;
341} mb0_transfer;
342
343/*
344 * mb1_transfer - state needed for mailbox 1 communication.
345 * @lock: The transaction lock.
346 * @work: The transaction completion structure.
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100347 * @ape_opp: The current APE OPP.
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200348 * @ack: Reply ("acknowledge") data.
349 */
Martin Perssone0befb22010-12-08 15:13:28 +0100350static struct {
351 struct mutex lock;
352 struct completion work;
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100353 u8 ape_opp;
Martin Perssone0befb22010-12-08 15:13:28 +0100354 struct {
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200355 u8 header;
Martin Perssone0befb22010-12-08 15:13:28 +0100356 u8 arm_opp;
357 u8 ape_opp;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200358 u8 ape_voltage_status;
Martin Perssone0befb22010-12-08 15:13:28 +0100359 } ack;
360} mb1_transfer;
361
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200362/*
363 * mb2_transfer - state needed for mailbox 2 communication.
364 * @lock: The transaction lock.
365 * @work: The transaction completion structure.
366 * @auto_pm_lock: The autonomous power management configuration lock.
367 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
368 * @req: Request data that need to persist between requests.
369 * @ack: Reply ("acknowledge") data.
370 */
Linus Walleije3726fc2010-08-19 12:36:01 +0100371static struct {
372 struct mutex lock;
373 struct completion work;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200374 spinlock_t auto_pm_lock;
375 bool auto_pm_enabled;
376 struct {
377 u8 status;
378 } ack;
379} mb2_transfer;
380
381/*
382 * mb3_transfer - state needed for mailbox 3 communication.
383 * @lock: The request lock.
384 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
385 * @sysclk_work: Work structure used for sysclk requests.
386 */
387static struct {
388 spinlock_t lock;
389 struct mutex sysclk_lock;
390 struct completion sysclk_work;
391} mb3_transfer;
392
393/*
394 * mb4_transfer - state needed for mailbox 4 communication.
395 * @lock: The transaction lock.
396 * @work: The transaction completion structure.
397 */
398static struct {
399 struct mutex lock;
400 struct completion work;
401} mb4_transfer;
402
403/*
404 * mb5_transfer - state needed for mailbox 5 communication.
405 * @lock: The transaction lock.
406 * @work: The transaction completion structure.
407 * @ack: Reply ("acknowledge") data.
408 */
409static struct {
410 struct mutex lock;
411 struct completion work;
Linus Walleije3726fc2010-08-19 12:36:01 +0100412 struct {
413 u8 status;
414 u8 value;
415 } ack;
416} mb5_transfer;
417
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200418static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
419
420/* Spinlocks */
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100421static DEFINE_SPINLOCK(prcmu_lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200422static DEFINE_SPINLOCK(clkout_lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200423
424/* Global var to runtime determine TCDM base for v2 or v1 */
425static __iomem void *tcdm_base;
426
427struct clk_mgt {
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100428 void __iomem *reg;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200429 u32 pllsw;
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100430 int branch;
431 bool clk38div;
432};
433
434enum {
435 PLL_RAW,
436 PLL_FIX,
437 PLL_DIV
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200438};
439
440static DEFINE_SPINLOCK(clk_mgt_lock);
441
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100442#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
443 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200444struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100445 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
446 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
447 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
448 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
449 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
450 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
451 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
452 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
453 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
454 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
455 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
456 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
457 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
458 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
459 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
460 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
461 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
462 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
463 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
464 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
465 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
466 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
467 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
468 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
469 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
470 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
471 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
472 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
474};
475
476struct dsiclk {
477 u32 divsel_mask;
478 u32 divsel_shift;
479 u32 divsel;
480};
481
482static struct dsiclk dsiclk[2] = {
483 {
484 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
485 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
486 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
487 },
488 {
489 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
490 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
491 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
492 }
493};
494
495struct dsiescclk {
496 u32 en;
497 u32 div_mask;
498 u32 div_shift;
499};
500
501static struct dsiescclk dsiescclk[3] = {
502 {
503 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
504 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
505 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
506 },
507 {
508 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
509 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
510 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
511 },
512 {
513 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
514 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
515 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
516 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200517};
518
Mattias Nilsson0837bb72011-08-12 10:28:18 +0200519static struct regulator *hwacc_regulator[NUM_HW_ACC];
520static struct regulator *hwacc_ret_regulator[NUM_HW_ACC];
521
522static bool hwacc_enabled[NUM_HW_ACC];
523static bool hwacc_ret_enabled[NUM_HW_ACC];
524
525static const char *hwacc_regulator_name[NUM_HW_ACC] = {
526 [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp",
527 [HW_ACC_SVAPIPE] = "hwacc-sva-pipe",
528 [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp",
529 [HW_ACC_SIAPIPE] = "hwacc-sia-pipe",
530 [HW_ACC_SGA] = "hwacc-sga",
531 [HW_ACC_B2R2] = "hwacc-b2r2",
532 [HW_ACC_MCDE] = "hwacc-mcde",
533 [HW_ACC_ESRAM1] = "hwacc-esram1",
534 [HW_ACC_ESRAM2] = "hwacc-esram2",
535 [HW_ACC_ESRAM3] = "hwacc-esram3",
536 [HW_ACC_ESRAM4] = "hwacc-esram4",
537};
538
539static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = {
540 [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret",
541 [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret",
542 [HW_ACC_ESRAM1] = "hwacc-esram1-ret",
543 [HW_ACC_ESRAM2] = "hwacc-esram2-ret",
544 [HW_ACC_ESRAM3] = "hwacc-esram3-ret",
545 [HW_ACC_ESRAM4] = "hwacc-esram4-ret",
546};
547
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200548/*
549* Used by MCDE to setup all necessary PRCMU registers
550*/
551#define PRCMU_RESET_DSIPLL 0x00004000
552#define PRCMU_UNCLAMP_DSIPLL 0x00400800
553
554#define PRCMU_CLK_PLL_DIV_SHIFT 0
555#define PRCMU_CLK_PLL_SW_SHIFT 5
556#define PRCMU_CLK_38 (1 << 9)
557#define PRCMU_CLK_38_SRC (1 << 10)
558#define PRCMU_CLK_38_DIV (1 << 11)
559
560/* PLLDIV=12, PLLSW=4 (PLLDDR) */
561#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
562
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200563/* DPI 50000000 Hz */
564#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
565 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
566#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
567
568/* D=101, N=1, R=4, SELDIV2=0 */
569#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
570
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200571#define PRCMU_ENABLE_PLLDSI 0x00000001
572#define PRCMU_DISABLE_PLLDSI 0x00000000
573#define PRCMU_RELEASE_RESET_DSS 0x0000400C
574#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
575/* ESC clk, div0=1, div1=1, div2=3 */
576#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
577#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
578#define PRCMU_DSI_RESET_SW 0x00000007
579
580#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
581
Mattias Nilsson73180f82011-08-12 10:28:10 +0200582int db8500_prcmu_enable_dsipll(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200583{
584 int i;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200585
586 /* Clear DSIPLL_RESETN */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200587 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200588 /* Unclamp DSIPLL in/out */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200589 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200590
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200591 /* Set DSI PLL FREQ */
Daniel Willerudc72fe852012-01-13 16:20:03 +0100592 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200593 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200594 /* Enable Escape clocks */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200595 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200596
597 /* Start DSI PLL */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200598 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200599 /* Reset DSI PLL */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200600 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200601 for (i = 0; i < 10; i++) {
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200602 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200603 == PRCMU_PLLDSI_LOCKP_LOCKED)
604 break;
605 udelay(100);
606 }
607 /* Set DSIPLL_RESETN */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200608 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200609 return 0;
610}
611
Mattias Nilsson73180f82011-08-12 10:28:10 +0200612int db8500_prcmu_disable_dsipll(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200613{
614 /* Disable dsi pll */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200615 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200616 /* Disable escapeclock */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200617 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200618 return 0;
619}
620
Mattias Nilsson73180f82011-08-12 10:28:10 +0200621int db8500_prcmu_set_display_clocks(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200622{
623 unsigned long flags;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200624
625 spin_lock_irqsave(&clk_mgt_lock, flags);
626
627 /* Grab the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200628 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200629 cpu_relax();
630
Daniel Willerudc72fe852012-01-13 16:20:03 +0100631 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200632 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
633 writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200634
635 /* Release the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200636 writel(0, PRCM_SEM);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200637
638 spin_unlock_irqrestore(&clk_mgt_lock, flags);
639
640 return 0;
641}
642
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100643u32 db8500_prcmu_read(unsigned int reg)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200644{
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100645 return readl(_PRCMU_BASE + reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200646}
647
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100648void db8500_prcmu_write(unsigned int reg, u32 value)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200649{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200650 unsigned long flags;
651
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100652 spin_lock_irqsave(&prcmu_lock, flags);
653 writel(value, (_PRCMU_BASE + reg));
654 spin_unlock_irqrestore(&prcmu_lock, flags);
655}
656
657void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
658{
659 u32 val;
660 unsigned long flags;
661
662 spin_lock_irqsave(&prcmu_lock, flags);
663 val = readl(_PRCMU_BASE + reg);
664 val = ((val & ~mask) | (value & mask));
665 writel(val, (_PRCMU_BASE + reg));
666 spin_unlock_irqrestore(&prcmu_lock, flags);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200667}
668
Mattias Nilssonb58d12f2012-01-13 16:20:10 +0100669struct prcmu_fw_version *prcmu_get_fw_version(void)
670{
671 return fw_info.valid ? &fw_info.version : NULL;
672}
673
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200674bool prcmu_has_arm_maxopp(void)
675{
676 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
677 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
678}
679
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200680/**
681 * prcmu_get_boot_status - PRCMU boot status checking
682 * Returns: the current PRCMU boot status
683 */
684int prcmu_get_boot_status(void)
685{
686 return readb(tcdm_base + PRCM_BOOT_STATUS);
687}
688
689/**
690 * prcmu_set_rc_a2p - This function is used to run few power state sequences
691 * @val: Value to be set, i.e. transition requested
692 * Returns: 0 on success, -EINVAL on invalid argument
693 *
694 * This function is used to run the following power state sequences -
695 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
696 */
697int prcmu_set_rc_a2p(enum romcode_write val)
698{
699 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
700 return -EINVAL;
701 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
702 return 0;
703}
704
705/**
706 * prcmu_get_rc_p2a - This function is used to get power state sequences
707 * Returns: the power transition that has last happened
708 *
709 * This function can return the following transitions-
710 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
711 */
712enum romcode_read prcmu_get_rc_p2a(void)
713{
714 return readb(tcdm_base + PRCM_ROMCODE_P2A);
715}
716
717/**
718 * prcmu_get_current_mode - Return the current XP70 power mode
719 * Returns: Returns the current AP(ARM) power mode: init,
720 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
721 */
722enum ap_pwrst prcmu_get_xp70_current_state(void)
723{
724 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
725}
726
727/**
728 * prcmu_config_clkout - Configure one of the programmable clock outputs.
729 * @clkout: The CLKOUT number (0 or 1).
730 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
731 * @div: The divider to be applied.
732 *
733 * Configures one of the programmable clock outputs (CLKOUTs).
734 * @div should be in the range [1,63] to request a configuration, or 0 to
735 * inform that the configuration is no longer requested.
736 */
737int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
738{
739 static int requests[2];
740 int r = 0;
741 unsigned long flags;
742 u32 val;
743 u32 bits;
744 u32 mask;
745 u32 div_mask;
746
747 BUG_ON(clkout > 1);
748 BUG_ON(div > 63);
749 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
750
751 if (!div && !requests[clkout])
752 return -EINVAL;
753
754 switch (clkout) {
755 case 0:
756 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
757 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
758 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
759 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
760 break;
761 case 1:
762 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
763 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
764 PRCM_CLKOCR_CLK1TYPE);
765 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
766 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
767 break;
768 }
769 bits &= mask;
770
771 spin_lock_irqsave(&clkout_lock, flags);
772
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200773 val = readl(PRCM_CLKOCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200774 if (val & div_mask) {
775 if (div) {
776 if ((val & mask) != bits) {
777 r = -EBUSY;
778 goto unlock_and_return;
779 }
780 } else {
781 if ((val & mask & ~div_mask) != bits) {
782 r = -EINVAL;
783 goto unlock_and_return;
784 }
785 }
786 }
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200787 writel((bits | (val & ~mask)), PRCM_CLKOCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200788 requests[clkout] += (div ? 1 : -1);
789
790unlock_and_return:
791 spin_unlock_irqrestore(&clkout_lock, flags);
792
793 return r;
794}
795
Mattias Nilsson73180f82011-08-12 10:28:10 +0200796int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200797{
798 unsigned long flags;
799
800 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
801
802 spin_lock_irqsave(&mb0_transfer.lock, flags);
803
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200804 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200805 cpu_relax();
806
807 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
808 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
809 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
810 writeb((keep_ulp_clk ? 1 : 0),
811 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
812 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200813 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200814
815 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
816
817 return 0;
818}
819
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100820u8 db8500_prcmu_get_power_state_result(void)
821{
822 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
823}
824
Daniel Lezcano485540d2012-02-20 12:30:26 +0100825/* This function decouple the gic from the prcmu */
826int db8500_prcmu_gic_decouple(void)
827{
Daniel Lezcano801448e2012-02-28 22:46:05 +0100828 u32 val = readl(PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100829
830 /* Set bit 0 register value to 1 */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100831 writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
832 PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100833
834 /* Make sure the register is updated */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100835 readl(PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100836
837 /* Wait a few cycles for the gic mask completion */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100838 udelay(1);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100839
840 return 0;
841}
842
843/* This function recouple the gic with the prcmu */
844int db8500_prcmu_gic_recouple(void)
845{
Daniel Lezcano801448e2012-02-28 22:46:05 +0100846 u32 val = readl(PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100847
848 /* Set bit 0 register value to 0 */
Daniel Lezcano801448e2012-02-28 22:46:05 +0100849 writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
Daniel Lezcano485540d2012-02-20 12:30:26 +0100850
851 return 0;
852}
853
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +0100854#define PRCMU_GIC_NUMBER_REGS 5
855
856/*
857 * This function checks if there are pending irq on the gic. It only
858 * makes sense if the gic has been decoupled before with the
859 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
860 * disables the forwarding of the interrupt to any CPU interface. It
861 * does not prevent the interrupt from changing state, for example
862 * becoming pending, or active and pending if it is already
863 * active. Hence, we have to check the interrupt is pending *and* is
864 * active.
865 */
866bool db8500_prcmu_gic_pending_irq(void)
867{
868 u32 pr; /* Pending register */
869 u32 er; /* Enable register */
870 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
871 int i;
872
873 /* 5 registers. STI & PPI not skipped */
874 for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
875
876 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
877 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
878
879 if (pr & er)
880 return true; /* There is a pending interrupt */
881 }
882
883 return false;
884}
885
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100886/*
887 * This function copies the gic SPI settings to the prcmu in order to
888 * monitor them and abort/finish the retention/off sequence or state.
889 */
890int db8500_prcmu_copy_gic_settings(void)
891{
892 u32 er; /* Enable register */
893 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
894 int i;
895
896 /* We skip the STI and PPI */
897 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
898 er = readl_relaxed(dist_base +
899 GIC_DIST_ENABLE_SET + (i + 1) * 4);
900 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
901 }
902
903 return 0;
904}
905
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200906/* This function should only be called while mb0_transfer.lock is held. */
907static void config_wakeups(void)
908{
909 const u8 header[2] = {
910 MB0H_CONFIG_WAKEUPS_EXE,
911 MB0H_CONFIG_WAKEUPS_SLEEP
912 };
913 static u32 last_dbb_events;
914 static u32 last_abb_events;
915 u32 dbb_events;
916 u32 abb_events;
917 unsigned int i;
918
919 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
920 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
921
922 abb_events = mb0_transfer.req.abb_events;
923
924 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
925 return;
926
927 for (i = 0; i < 2; i++) {
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200928 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200929 cpu_relax();
930 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
931 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
932 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200933 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200934 }
935 last_dbb_events = dbb_events;
936 last_abb_events = abb_events;
937}
938
Mattias Nilsson73180f82011-08-12 10:28:10 +0200939void db8500_prcmu_enable_wakeups(u32 wakeups)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200940{
941 unsigned long flags;
942 u32 bits;
943 int i;
944
945 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
946
947 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
948 if (wakeups & BIT(i))
949 bits |= prcmu_wakeup_bit[i];
950 }
951
952 spin_lock_irqsave(&mb0_transfer.lock, flags);
953
954 mb0_transfer.req.dbb_wakeups = bits;
955 config_wakeups();
956
957 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
958}
959
Mattias Nilsson73180f82011-08-12 10:28:10 +0200960void db8500_prcmu_config_abb_event_readout(u32 abb_events)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200961{
962 unsigned long flags;
963
964 spin_lock_irqsave(&mb0_transfer.lock, flags);
965
966 mb0_transfer.req.abb_events = abb_events;
967 config_wakeups();
968
969 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
970}
971
Mattias Nilsson73180f82011-08-12 10:28:10 +0200972void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200973{
974 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
975 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
976 else
977 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
978}
979
980/**
Mattias Nilsson73180f82011-08-12 10:28:10 +0200981 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200982 * @opp: The new ARM operating point to which transition is to be made
983 * Returns: 0 on success, non-zero on failure
984 *
985 * This function sets the the operating point of the ARM.
986 */
Mattias Nilsson73180f82011-08-12 10:28:10 +0200987int db8500_prcmu_set_arm_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200988{
989 int r;
990
991 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
992 return -EINVAL;
993
994 r = 0;
995
996 mutex_lock(&mb1_transfer.lock);
997
Mattias Nilssonc553b3c2011-08-12 10:27:20 +0200998 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +0200999 cpu_relax();
1000
1001 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1002 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1003 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1004
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001005 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001006 wait_for_completion(&mb1_transfer.work);
1007
1008 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1009 (mb1_transfer.ack.arm_opp != opp))
1010 r = -EIO;
1011
1012 mutex_unlock(&mb1_transfer.lock);
1013
1014 return r;
1015}
1016
1017/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001018 * db8500_prcmu_get_arm_opp - get the current ARM OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001019 *
1020 * Returns: the current ARM OPP
1021 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001022int db8500_prcmu_get_arm_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001023{
1024 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1025}
1026
1027/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001028 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001029 *
1030 * Returns: the current DDR OPP
1031 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001032int db8500_prcmu_get_ddr_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001033{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001034 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001035}
1036
1037/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001038 * db8500_set_ddr_opp - set the appropriate DDR OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001039 * @opp: The new DDR operating point to which transition is to be made
1040 * Returns: 0 on success, non-zero on failure
1041 *
1042 * This function sets the operating point of the DDR.
1043 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001044int db8500_prcmu_set_ddr_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001045{
1046 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1047 return -EINVAL;
1048 /* Changing the DDR OPP can hang the hardware pre-v21 */
1049 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001050 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001051
1052 return 0;
1053}
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001054
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001055/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1056static void request_even_slower_clocks(bool enable)
1057{
1058 void __iomem *clock_reg[] = {
1059 PRCM_ACLK_MGT,
1060 PRCM_DMACLK_MGT
1061 };
1062 unsigned long flags;
1063 unsigned int i;
1064
1065 spin_lock_irqsave(&clk_mgt_lock, flags);
1066
1067 /* Grab the HW semaphore. */
1068 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1069 cpu_relax();
1070
1071 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1072 u32 val;
1073 u32 div;
1074
1075 val = readl(clock_reg[i]);
1076 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1077 if (enable) {
1078 if ((div <= 1) || (div > 15)) {
1079 pr_err("prcmu: Bad clock divider %d in %s\n",
1080 div, __func__);
1081 goto unlock_and_return;
1082 }
1083 div <<= 1;
1084 } else {
1085 if (div <= 2)
1086 goto unlock_and_return;
1087 div >>= 1;
1088 }
1089 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1090 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1091 writel(val, clock_reg[i]);
1092 }
1093
1094unlock_and_return:
1095 /* Release the HW semaphore. */
1096 writel(0, PRCM_SEM);
1097
1098 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1099}
1100
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001101/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001102 * db8500_set_ape_opp - set the appropriate APE OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001103 * @opp: The new APE operating point to which transition is to be made
1104 * Returns: 0 on success, non-zero on failure
1105 *
1106 * This function sets the operating point of the APE.
1107 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001108int db8500_prcmu_set_ape_opp(u8 opp)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001109{
1110 int r = 0;
1111
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001112 if (opp == mb1_transfer.ape_opp)
1113 return 0;
1114
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001115 mutex_lock(&mb1_transfer.lock);
1116
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001117 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1118 request_even_slower_clocks(false);
1119
1120 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1121 goto skip_message;
1122
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001123 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001124 cpu_relax();
1125
1126 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1127 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001128 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1129 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001130
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001131 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001132 wait_for_completion(&mb1_transfer.work);
1133
1134 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1135 (mb1_transfer.ack.ape_opp != opp))
1136 r = -EIO;
1137
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01001138skip_message:
1139 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1140 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1141 request_even_slower_clocks(true);
1142 if (!r)
1143 mb1_transfer.ape_opp = opp;
1144
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001145 mutex_unlock(&mb1_transfer.lock);
1146
1147 return r;
1148}
1149
1150/**
Mattias Nilsson05089012012-01-13 16:20:20 +01001151 * db8500_prcmu_get_ape_opp - get the current APE OPP
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001152 *
1153 * Returns: the current APE OPP
1154 */
Mattias Nilsson05089012012-01-13 16:20:20 +01001155int db8500_prcmu_get_ape_opp(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001156{
1157 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1158}
1159
1160/**
1161 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1162 * @enable: true to request the higher voltage, false to drop a request.
1163 *
1164 * Calls to this function to enable and disable requests must be balanced.
1165 */
1166int prcmu_request_ape_opp_100_voltage(bool enable)
1167{
1168 int r = 0;
1169 u8 header;
1170 static unsigned int requests;
1171
1172 mutex_lock(&mb1_transfer.lock);
1173
1174 if (enable) {
1175 if (0 != requests++)
1176 goto unlock_and_return;
1177 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1178 } else {
1179 if (requests == 0) {
1180 r = -EIO;
1181 goto unlock_and_return;
1182 } else if (1 != requests--) {
1183 goto unlock_and_return;
1184 }
1185 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1186 }
1187
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001188 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001189 cpu_relax();
1190
1191 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1192
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001193 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001194 wait_for_completion(&mb1_transfer.work);
1195
1196 if ((mb1_transfer.ack.header != header) ||
1197 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1198 r = -EIO;
1199
1200unlock_and_return:
1201 mutex_unlock(&mb1_transfer.lock);
1202
1203 return r;
1204}
1205
1206/**
1207 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1208 *
1209 * This function releases the power state requirements of a USB wakeup.
1210 */
1211int prcmu_release_usb_wakeup_state(void)
1212{
1213 int r = 0;
1214
1215 mutex_lock(&mb1_transfer.lock);
1216
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001217 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001218 cpu_relax();
1219
1220 writeb(MB1H_RELEASE_USB_WAKEUP,
1221 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1222
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001223 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001224 wait_for_completion(&mb1_transfer.work);
1225
1226 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1227 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1228 r = -EIO;
1229
1230 mutex_unlock(&mb1_transfer.lock);
1231
1232 return r;
1233}
1234
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001235static int request_pll(u8 clock, bool enable)
1236{
1237 int r = 0;
1238
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001239 if (clock == PRCMU_PLLSOC0)
1240 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1241 else if (clock == PRCMU_PLLSOC1)
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001242 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1243 else
1244 return -EINVAL;
1245
1246 mutex_lock(&mb1_transfer.lock);
1247
1248 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1249 cpu_relax();
1250
1251 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1252 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1253
1254 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1255 wait_for_completion(&mb1_transfer.work);
1256
1257 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1258 r = -EIO;
1259
1260 mutex_unlock(&mb1_transfer.lock);
1261
1262 return r;
1263}
1264
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001265/**
Bengt Jonsson0b9199e2011-08-12 10:28:25 +02001266 * prcmu_set_hwacc - set the power state of a h/w accelerator
1267 * @hwacc_dev: The hardware accelerator (enum hw_acc_dev).
1268 * @state: The new power state (enum hw_acc_state).
1269 *
1270 * This function sets the power state of a hardware accelerator.
1271 * This function should not be called from interrupt context.
1272 *
1273 * NOTE! Deprecated, to be removed when all users switched over to use the
1274 * regulator framework API.
1275 */
1276int prcmu_set_hwacc(u16 hwacc_dev, u8 state)
1277{
1278 int r = 0;
1279 bool ram_retention = false;
1280 bool enable, enable_ret;
1281
1282 /* check argument */
1283 BUG_ON(hwacc_dev >= NUM_HW_ACC);
1284
1285 /* get state of switches */
1286 enable = hwacc_enabled[hwacc_dev];
1287 enable_ret = hwacc_ret_enabled[hwacc_dev];
1288
1289 /* set flag if retention is possible */
1290 switch (hwacc_dev) {
1291 case HW_ACC_SVAMMDSP:
1292 case HW_ACC_SIAMMDSP:
1293 case HW_ACC_ESRAM1:
1294 case HW_ACC_ESRAM2:
1295 case HW_ACC_ESRAM3:
1296 case HW_ACC_ESRAM4:
1297 ram_retention = true;
1298 break;
1299 }
1300
1301 /* check argument */
1302 BUG_ON(state > HW_ON);
1303 BUG_ON(state == HW_OFF_RAMRET && !ram_retention);
1304
1305 /* modify enable flags */
1306 switch (state) {
1307 case HW_OFF:
1308 enable_ret = false;
1309 enable = false;
1310 break;
1311 case HW_ON:
1312 enable = true;
1313 break;
1314 case HW_OFF_RAMRET:
1315 enable_ret = true;
1316 enable = false;
1317 break;
1318 }
1319
1320 /* get regulator (lazy) */
1321 if (hwacc_regulator[hwacc_dev] == NULL) {
1322 hwacc_regulator[hwacc_dev] = regulator_get(NULL,
1323 hwacc_regulator_name[hwacc_dev]);
1324 if (IS_ERR(hwacc_regulator[hwacc_dev])) {
1325 pr_err("prcmu: failed to get supply %s\n",
1326 hwacc_regulator_name[hwacc_dev]);
1327 r = PTR_ERR(hwacc_regulator[hwacc_dev]);
1328 goto out;
1329 }
1330 }
1331
1332 if (ram_retention) {
1333 if (hwacc_ret_regulator[hwacc_dev] == NULL) {
1334 hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL,
1335 hwacc_ret_regulator_name[hwacc_dev]);
1336 if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) {
1337 pr_err("prcmu: failed to get supply %s\n",
1338 hwacc_ret_regulator_name[hwacc_dev]);
1339 r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]);
1340 goto out;
1341 }
1342 }
1343 }
1344
1345 /* set regulators */
1346 if (ram_retention) {
1347 if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) {
1348 r = regulator_enable(hwacc_ret_regulator[hwacc_dev]);
1349 if (r < 0) {
1350 pr_err("prcmu_set_hwacc: ret enable failed\n");
1351 goto out;
1352 }
1353 hwacc_ret_enabled[hwacc_dev] = true;
1354 }
1355 }
1356
1357 if (enable && !hwacc_enabled[hwacc_dev]) {
1358 r = regulator_enable(hwacc_regulator[hwacc_dev]);
1359 if (r < 0) {
1360 pr_err("prcmu_set_hwacc: enable failed\n");
1361 goto out;
1362 }
1363 hwacc_enabled[hwacc_dev] = true;
1364 }
1365
1366 if (!enable && hwacc_enabled[hwacc_dev]) {
1367 r = regulator_disable(hwacc_regulator[hwacc_dev]);
1368 if (r < 0) {
1369 pr_err("prcmu_set_hwacc: disable failed\n");
1370 goto out;
1371 }
1372 hwacc_enabled[hwacc_dev] = false;
1373 }
1374
1375 if (ram_retention) {
1376 if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) {
1377 r = regulator_disable(hwacc_ret_regulator[hwacc_dev]);
1378 if (r < 0) {
1379 pr_err("prcmu_set_hwacc: ret disable failed\n");
1380 goto out;
1381 }
1382 hwacc_ret_enabled[hwacc_dev] = false;
1383 }
1384 }
1385
1386out:
1387 return r;
1388}
1389EXPORT_SYMBOL(prcmu_set_hwacc);
1390
1391/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001392 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001393 * @epod_id: The EPOD to set
1394 * @epod_state: The new EPOD state
1395 *
1396 * This function sets the state of a EPOD (power domain). It may not be called
1397 * from interrupt context.
1398 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001399int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001400{
1401 int r = 0;
1402 bool ram_retention = false;
1403 int i;
1404
1405 /* check argument */
1406 BUG_ON(epod_id >= NUM_EPOD_ID);
1407
1408 /* set flag if retention is possible */
1409 switch (epod_id) {
1410 case EPOD_ID_SVAMMDSP:
1411 case EPOD_ID_SIAMMDSP:
1412 case EPOD_ID_ESRAM12:
1413 case EPOD_ID_ESRAM34:
1414 ram_retention = true;
1415 break;
1416 }
1417
1418 /* check argument */
1419 BUG_ON(epod_state > EPOD_STATE_ON);
1420 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1421
1422 /* get lock */
1423 mutex_lock(&mb2_transfer.lock);
1424
1425 /* wait for mailbox */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001426 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001427 cpu_relax();
1428
1429 /* fill in mailbox */
1430 for (i = 0; i < NUM_EPOD_ID; i++)
1431 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1432 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1433
1434 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1435
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001436 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001437
1438 /*
1439 * The current firmware version does not handle errors correctly,
1440 * and we cannot recover if there is an error.
1441 * This is expected to change when the firmware is updated.
1442 */
1443 if (!wait_for_completion_timeout(&mb2_transfer.work,
1444 msecs_to_jiffies(20000))) {
1445 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1446 __func__);
1447 r = -EIO;
1448 goto unlock_and_return;
1449 }
1450
1451 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1452 r = -EIO;
1453
1454unlock_and_return:
1455 mutex_unlock(&mb2_transfer.lock);
1456 return r;
1457}
1458
1459/**
1460 * prcmu_configure_auto_pm - Configure autonomous power management.
1461 * @sleep: Configuration for ApSleep.
1462 * @idle: Configuration for ApIdle.
1463 */
1464void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1465 struct prcmu_auto_pm_config *idle)
1466{
1467 u32 sleep_cfg;
1468 u32 idle_cfg;
1469 unsigned long flags;
1470
1471 BUG_ON((sleep == NULL) || (idle == NULL));
1472
1473 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1474 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1475 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1476 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1477 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1478 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1479
1480 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1481 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1482 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1483 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1484 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1485 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1486
1487 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1488
1489 /*
1490 * The autonomous power management configuration is done through
1491 * fields in mailbox 2, but these fields are only used as shared
1492 * variables - i.e. there is no need to send a message.
1493 */
1494 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1495 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1496
1497 mb2_transfer.auto_pm_enabled =
1498 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1499 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1500 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1501 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1502
1503 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1504}
1505EXPORT_SYMBOL(prcmu_configure_auto_pm);
1506
1507bool prcmu_is_auto_pm_enabled(void)
1508{
1509 return mb2_transfer.auto_pm_enabled;
1510}
1511
1512static int request_sysclk(bool enable)
1513{
1514 int r;
1515 unsigned long flags;
1516
1517 r = 0;
1518
1519 mutex_lock(&mb3_transfer.sysclk_lock);
1520
1521 spin_lock_irqsave(&mb3_transfer.lock, flags);
1522
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001523 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001524 cpu_relax();
1525
1526 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1527
1528 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001529 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001530
1531 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1532
1533 /*
1534 * The firmware only sends an ACK if we want to enable the
1535 * SysClk, and it succeeds.
1536 */
1537 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1538 msecs_to_jiffies(20000))) {
1539 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1540 __func__);
1541 r = -EIO;
1542 }
1543
1544 mutex_unlock(&mb3_transfer.sysclk_lock);
1545
1546 return r;
1547}
1548
1549static int request_timclk(bool enable)
1550{
1551 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1552
1553 if (!enable)
1554 val |= PRCM_TCR_STOP_TIMERS;
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001555 writel(val, PRCM_TCR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001556
1557 return 0;
1558}
1559
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001560static int request_clock(u8 clock, bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001561{
1562 u32 val;
1563 unsigned long flags;
1564
1565 spin_lock_irqsave(&clk_mgt_lock, flags);
1566
1567 /* Grab the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001568 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001569 cpu_relax();
1570
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001571 val = readl(clk_mgt[clock].reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001572 if (enable) {
1573 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1574 } else {
1575 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1576 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1577 }
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001578 writel(val, clk_mgt[clock].reg);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001579
1580 /* Release the HW semaphore. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02001581 writel(0, PRCM_SEM);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001582
1583 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1584
1585 return 0;
1586}
1587
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001588static int request_sga_clock(u8 clock, bool enable)
1589{
1590 u32 val;
1591 int ret;
1592
1593 if (enable) {
1594 val = readl(PRCM_CGATING_BYPASS);
1595 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1596 }
1597
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001598 ret = request_clock(clock, enable);
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001599
1600 if (!ret && !enable) {
1601 val = readl(PRCM_CGATING_BYPASS);
1602 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1603 }
1604
1605 return ret;
1606}
1607
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001608static inline bool plldsi_locked(void)
1609{
1610 return (readl(PRCM_PLLDSI_LOCKP) &
1611 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1612 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1613 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1614 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1615}
1616
1617static int request_plldsi(bool enable)
1618{
1619 int r = 0;
1620 u32 val;
1621
1622 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1623 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1624 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1625
1626 val = readl(PRCM_PLLDSI_ENABLE);
1627 if (enable)
1628 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1629 else
1630 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1631 writel(val, PRCM_PLLDSI_ENABLE);
1632
1633 if (enable) {
1634 unsigned int i;
1635 bool locked = plldsi_locked();
1636
1637 for (i = 10; !locked && (i > 0); --i) {
1638 udelay(100);
1639 locked = plldsi_locked();
1640 }
1641 if (locked) {
1642 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1643 PRCM_APE_RESETN_SET);
1644 } else {
1645 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1646 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1647 PRCM_MMIP_LS_CLAMP_SET);
1648 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1649 writel(val, PRCM_PLLDSI_ENABLE);
1650 r = -EAGAIN;
1651 }
1652 } else {
1653 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1654 }
1655 return r;
1656}
1657
1658static int request_dsiclk(u8 n, bool enable)
1659{
1660 u32 val;
1661
1662 val = readl(PRCM_DSI_PLLOUT_SEL);
1663 val &= ~dsiclk[n].divsel_mask;
1664 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1665 dsiclk[n].divsel_shift);
1666 writel(val, PRCM_DSI_PLLOUT_SEL);
1667 return 0;
1668}
1669
1670static int request_dsiescclk(u8 n, bool enable)
1671{
1672 u32 val;
1673
1674 val = readl(PRCM_DSITVCLK_DIV);
1675 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1676 writel(val, PRCM_DSITVCLK_DIV);
1677 return 0;
1678}
1679
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001680/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02001681 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001682 * @clock: The clock for which the request is made.
1683 * @enable: Whether the clock should be enabled (true) or disabled (false).
1684 *
1685 * This function should only be used by the clock implementation.
1686 * Do not use it from any other place!
1687 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02001688int db8500_prcmu_request_clock(u8 clock, bool enable)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001689{
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001690 if (clock == PRCMU_SGACLK)
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001691 return request_sga_clock(clock, enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001692 else if (clock < PRCMU_NUM_REG_CLOCKS)
1693 return request_clock(clock, enable);
1694 else if (clock == PRCMU_TIMCLK)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001695 return request_timclk(enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001696 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1697 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1698 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1699 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1700 else if (clock == PRCMU_PLLDSI)
1701 return request_plldsi(enable);
1702 else if (clock == PRCMU_SYSCLK)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02001703 return request_sysclk(enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001704 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
Mattias Nilsson0837bb72011-08-12 10:28:18 +02001705 return request_pll(clock, enable);
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001706 else
1707 return -EINVAL;
1708}
1709
1710static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1711 int branch)
1712{
1713 u64 rate;
1714 u32 val;
1715 u32 d;
1716 u32 div = 1;
1717
1718 val = readl(reg);
1719
1720 rate = src_rate;
1721 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1722
1723 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1724 if (d > 1)
1725 div *= d;
1726
1727 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1728 if (d > 1)
1729 div *= d;
1730
1731 if (val & PRCM_PLL_FREQ_SELDIV2)
1732 div *= 2;
1733
1734 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1735 (val & PRCM_PLL_FREQ_DIV2EN) &&
1736 ((reg == PRCM_PLLSOC0_FREQ) ||
1737 (reg == PRCM_PLLDDR_FREQ))))
1738 div *= 2;
1739
1740 (void)do_div(rate, div);
1741
1742 return (unsigned long)rate;
1743}
1744
1745#define ROOT_CLOCK_RATE 38400000
1746
1747static unsigned long clock_rate(u8 clock)
1748{
1749 u32 val;
1750 u32 pllsw;
1751 unsigned long rate = ROOT_CLOCK_RATE;
1752
1753 val = readl(clk_mgt[clock].reg);
1754
1755 if (val & PRCM_CLK_MGT_CLK38) {
1756 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1757 rate /= 2;
1758 return rate;
Linus Walleije62ccf32011-10-10 12:14:14 +02001759 }
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001760
1761 val |= clk_mgt[clock].pllsw;
1762 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1763
1764 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1765 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1766 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1767 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1768 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1769 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1770 else
1771 return 0;
1772
1773 if ((clock == PRCMU_SGACLK) &&
1774 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1775 u64 r = (rate * 10);
1776
1777 (void)do_div(r, 25);
1778 return (unsigned long)r;
1779 }
1780 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1781 if (val)
1782 return rate / val;
1783 else
1784 return 0;
1785}
1786
1787static unsigned long dsiclk_rate(u8 n)
1788{
1789 u32 divsel;
1790 u32 div = 1;
1791
1792 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1793 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1794
1795 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1796 divsel = dsiclk[n].divsel;
1797
1798 switch (divsel) {
1799 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1800 div *= 2;
1801 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1802 div *= 2;
1803 case PRCM_DSI_PLLOUT_SEL_PHI:
1804 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1805 PLL_RAW) / div;
1806 default:
1807 return 0;
1808 }
1809}
1810
1811static unsigned long dsiescclk_rate(u8 n)
1812{
1813 u32 div;
1814
1815 div = readl(PRCM_DSITVCLK_DIV);
1816 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1817 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1818}
1819
1820unsigned long prcmu_clock_rate(u8 clock)
1821{
Linus Walleije62ccf32011-10-10 12:14:14 +02001822 if (clock < PRCMU_NUM_REG_CLOCKS)
Mattias Nilsson6b6fae22012-01-13 16:20:28 +01001823 return clock_rate(clock);
1824 else if (clock == PRCMU_TIMCLK)
1825 return ROOT_CLOCK_RATE / 16;
1826 else if (clock == PRCMU_SYSCLK)
1827 return ROOT_CLOCK_RATE;
1828 else if (clock == PRCMU_PLLSOC0)
1829 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1830 else if (clock == PRCMU_PLLSOC1)
1831 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1832 else if (clock == PRCMU_PLLDDR)
1833 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1834 else if (clock == PRCMU_PLLDSI)
1835 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1836 PLL_RAW);
1837 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1838 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1839 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1840 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1841 else
1842 return 0;
1843}
1844
1845static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1846{
1847 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1848 return ROOT_CLOCK_RATE;
1849 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1850 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1851 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1852 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1853 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1854 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1855 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1856 else
1857 return 0;
1858}
1859
1860static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1861{
1862 u32 div;
1863
1864 div = (src_rate / rate);
1865 if (div == 0)
1866 return 1;
1867 if (rate < (src_rate / div))
1868 div++;
1869 return div;
1870}
1871
1872static long round_clock_rate(u8 clock, unsigned long rate)
1873{
1874 u32 val;
1875 u32 div;
1876 unsigned long src_rate;
1877 long rounded_rate;
1878
1879 val = readl(clk_mgt[clock].reg);
1880 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1881 clk_mgt[clock].branch);
1882 div = clock_divider(src_rate, rate);
1883 if (val & PRCM_CLK_MGT_CLK38) {
1884 if (clk_mgt[clock].clk38div) {
1885 if (div > 2)
1886 div = 2;
1887 } else {
1888 div = 1;
1889 }
1890 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1891 u64 r = (src_rate * 10);
1892
1893 (void)do_div(r, 25);
1894 if (r <= rate)
1895 return (unsigned long)r;
1896 }
1897 rounded_rate = (src_rate / min(div, (u32)31));
1898
1899 return rounded_rate;
1900}
1901
1902#define MIN_PLL_VCO_RATE 600000000ULL
1903#define MAX_PLL_VCO_RATE 1680640000ULL
1904
1905static long round_plldsi_rate(unsigned long rate)
1906{
1907 long rounded_rate = 0;
1908 unsigned long src_rate;
1909 unsigned long rem;
1910 u32 r;
1911
1912 src_rate = clock_rate(PRCMU_HDMICLK);
1913 rem = rate;
1914
1915 for (r = 7; (rem > 0) && (r > 0); r--) {
1916 u64 d;
1917
1918 d = (r * rate);
1919 (void)do_div(d, src_rate);
1920 if (d < 6)
1921 d = 6;
1922 else if (d > 255)
1923 d = 255;
1924 d *= src_rate;
1925 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1926 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1927 continue;
1928 (void)do_div(d, r);
1929 if (rate < d) {
1930 if (rounded_rate == 0)
1931 rounded_rate = (long)d;
1932 break;
1933 }
1934 if ((rate - d) < rem) {
1935 rem = (rate - d);
1936 rounded_rate = (long)d;
1937 }
1938 }
1939 return rounded_rate;
1940}
1941
1942static long round_dsiclk_rate(unsigned long rate)
1943{
1944 u32 div;
1945 unsigned long src_rate;
1946 long rounded_rate;
1947
1948 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1949 PLL_RAW);
1950 div = clock_divider(src_rate, rate);
1951 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1952
1953 return rounded_rate;
1954}
1955
1956static long round_dsiescclk_rate(unsigned long rate)
1957{
1958 u32 div;
1959 unsigned long src_rate;
1960 long rounded_rate;
1961
1962 src_rate = clock_rate(PRCMU_TVCLK);
1963 div = clock_divider(src_rate, rate);
1964 rounded_rate = (src_rate / min(div, (u32)255));
1965
1966 return rounded_rate;
1967}
1968
1969long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1970{
1971 if (clock < PRCMU_NUM_REG_CLOCKS)
1972 return round_clock_rate(clock, rate);
1973 else if (clock == PRCMU_PLLDSI)
1974 return round_plldsi_rate(rate);
1975 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1976 return round_dsiclk_rate(rate);
1977 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1978 return round_dsiescclk_rate(rate);
1979 else
1980 return (long)prcmu_clock_rate(clock);
1981}
1982
1983static void set_clock_rate(u8 clock, unsigned long rate)
1984{
1985 u32 val;
1986 u32 div;
1987 unsigned long src_rate;
1988 unsigned long flags;
1989
1990 spin_lock_irqsave(&clk_mgt_lock, flags);
1991
1992 /* Grab the HW semaphore. */
1993 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1994 cpu_relax();
1995
1996 val = readl(clk_mgt[clock].reg);
1997 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1998 clk_mgt[clock].branch);
1999 div = clock_divider(src_rate, rate);
2000 if (val & PRCM_CLK_MGT_CLK38) {
2001 if (clk_mgt[clock].clk38div) {
2002 if (div > 1)
2003 val |= PRCM_CLK_MGT_CLK38DIV;
2004 else
2005 val &= ~PRCM_CLK_MGT_CLK38DIV;
2006 }
2007 } else if (clock == PRCMU_SGACLK) {
2008 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
2009 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
2010 if (div == 3) {
2011 u64 r = (src_rate * 10);
2012
2013 (void)do_div(r, 25);
2014 if (r <= rate) {
2015 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
2016 div = 0;
2017 }
2018 }
2019 val |= min(div, (u32)31);
2020 } else {
2021 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
2022 val |= min(div, (u32)31);
2023 }
2024 writel(val, clk_mgt[clock].reg);
2025
2026 /* Release the HW semaphore. */
2027 writel(0, PRCM_SEM);
2028
2029 spin_unlock_irqrestore(&clk_mgt_lock, flags);
2030}
2031
2032static int set_plldsi_rate(unsigned long rate)
2033{
2034 unsigned long src_rate;
2035 unsigned long rem;
2036 u32 pll_freq = 0;
2037 u32 r;
2038
2039 src_rate = clock_rate(PRCMU_HDMICLK);
2040 rem = rate;
2041
2042 for (r = 7; (rem > 0) && (r > 0); r--) {
2043 u64 d;
2044 u64 hwrate;
2045
2046 d = (r * rate);
2047 (void)do_div(d, src_rate);
2048 if (d < 6)
2049 d = 6;
2050 else if (d > 255)
2051 d = 255;
2052 hwrate = (d * src_rate);
2053 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
2054 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
2055 continue;
2056 (void)do_div(hwrate, r);
2057 if (rate < hwrate) {
2058 if (pll_freq == 0)
2059 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2060 (r << PRCM_PLL_FREQ_R_SHIFT));
2061 break;
2062 }
2063 if ((rate - hwrate) < rem) {
2064 rem = (rate - hwrate);
2065 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2066 (r << PRCM_PLL_FREQ_R_SHIFT));
2067 }
2068 }
2069 if (pll_freq == 0)
2070 return -EINVAL;
2071
2072 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
2073 writel(pll_freq, PRCM_PLLDSI_FREQ);
2074
2075 return 0;
2076}
2077
2078static void set_dsiclk_rate(u8 n, unsigned long rate)
2079{
2080 u32 val;
2081 u32 div;
2082
2083 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
2084 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
2085
2086 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
2087 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
2088 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
2089
2090 val = readl(PRCM_DSI_PLLOUT_SEL);
2091 val &= ~dsiclk[n].divsel_mask;
2092 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
2093 writel(val, PRCM_DSI_PLLOUT_SEL);
2094}
2095
2096static void set_dsiescclk_rate(u8 n, unsigned long rate)
2097{
2098 u32 val;
2099 u32 div;
2100
2101 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
2102 val = readl(PRCM_DSITVCLK_DIV);
2103 val &= ~dsiescclk[n].div_mask;
2104 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
2105 writel(val, PRCM_DSITVCLK_DIV);
2106}
2107
2108int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2109{
2110 if (clock < PRCMU_NUM_REG_CLOCKS)
2111 set_clock_rate(clock, rate);
2112 else if (clock == PRCMU_PLLDSI)
2113 return set_plldsi_rate(rate);
2114 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2115 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
2116 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2117 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
2118 return 0;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002119}
2120
Mattias Nilsson73180f82011-08-12 10:28:10 +02002121int db8500_prcmu_config_esram0_deep_sleep(u8 state)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002122{
2123 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2124 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2125 return -EINVAL;
2126
2127 mutex_lock(&mb4_transfer.lock);
2128
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002129 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002130 cpu_relax();
2131
2132 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2133 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2134 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2135 writeb(DDR_PWR_STATE_ON,
2136 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2137 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2138
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002139 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002140 wait_for_completion(&mb4_transfer.work);
2141
2142 mutex_unlock(&mb4_transfer.lock);
2143
2144 return 0;
2145}
2146
Mattias Nilsson05089012012-01-13 16:20:20 +01002147int db8500_prcmu_config_hotdog(u8 threshold)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002148{
2149 mutex_lock(&mb4_transfer.lock);
2150
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002151 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002152 cpu_relax();
2153
2154 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2155 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2156
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002157 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002158 wait_for_completion(&mb4_transfer.work);
2159
2160 mutex_unlock(&mb4_transfer.lock);
2161
2162 return 0;
2163}
2164
Mattias Nilsson05089012012-01-13 16:20:20 +01002165int db8500_prcmu_config_hotmon(u8 low, u8 high)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002166{
2167 mutex_lock(&mb4_transfer.lock);
2168
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002169 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002170 cpu_relax();
2171
2172 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2173 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2174 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2175 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2176 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2177
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002178 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002179 wait_for_completion(&mb4_transfer.work);
2180
2181 mutex_unlock(&mb4_transfer.lock);
2182
2183 return 0;
2184}
2185
2186static int config_hot_period(u16 val)
2187{
2188 mutex_lock(&mb4_transfer.lock);
2189
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002190 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002191 cpu_relax();
2192
2193 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2194 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2195
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002196 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002197 wait_for_completion(&mb4_transfer.work);
2198
2199 mutex_unlock(&mb4_transfer.lock);
2200
2201 return 0;
2202}
2203
Mattias Nilsson05089012012-01-13 16:20:20 +01002204int db8500_prcmu_start_temp_sense(u16 cycles32k)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002205{
2206 if (cycles32k == 0xFFFF)
2207 return -EINVAL;
2208
2209 return config_hot_period(cycles32k);
2210}
2211
Mattias Nilsson05089012012-01-13 16:20:20 +01002212int db8500_prcmu_stop_temp_sense(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002213{
2214 return config_hot_period(0xFFFF);
2215}
2216
Jonas Aberg84165b82011-08-12 10:28:33 +02002217static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2218{
2219
2220 mutex_lock(&mb4_transfer.lock);
2221
2222 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2223 cpu_relax();
2224
2225 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2226 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2227 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2228 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2229
2230 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2231
2232 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2233 wait_for_completion(&mb4_transfer.work);
2234
2235 mutex_unlock(&mb4_transfer.lock);
2236
2237 return 0;
2238
2239}
2240
Mattias Nilsson05089012012-01-13 16:20:20 +01002241int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
Jonas Aberg84165b82011-08-12 10:28:33 +02002242{
2243 BUG_ON(num == 0 || num > 0xf);
2244 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2245 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2246 A9WDOG_AUTO_OFF_DIS);
2247}
2248
Mattias Nilsson05089012012-01-13 16:20:20 +01002249int db8500_prcmu_enable_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002250{
2251 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2252}
2253
Mattias Nilsson05089012012-01-13 16:20:20 +01002254int db8500_prcmu_disable_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002255{
2256 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2257}
2258
Mattias Nilsson05089012012-01-13 16:20:20 +01002259int db8500_prcmu_kick_a9wdog(u8 id)
Jonas Aberg84165b82011-08-12 10:28:33 +02002260{
2261 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2262}
2263
2264/*
2265 * timeout is 28 bit, in ms.
2266 */
Mattias Nilsson05089012012-01-13 16:20:20 +01002267int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
Jonas Aberg84165b82011-08-12 10:28:33 +02002268{
Jonas Aberg84165b82011-08-12 10:28:33 +02002269 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2270 (id & A9WDOG_ID_MASK) |
2271 /*
2272 * Put the lowest 28 bits of timeout at
2273 * offset 4. Four first bits are used for id.
2274 */
2275 (u8)((timeout << 4) & 0xf0),
2276 (u8)((timeout >> 4) & 0xff),
2277 (u8)((timeout >> 12) & 0xff),
2278 (u8)((timeout >> 20) & 0xff));
2279}
2280
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002281/**
Linus Walleije3726fc2010-08-19 12:36:01 +01002282 * prcmu_abb_read() - Read register value(s) from the ABB.
2283 * @slave: The I2C slave address.
2284 * @reg: The (start) register address.
2285 * @value: The read out value(s).
2286 * @size: The number of registers to read.
2287 *
2288 * Reads register value(s) from the ABB.
2289 * @size has to be 1 for the current firmware version.
2290 */
2291int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2292{
2293 int r;
2294
2295 if (size != 1)
2296 return -EINVAL;
2297
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002298 mutex_lock(&mb5_transfer.lock);
Linus Walleije3726fc2010-08-19 12:36:01 +01002299
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002300 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
Linus Walleije3726fc2010-08-19 12:36:01 +01002301 cpu_relax();
2302
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002303 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2304 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2305 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2306 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
Linus Walleije3726fc2010-08-19 12:36:01 +01002307
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002308 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002309
Linus Walleije3726fc2010-08-19 12:36:01 +01002310 if (!wait_for_completion_timeout(&mb5_transfer.work,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002311 msecs_to_jiffies(20000))) {
2312 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2313 __func__);
Linus Walleije3726fc2010-08-19 12:36:01 +01002314 r = -EIO;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002315 } else {
2316 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
Linus Walleije3726fc2010-08-19 12:36:01 +01002317 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002318
Linus Walleije3726fc2010-08-19 12:36:01 +01002319 if (!r)
2320 *value = mb5_transfer.ack.value;
2321
Linus Walleije3726fc2010-08-19 12:36:01 +01002322 mutex_unlock(&mb5_transfer.lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002323
Linus Walleije3726fc2010-08-19 12:36:01 +01002324 return r;
2325}
Linus Walleije3726fc2010-08-19 12:36:01 +01002326
2327/**
2328 * prcmu_abb_write() - Write register value(s) to the ABB.
2329 * @slave: The I2C slave address.
2330 * @reg: The (start) register address.
2331 * @value: The value(s) to write.
2332 * @size: The number of registers to write.
2333 *
2334 * Reads register value(s) from the ABB.
2335 * @size has to be 1 for the current firmware version.
2336 */
2337int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2338{
2339 int r;
2340
2341 if (size != 1)
2342 return -EINVAL;
2343
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002344 mutex_lock(&mb5_transfer.lock);
Linus Walleije3726fc2010-08-19 12:36:01 +01002345
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002346 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
Linus Walleije3726fc2010-08-19 12:36:01 +01002347 cpu_relax();
2348
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002349 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2350 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2351 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2352 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
Linus Walleije3726fc2010-08-19 12:36:01 +01002353
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002354 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002355
Linus Walleije3726fc2010-08-19 12:36:01 +01002356 if (!wait_for_completion_timeout(&mb5_transfer.work,
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002357 msecs_to_jiffies(20000))) {
2358 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2359 __func__);
Linus Walleije3726fc2010-08-19 12:36:01 +01002360 r = -EIO;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002361 } else {
2362 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
Linus Walleije3726fc2010-08-19 12:36:01 +01002363 }
Linus Walleije3726fc2010-08-19 12:36:01 +01002364
Linus Walleije3726fc2010-08-19 12:36:01 +01002365 mutex_unlock(&mb5_transfer.lock);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002366
Linus Walleije3726fc2010-08-19 12:36:01 +01002367 return r;
2368}
Linus Walleije3726fc2010-08-19 12:36:01 +01002369
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002370/**
2371 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2372 */
2373void prcmu_ac_wake_req(void)
Martin Perssone0befb22010-12-08 15:13:28 +01002374{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002375 u32 val;
Mattias Nilssond6e30022011-08-12 10:28:43 +02002376 u32 status;
Martin Perssone0befb22010-12-08 15:13:28 +01002377
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002378 mutex_lock(&mb0_transfer.ac_wake_lock);
Martin Perssone0befb22010-12-08 15:13:28 +01002379
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002380 val = readl(PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002381 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2382 goto unlock_and_return;
2383
2384 atomic_set(&ac_wake_req_state, 1);
2385
Mattias Nilssond6e30022011-08-12 10:28:43 +02002386retry:
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002387 writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002388
2389 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
Mattias Nilssond6e30022011-08-12 10:28:43 +02002390 msecs_to_jiffies(5000))) {
Linus Walleij57265bc2011-10-10 13:04:44 +02002391 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
Mattias Nilssond6e30022011-08-12 10:28:43 +02002392 __func__);
2393 goto unlock_and_return;
2394 }
2395
2396 /*
2397 * The modem can generate an AC_WAKE_ACK, and then still go to sleep.
2398 * As a workaround, we wait, and then check that the modem is indeed
2399 * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS
2400 * register, which may not be the whole truth).
2401 */
2402 udelay(400);
2403 status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2));
2404 if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE |
2405 PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) {
2406 pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n",
2407 __func__, status);
2408 udelay(1200);
2409 writel(val, PRCM_HOSTACCESS_REQ);
2410 if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2411 msecs_to_jiffies(5000)))
2412 goto retry;
Linus Walleij57265bc2011-10-10 13:04:44 +02002413 pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n",
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002414 __func__);
2415 }
2416
2417unlock_and_return:
2418 mutex_unlock(&mb0_transfer.ac_wake_lock);
2419}
2420
2421/**
2422 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2423 */
2424void prcmu_ac_sleep_req()
2425{
2426 u32 val;
2427
2428 mutex_lock(&mb0_transfer.ac_wake_lock);
2429
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002430 val = readl(PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002431 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2432 goto unlock_and_return;
2433
2434 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002435 PRCM_HOSTACCESS_REQ);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002436
2437 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
Mattias Nilssond6e30022011-08-12 10:28:43 +02002438 msecs_to_jiffies(5000))) {
Linus Walleij57265bc2011-10-10 13:04:44 +02002439 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002440 __func__);
2441 }
2442
2443 atomic_set(&ac_wake_req_state, 0);
2444
2445unlock_and_return:
2446 mutex_unlock(&mb0_transfer.ac_wake_lock);
2447}
2448
Mattias Nilsson73180f82011-08-12 10:28:10 +02002449bool db8500_prcmu_is_ac_wake_requested(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002450{
2451 return (atomic_read(&ac_wake_req_state) != 0);
2452}
2453
2454/**
Mattias Nilsson73180f82011-08-12 10:28:10 +02002455 * db8500_prcmu_system_reset - System reset
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002456 *
Mattias Nilsson73180f82011-08-12 10:28:10 +02002457 * Saves the reset reason code and then sets the APE_SOFTRST register which
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002458 * fires interrupt to fw
2459 */
Mattias Nilsson73180f82011-08-12 10:28:10 +02002460void db8500_prcmu_system_reset(u16 reset_code)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002461{
2462 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002463 writel(1, PRCM_APE_SOFTRST);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002464}
2465
2466/**
Sebastian Rasmussen597045d2011-08-12 10:28:53 +02002467 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2468 *
2469 * Retrieves the reset reason code stored by prcmu_system_reset() before
2470 * last restart.
2471 */
2472u16 db8500_prcmu_get_reset_code(void)
2473{
2474 return readw(tcdm_base + PRCM_SW_RST_REASON);
2475}
2476
2477/**
Mattias Nilsson05089012012-01-13 16:20:20 +01002478 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002479 */
Mattias Nilsson05089012012-01-13 16:20:20 +01002480void db8500_prcmu_modem_reset(void)
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002481{
Martin Perssone0befb22010-12-08 15:13:28 +01002482 mutex_lock(&mb1_transfer.lock);
2483
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002484 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
Martin Perssone0befb22010-12-08 15:13:28 +01002485 cpu_relax();
2486
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002487 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002488 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
Martin Perssone0befb22010-12-08 15:13:28 +01002489 wait_for_completion(&mb1_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002490
2491 /*
2492 * No need to check return from PRCMU as modem should go in reset state
2493 * This state is already managed by upper layer
2494 */
Martin Perssone0befb22010-12-08 15:13:28 +01002495
2496 mutex_unlock(&mb1_transfer.lock);
Martin Perssone0befb22010-12-08 15:13:28 +01002497}
2498
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002499static void ack_dbb_wakeup(void)
Martin Perssone0befb22010-12-08 15:13:28 +01002500{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002501 unsigned long flags;
Martin Perssone0befb22010-12-08 15:13:28 +01002502
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002503 spin_lock_irqsave(&mb0_transfer.lock, flags);
Martin Perssone0befb22010-12-08 15:13:28 +01002504
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002505 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002506 cpu_relax();
Martin Perssone0befb22010-12-08 15:13:28 +01002507
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002508 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002509 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
Martin Perssone0befb22010-12-08 15:13:28 +01002510
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002511 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
Martin Perssone0befb22010-12-08 15:13:28 +01002512}
2513
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002514static inline void print_unknown_header_warning(u8 n, u8 header)
Linus Walleije3726fc2010-08-19 12:36:01 +01002515{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002516 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2517 header, n);
Linus Walleije3726fc2010-08-19 12:36:01 +01002518}
2519
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002520static bool read_mailbox_0(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002521{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002522 bool r;
2523 u32 ev;
2524 unsigned int n;
2525 u8 header;
2526
2527 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2528 switch (header) {
2529 case MB0H_WAKEUP_EXE:
2530 case MB0H_WAKEUP_SLEEP:
2531 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2532 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2533 else
2534 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2535
2536 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2537 complete(&mb0_transfer.ac_wake_work);
2538 if (ev & WAKEUP_BIT_SYSCLK_OK)
2539 complete(&mb3_transfer.sysclk_work);
2540
2541 ev &= mb0_transfer.req.dbb_irqs;
2542
2543 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2544 if (ev & prcmu_irq_bit[n])
2545 generic_handle_irq(IRQ_PRCMU_BASE + n);
2546 }
2547 r = true;
2548 break;
2549 default:
2550 print_unknown_header_warning(0, header);
2551 r = false;
2552 break;
2553 }
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002554 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002555 return r;
2556}
2557
2558static bool read_mailbox_1(void)
2559{
2560 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2561 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2562 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2563 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2564 PRCM_ACK_MB1_CURRENT_APE_OPP);
2565 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2566 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002567 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
Martin Perssone0befb22010-12-08 15:13:28 +01002568 complete(&mb1_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002569 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002570}
2571
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002572static bool read_mailbox_2(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002573{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002574 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002575 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002576 complete(&mb2_transfer.work);
2577 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002578}
2579
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002580static bool read_mailbox_3(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002581{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002582 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002583 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002584}
2585
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002586static bool read_mailbox_4(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002587{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002588 u8 header;
2589 bool do_complete = true;
2590
2591 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2592 switch (header) {
2593 case MB4H_MEM_ST:
2594 case MB4H_HOTDOG:
2595 case MB4H_HOTMON:
2596 case MB4H_HOT_PERIOD:
Mattias Nilssona592c2e2011-08-12 10:27:41 +02002597 case MB4H_A9WDOG_CONF:
2598 case MB4H_A9WDOG_EN:
2599 case MB4H_A9WDOG_DIS:
2600 case MB4H_A9WDOG_LOAD:
2601 case MB4H_A9WDOG_KICK:
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002602 break;
2603 default:
2604 print_unknown_header_warning(4, header);
2605 do_complete = false;
2606 break;
2607 }
2608
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002609 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002610
2611 if (do_complete)
2612 complete(&mb4_transfer.work);
2613
2614 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002615}
2616
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002617static bool read_mailbox_5(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002618{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002619 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2620 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002621 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
Linus Walleije3726fc2010-08-19 12:36:01 +01002622 complete(&mb5_transfer.work);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002623 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002624}
2625
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002626static bool read_mailbox_6(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002627{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002628 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002629 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002630}
2631
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002632static bool read_mailbox_7(void)
Linus Walleije3726fc2010-08-19 12:36:01 +01002633{
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002634 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002635 return false;
Linus Walleije3726fc2010-08-19 12:36:01 +01002636}
2637
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002638static bool (* const read_mailbox[NUM_MB])(void) = {
Linus Walleije3726fc2010-08-19 12:36:01 +01002639 read_mailbox_0,
2640 read_mailbox_1,
2641 read_mailbox_2,
2642 read_mailbox_3,
2643 read_mailbox_4,
2644 read_mailbox_5,
2645 read_mailbox_6,
2646 read_mailbox_7
2647};
2648
2649static irqreturn_t prcmu_irq_handler(int irq, void *data)
2650{
2651 u32 bits;
2652 u8 n;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002653 irqreturn_t r;
Linus Walleije3726fc2010-08-19 12:36:01 +01002654
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02002655 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
Linus Walleije3726fc2010-08-19 12:36:01 +01002656 if (unlikely(!bits))
2657 return IRQ_NONE;
2658
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002659 r = IRQ_HANDLED;
Linus Walleije3726fc2010-08-19 12:36:01 +01002660 for (n = 0; bits; n++) {
2661 if (bits & MBOX_BIT(n)) {
2662 bits -= MBOX_BIT(n);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002663 if (read_mailbox[n]())
2664 r = IRQ_WAKE_THREAD;
Linus Walleije3726fc2010-08-19 12:36:01 +01002665 }
2666 }
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002667 return r;
2668}
2669
2670static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2671{
2672 ack_dbb_wakeup();
Linus Walleije3726fc2010-08-19 12:36:01 +01002673 return IRQ_HANDLED;
2674}
2675
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002676static void prcmu_mask_work(struct work_struct *work)
2677{
2678 unsigned long flags;
2679
2680 spin_lock_irqsave(&mb0_transfer.lock, flags);
2681
2682 config_wakeups();
2683
2684 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2685}
2686
2687static void prcmu_irq_mask(struct irq_data *d)
2688{
2689 unsigned long flags;
2690
2691 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2692
2693 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2694
2695 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2696
2697 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2698 schedule_work(&mb0_transfer.mask_work);
2699}
2700
2701static void prcmu_irq_unmask(struct irq_data *d)
2702{
2703 unsigned long flags;
2704
2705 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2706
2707 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2708
2709 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2710
2711 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2712 schedule_work(&mb0_transfer.mask_work);
2713}
2714
2715static void noop(struct irq_data *d)
2716{
2717}
2718
2719static struct irq_chip prcmu_irq_chip = {
2720 .name = "prcmu",
2721 .irq_disable = prcmu_irq_mask,
2722 .irq_ack = noop,
2723 .irq_mask = prcmu_irq_mask,
2724 .irq_unmask = prcmu_irq_unmask,
2725};
2726
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002727static char *fw_project_name(u8 project)
2728{
2729 switch (project) {
2730 case PRCMU_FW_PROJECT_U8500:
2731 return "U8500";
2732 case PRCMU_FW_PROJECT_U8500_C2:
2733 return "U8500 C2";
2734 case PRCMU_FW_PROJECT_U9500:
2735 return "U9500";
2736 case PRCMU_FW_PROJECT_U9500_C2:
2737 return "U9500 C2";
2738 default:
2739 return "Unknown";
2740 }
2741}
2742
Mattias Nilsson73180f82011-08-12 10:28:10 +02002743void __init db8500_prcmu_early_init(void)
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002744{
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002745 unsigned int i;
Linus Walleij3e2762c2012-01-02 14:17:40 +01002746 if (cpu_is_u8500v2()) {
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002747 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2748
2749 if (tcpm_base != NULL) {
Linus Walleij3e2762c2012-01-02 14:17:40 +01002750 u32 version;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002751 version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
Mattias Nilssonb58d12f2012-01-13 16:20:10 +01002752 fw_info.version.project = version & 0xFF;
2753 fw_info.version.api_version = (version >> 8) & 0xFF;
2754 fw_info.version.func_version = (version >> 16) & 0xFF;
2755 fw_info.version.errata = (version >> 24) & 0xFF;
2756 fw_info.valid = true;
2757 pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2758 fw_project_name(fw_info.version.project),
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002759 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2760 (version >> 24) & 0xFF);
2761 iounmap(tcpm_base);
2762 }
2763
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002764 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2765 } else {
2766 pr_err("prcmu: Unsupported chip version\n");
2767 BUG();
2768 }
Mattias Wallinfcbd4582010-12-02 16:20:42 +01002769
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002770 spin_lock_init(&mb0_transfer.lock);
2771 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2772 mutex_init(&mb0_transfer.ac_wake_lock);
2773 init_completion(&mb0_transfer.ac_wake_work);
Martin Perssone0befb22010-12-08 15:13:28 +01002774 mutex_init(&mb1_transfer.lock);
2775 init_completion(&mb1_transfer.work);
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +01002776 mb1_transfer.ape_opp = APE_NO_CHANGE;
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002777 mutex_init(&mb2_transfer.lock);
2778 init_completion(&mb2_transfer.work);
2779 spin_lock_init(&mb2_transfer.auto_pm_lock);
2780 spin_lock_init(&mb3_transfer.lock);
2781 mutex_init(&mb3_transfer.sysclk_lock);
2782 init_completion(&mb3_transfer.sysclk_work);
2783 mutex_init(&mb4_transfer.lock);
2784 init_completion(&mb4_transfer.work);
Linus Walleije3726fc2010-08-19 12:36:01 +01002785 mutex_init(&mb5_transfer.lock);
2786 init_completion(&mb5_transfer.work);
2787
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002788 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
Linus Walleije3726fc2010-08-19 12:36:01 +01002789
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02002790 /* Initalize irqs. */
2791 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
2792 unsigned int irq;
2793
2794 irq = IRQ_PRCMU_BASE + i;
2795 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
2796 handle_simple_irq);
2797 set_irq_flags(irq, IRQF_VALID);
2798 }
Linus Walleije3726fc2010-08-19 12:36:01 +01002799}
2800
Mattias Nilsson05089012012-01-13 16:20:20 +01002801static void __init init_prcm_registers(void)
Mattias Nilssond65e12d2011-08-12 10:27:50 +02002802{
2803 u32 val;
2804
2805 val = readl(PRCM_A9PL_FORCE_CLKEN);
2806 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2807 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2808 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2809}
2810
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002811/*
2812 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2813 */
2814static struct regulator_consumer_supply db8500_vape_consumers[] = {
2815 REGULATOR_SUPPLY("v-ape", NULL),
2816 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2817 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2818 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2819 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2820 /* "v-mmc" changed to "vcore" in the mainline kernel */
2821 REGULATOR_SUPPLY("vcore", "sdi0"),
2822 REGULATOR_SUPPLY("vcore", "sdi1"),
2823 REGULATOR_SUPPLY("vcore", "sdi2"),
2824 REGULATOR_SUPPLY("vcore", "sdi3"),
2825 REGULATOR_SUPPLY("vcore", "sdi4"),
2826 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2827 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2828 /* "v-uart" changed to "vcore" in the mainline kernel */
2829 REGULATOR_SUPPLY("vcore", "uart0"),
2830 REGULATOR_SUPPLY("vcore", "uart1"),
2831 REGULATOR_SUPPLY("vcore", "uart2"),
2832 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
Bengt Jonsson992b1332012-01-13 16:20:36 +01002833 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002834};
2835
2836static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002837 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2838 /* AV8100 regulator */
2839 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2840};
2841
2842static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002843 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002844 REGULATOR_SUPPLY("vsupply", "mcde"),
2845};
2846
2847/* SVA MMDSP regulator switch */
2848static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2849 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2850};
2851
2852/* SVA pipe regulator switch */
2853static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2854 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2855};
2856
2857/* SIA MMDSP regulator switch */
2858static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2859 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2860};
2861
2862/* SIA pipe regulator switch */
2863static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2864 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2865};
2866
2867static struct regulator_consumer_supply db8500_sga_consumers[] = {
2868 REGULATOR_SUPPLY("v-mali", NULL),
2869};
2870
2871/* ESRAM1 and 2 regulator switch */
2872static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2873 REGULATOR_SUPPLY("esram12", "cm_control"),
2874};
2875
2876/* ESRAM3 and 4 regulator switch */
2877static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2878 REGULATOR_SUPPLY("v-esram34", "mcde"),
2879 REGULATOR_SUPPLY("esram34", "cm_control"),
Bengt Jonsson992b1332012-01-13 16:20:36 +01002880 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002881};
2882
2883static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2884 [DB8500_REGULATOR_VAPE] = {
2885 .constraints = {
2886 .name = "db8500-vape",
2887 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2888 },
2889 .consumer_supplies = db8500_vape_consumers,
2890 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2891 },
2892 [DB8500_REGULATOR_VARM] = {
2893 .constraints = {
2894 .name = "db8500-varm",
2895 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2896 },
2897 },
2898 [DB8500_REGULATOR_VMODEM] = {
2899 .constraints = {
2900 .name = "db8500-vmodem",
2901 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2902 },
2903 },
2904 [DB8500_REGULATOR_VPLL] = {
2905 .constraints = {
2906 .name = "db8500-vpll",
2907 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2908 },
2909 },
2910 [DB8500_REGULATOR_VSMPS1] = {
2911 .constraints = {
2912 .name = "db8500-vsmps1",
2913 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2914 },
2915 },
2916 [DB8500_REGULATOR_VSMPS2] = {
2917 .constraints = {
2918 .name = "db8500-vsmps2",
2919 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920 },
2921 .consumer_supplies = db8500_vsmps2_consumers,
2922 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2923 },
2924 [DB8500_REGULATOR_VSMPS3] = {
2925 .constraints = {
2926 .name = "db8500-vsmps3",
2927 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2928 },
2929 },
2930 [DB8500_REGULATOR_VRF1] = {
2931 .constraints = {
2932 .name = "db8500-vrf1",
2933 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2934 },
2935 },
2936 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002937 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002938 .constraints = {
2939 .name = "db8500-sva-mmdsp",
2940 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2941 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002942 .consumer_supplies = db8500_svammdsp_consumers,
2943 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002944 },
2945 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2946 .constraints = {
2947 /* "ret" means "retention" */
2948 .name = "db8500-sva-mmdsp-ret",
2949 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2950 },
2951 },
2952 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002953 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002954 .constraints = {
2955 .name = "db8500-sva-pipe",
2956 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2957 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002958 .consumer_supplies = db8500_svapipe_consumers,
2959 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002960 },
2961 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002962 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002963 .constraints = {
2964 .name = "db8500-sia-mmdsp",
2965 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2966 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002967 .consumer_supplies = db8500_siammdsp_consumers,
2968 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002969 },
2970 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2971 .constraints = {
2972 .name = "db8500-sia-mmdsp-ret",
2973 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2974 },
2975 },
2976 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01002977 /* dependency to u8500-vape is handled outside regulator framework */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002978 .constraints = {
2979 .name = "db8500-sia-pipe",
2980 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2981 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002982 .consumer_supplies = db8500_siapipe_consumers,
2983 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002984 },
2985 [DB8500_REGULATOR_SWITCH_SGA] = {
2986 .supply_regulator = "db8500-vape",
2987 .constraints = {
2988 .name = "db8500-sga",
2989 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2990 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02002991 .consumer_supplies = db8500_sga_consumers,
2992 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2993
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02002994 },
2995 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2996 .supply_regulator = "db8500-vape",
2997 .constraints = {
2998 .name = "db8500-b2r2-mcde",
2999 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3000 },
3001 .consumer_supplies = db8500_b2r2_mcde_consumers,
3002 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
3003 },
3004 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01003005 /*
3006 * esram12 is set in retention and supplied by Vsafe when Vape is off,
3007 * no need to hold Vape
3008 */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02003009 .constraints = {
3010 .name = "db8500-esram12",
3011 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3012 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02003013 .consumer_supplies = db8500_esram12_consumers,
3014 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02003015 },
3016 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
3017 .constraints = {
3018 .name = "db8500-esram12-ret",
3019 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3020 },
3021 },
3022 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
Bengt Jonsson992b1332012-01-13 16:20:36 +01003023 /*
3024 * esram34 is set in retention and supplied by Vsafe when Vape is off,
3025 * no need to hold Vape
3026 */
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02003027 .constraints = {
3028 .name = "db8500-esram34",
3029 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3030 },
Bengt Jonsson624e87c2011-08-12 10:29:02 +02003031 .consumer_supplies = db8500_esram34_consumers,
3032 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
Bengt Jonsson1032fbf2011-04-01 14:43:33 +02003033 },
3034 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3035 .constraints = {
3036 .name = "db8500-esram34-ret",
3037 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3038 },
3039 },
3040};
3041
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003042static struct mfd_cell db8500_prcmu_devs[] = {
3043 {
3044 .name = "db8500-prcmu-regulators",
Mattias Wallin1ed78912011-05-27 11:49:43 +02003045 .platform_data = &db8500_regulators,
3046 .pdata_size = sizeof(db8500_regulators),
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003047 },
3048 {
3049 .name = "cpufreq-u8500",
3050 },
3051};
3052
3053/**
3054 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3055 *
3056 */
3057static int __init db8500_prcmu_probe(struct platform_device *pdev)
3058{
3059 int err = 0;
3060
3061 if (ux500_is_svp())
3062 return -ENODEV;
3063
Mattias Nilsson05089012012-01-13 16:20:20 +01003064 init_prcm_registers();
Mattias Nilssond65e12d2011-08-12 10:27:50 +02003065
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003066 /* Clean up the mailbox interrupts after pre-kernel code. */
Mattias Nilssonc553b3c2011-08-12 10:27:20 +02003067 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
Mattias Nilsson3df57bc2011-05-16 00:15:05 +02003068
3069 err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler,
3070 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3071 if (err < 0) {
3072 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3073 err = -EBUSY;
3074 goto no_irq_return;
3075 }
3076
3077 if (cpu_is_u8500v20_or_later())
3078 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3079
3080 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3081 ARRAY_SIZE(db8500_prcmu_devs), NULL,
3082 0);
3083
3084 if (err)
3085 pr_err("prcmu: Failed to add subdevices\n");
3086 else
3087 pr_info("DB8500 PRCMU initialized\n");
3088
3089no_irq_return:
3090 return err;
3091}
3092
3093static struct platform_driver db8500_prcmu_driver = {
3094 .driver = {
3095 .name = "db8500-prcmu",
3096 .owner = THIS_MODULE,
3097 },
3098};
3099
3100static int __init db8500_prcmu_init(void)
3101{
3102 return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe);
3103}
3104
3105arch_initcall(db8500_prcmu_init);
3106
3107MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3108MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3109MODULE_LICENSE("GPL v2");