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Andrew Victorb2c65612007-02-08 09:42:40 +01001/*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
Nicolas Pitrec9dfafb2011-08-02 10:21:36 -040015#include <asm/proc-fns.h>
Russell King80b02c12009-01-08 10:01:47 +000016#include <asm/irq.h>
Andrew Victorb2c65612007-02-08 09:42:40 +010017#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
David Howells9f97da72012-03-28 18:30:01 +010019#include <asm/system_misc.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/at91sam9263.h>
Ludovic Desroches8fe82a52012-06-21 14:47:27 +020021#include <mach/at91_aic.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/at91_pmc.h>
23#include <mach/at91_rstc.h>
Andrew Victorb2c65612007-02-08 09:42:40 +010024
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080025#include "soc.h"
Andrew Victorb2c65612007-02-08 09:42:40 +010026#include "generic.h"
27#include "clock.h"
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +080028#include "sam9_smc.h"
Andrew Victorb2c65612007-02-08 09:42:40 +010029
Andrew Victorb2c65612007-02-08 09:42:40 +010030/* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34/*
35 * The peripheral clocks.
36 */
37static struct clk pioA_clk = {
38 .name = "pioA_clk",
39 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
41};
42static struct clk pioB_clk = {
43 .name = "pioB_clk",
44 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioCDE_clk = {
48 .name = "pioCDE_clk",
49 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk usart0_clk = {
53 .name = "usart0_clk",
54 .pmc_mask = 1 << AT91SAM9263_ID_US0,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart1_clk = {
58 .name = "usart1_clk",
59 .pmc_mask = 1 << AT91SAM9263_ID_US1,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk usart2_clk = {
63 .name = "usart2_clk",
64 .pmc_mask = 1 << AT91SAM9263_ID_US2,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk mmc0_clk = {
68 .name = "mci0_clk",
69 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc1_clk = {
73 .name = "mci1_clk",
74 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
75 .type = CLK_TYPE_PERIPHERAL,
76};
Andrew Victore8788ba2007-05-02 17:14:57 +010077static struct clk can_clk = {
78 .name = "can_clk",
79 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
80 .type = CLK_TYPE_PERIPHERAL,
81};
Andrew Victorb2c65612007-02-08 09:42:40 +010082static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
Andrew Victore8788ba2007-05-02 17:14:57 +010097static struct clk ssc0_clk = {
98 .name = "ssc0_clk",
99 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk ssc1_clk = {
103 .name = "ssc1_clk",
104 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk ac97_clk = {
108 .name = "ac97_clk",
109 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
110 .type = CLK_TYPE_PERIPHERAL,
111};
Andrew Victorb2c65612007-02-08 09:42:40 +0100112static struct clk tcb_clk = {
113 .name = "tcb_clk",
114 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
115 .type = CLK_TYPE_PERIPHERAL,
116};
Andrew Victorbb1ad682008-09-18 19:42:37 +0100117static struct clk pwm_clk = {
118 .name = "pwm_clk",
Andrew Victore8788ba2007-05-02 17:14:57 +0100119 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
120 .type = CLK_TYPE_PERIPHERAL,
121};
Andrew Victor69b2e992007-02-14 08:44:43 +0100122static struct clk macb_clk = {
Jamie Iles865d6052011-08-09 16:51:11 +0200123 .name = "pclk",
Andrew Victorb2c65612007-02-08 09:42:40 +0100124 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
125 .type = CLK_TYPE_PERIPHERAL,
126};
Andrew Victore8788ba2007-05-02 17:14:57 +0100127static struct clk dma_clk = {
128 .name = "dma_clk",
129 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk twodge_clk = {
133 .name = "2dge_clk",
134 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
135 .type = CLK_TYPE_PERIPHERAL,
136};
Andrew Victorb2c65612007-02-08 09:42:40 +0100137static struct clk udc_clk = {
138 .name = "udc_clk",
139 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk isi_clk = {
143 .name = "isi_clk",
144 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk lcdc_clk = {
148 .name = "lcdc_clk",
Andrew Victor7f6e2d92007-02-22 07:34:56 +0100149 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
Andrew Victorb2c65612007-02-08 09:42:40 +0100150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk ohci_clk = {
153 .name = "ohci_clk",
154 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157
158static struct clk *periph_clocks[] __initdata = {
159 &pioA_clk,
160 &pioB_clk,
161 &pioCDE_clk,
162 &usart0_clk,
163 &usart1_clk,
164 &usart2_clk,
165 &mmc0_clk,
166 &mmc1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100167 &can_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100168 &twi_clk,
169 &spi0_clk,
170 &spi1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100171 &ssc0_clk,
172 &ssc1_clk,
173 &ac97_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100174 &tcb_clk,
Andrew Victorbb1ad682008-09-18 19:42:37 +0100175 &pwm_clk,
Andrew Victor69b2e992007-02-14 08:44:43 +0100176 &macb_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100177 &twodge_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100178 &udc_clk,
179 &isi_clk,
180 &lcdc_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100181 &dma_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100182 &ohci_clk,
183 // irq0 .. irq1
184};
185
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100186static struct clk_lookup periph_clocks_lookups[] = {
Jamie Iles865d6052011-08-09 16:51:11 +0200187 /* One additional fake clock for macb_hclk */
188 CLKDEV_CON_ID("hclk", &macb_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100189 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
190 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
191 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
192 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
193 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
194 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
Jean-Christophe PLAGNIOL-VILLARD0af43162011-08-30 03:29:28 +0200196 /* fake hclk clock */
197 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
Jean-Christophe PLAGNIOL-VILLARD619d4a42011-11-13 13:00:58 +0800198 CLKDEV_CON_ID("pioA", &pioA_clk),
199 CLKDEV_CON_ID("pioB", &pioB_clk),
200 CLKDEV_CON_ID("pioC", &pioCDE_clk),
201 CLKDEV_CON_ID("pioD", &pioCDE_clk),
202 CLKDEV_CON_ID("pioE", &pioCDE_clk),
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800203 /* more usart lookup table for DT entries */
204 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
205 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
206 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
207 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
208 /* more tc lookup table for DT entries */
209 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
210 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
211 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
212 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100213};
214
215static struct clk_lookup usart_clocks_lookups[] = {
216 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
219 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
220};
221
Andrew Victorb2c65612007-02-08 09:42:40 +0100222/*
223 * The four programmable clocks.
224 * You must configure pin multiplexing to bring these signals out.
225 */
226static struct clk pck0 = {
227 .name = "pck0",
228 .pmc_mask = AT91_PMC_PCK0,
229 .type = CLK_TYPE_PROGRAMMABLE,
230 .id = 0,
231};
232static struct clk pck1 = {
233 .name = "pck1",
234 .pmc_mask = AT91_PMC_PCK1,
235 .type = CLK_TYPE_PROGRAMMABLE,
236 .id = 1,
237};
238static struct clk pck2 = {
239 .name = "pck2",
240 .pmc_mask = AT91_PMC_PCK2,
241 .type = CLK_TYPE_PROGRAMMABLE,
242 .id = 2,
243};
244static struct clk pck3 = {
245 .name = "pck3",
246 .pmc_mask = AT91_PMC_PCK3,
247 .type = CLK_TYPE_PROGRAMMABLE,
248 .id = 3,
249};
250
251static void __init at91sam9263_register_clocks(void)
252{
253 int i;
254
255 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
256 clk_register(periph_clocks[i]);
257
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100258 clkdev_add_table(periph_clocks_lookups,
259 ARRAY_SIZE(periph_clocks_lookups));
260 clkdev_add_table(usart_clocks_lookups,
261 ARRAY_SIZE(usart_clocks_lookups));
262
Andrew Victorb2c65612007-02-08 09:42:40 +0100263 clk_register(&pck0);
264 clk_register(&pck1);
265 clk_register(&pck2);
266 clk_register(&pck3);
267}
268
269/* --------------------------------------------------------------------
270 * GPIO
271 * -------------------------------------------------------------------- */
272
Jean-Christophe PLAGNIOL-VILLARD1a2d9152011-10-17 14:28:38 +0800273static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
Andrew Victorb2c65612007-02-08 09:42:40 +0100274 {
275 .id = AT91SAM9263_ID_PIOA,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800276 .regbase = AT91SAM9263_BASE_PIOA,
Andrew Victorb2c65612007-02-08 09:42:40 +0100277 }, {
278 .id = AT91SAM9263_ID_PIOB,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800279 .regbase = AT91SAM9263_BASE_PIOB,
Andrew Victorb2c65612007-02-08 09:42:40 +0100280 }, {
281 .id = AT91SAM9263_ID_PIOCDE,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800282 .regbase = AT91SAM9263_BASE_PIOC,
Andrew Victorb2c65612007-02-08 09:42:40 +0100283 }, {
284 .id = AT91SAM9263_ID_PIOCDE,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800285 .regbase = AT91SAM9263_BASE_PIOD,
Andrew Victorb2c65612007-02-08 09:42:40 +0100286 }, {
287 .id = AT91SAM9263_ID_PIOCDE,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800288 .regbase = AT91SAM9263_BASE_PIOE,
Andrew Victorb2c65612007-02-08 09:42:40 +0100289 }
290};
291
Andrew Victorb2c65612007-02-08 09:42:40 +0100292/* --------------------------------------------------------------------
293 * AT91SAM9263 processor initialization
294 * -------------------------------------------------------------------- */
295
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800296static void __init at91sam9263_map_io(void)
Andrew Victorb2c65612007-02-08 09:42:40 +0100297{
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800298 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
299 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800300}
Andrew Victorb2c65612007-02-08 09:42:40 +0100301
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800302static void __init at91sam9263_ioremap_registers(void)
303{
Jean-Christophe PLAGNIOL-VILLARDf22deee2011-11-01 01:23:20 +0800304 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
Jean-Christophe PLAGNIOL-VILLARDe9f68b52011-11-18 01:25:52 +0800305 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
Jean-Christophe PLAGNIOL-VILLARDf363c402012-02-13 12:58:53 +0800306 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
307 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +0800308 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +0800309 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
310 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
Jean-Christophe PLAGNIOL-VILLARD4342d642011-11-27 23:15:50 +0800311 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800312}
313
Jean-Christophe PLAGNIOL-VILLARD46539372011-04-24 18:20:28 +0800314static void __init at91sam9263_initialize(void)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800315{
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +0800316 arm_pm_idle = at91sam9_idle;
Russell King1b2073e2011-11-03 09:53:29 +0000317 arm_pm_restart = at91sam9_alt_restart;
Andrew Victorb2c65612007-02-08 09:42:40 +0100318 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
319
Andrew Victorb2c65612007-02-08 09:42:40 +0100320 /* Register GPIO subsystem */
321 at91_gpio_init(at91sam9263_gpio, 5);
322}
323
324/* --------------------------------------------------------------------
325 * Interrupt initialization
326 * -------------------------------------------------------------------- */
327
328/*
329 * The default interrupt priority levels (0 = lowest, 7 = highest).
330 */
331static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
332 7, /* Advanced Interrupt Controller (FIQ) */
333 7, /* System Peripherals */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100334 1, /* Parallel IO Controller A */
335 1, /* Parallel IO Controller B */
336 1, /* Parallel IO Controller C, D and E */
Andrew Victorb2c65612007-02-08 09:42:40 +0100337 0,
338 0,
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100339 5, /* USART 0 */
340 5, /* USART 1 */
341 5, /* USART 2 */
Andrew Victorb2c65612007-02-08 09:42:40 +0100342 0, /* Multimedia Card Interface 0 */
343 0, /* Multimedia Card Interface 1 */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100344 3, /* CAN */
345 6, /* Two-Wire Interface */
346 5, /* Serial Peripheral Interface 0 */
347 5, /* Serial Peripheral Interface 1 */
348 4, /* Serial Synchronous Controller 0 */
349 4, /* Serial Synchronous Controller 1 */
350 5, /* AC97 Controller */
Andrew Victorb2c65612007-02-08 09:42:40 +0100351 0, /* Timer Counter 0, 1 and 2 */
352 0, /* Pulse Width Modulation Controller */
353 3, /* Ethernet */
354 0,
355 0, /* 2D Graphic Engine */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100356 2, /* USB Device Port */
Andrew Victorb2c65612007-02-08 09:42:40 +0100357 0, /* Image Sensor Interface */
358 3, /* LDC Controller */
359 0, /* DMA Controller */
360 0,
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100361 2, /* USB Host port */
Andrew Victorb2c65612007-02-08 09:42:40 +0100362 0, /* Advanced Interrupt Controller (IRQ0) */
363 0, /* Advanced Interrupt Controller (IRQ1) */
364};
365
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800366struct at91_init_soc __initdata at91sam9263_soc = {
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800367 .map_io = at91sam9263_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800368 .default_irq_priority = at91sam9263_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800369 .ioremap_registers = at91sam9263_ioremap_registers,
Jean-Christophe PLAGNIOL-VILLARD51ddec72011-04-24 18:15:34 +0800370 .register_clocks = at91sam9263_register_clocks,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800371 .init = at91sam9263_initialize,
372};