blob: a85a9c2f1385564998929e3a914cafb74d867d9a [file] [log] [blame]
Johannes Bergab69bde2013-06-17 22:44:02 +02001/*
2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
3 *
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * This file incorporates work covered by the following copyright and
18 * permission notice:
19 *
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
21 *
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
33 */
34
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/ip.h>
39#include <linux/ipv6.h>
40#include <linux/if_vlan.h>
41#include <linux/mdio.h>
42#include <linux/aer.h>
43#include <linux/bitops.h>
44#include <linux/netdevice.h>
45#include <linux/etherdevice.h>
46#include <net/ip6_checksum.h>
47#include <linux/crc32.h>
48#include "alx.h"
49#include "hw.h"
50#include "reg.h"
51
52const char alx_drv_name[] = "alx";
53
54
55static void alx_free_txbuf(struct alx_priv *alx, int entry)
56{
57 struct alx_buffer *txb = &alx->txq.bufs[entry];
58
59 if (dma_unmap_len(txb, size)) {
60 dma_unmap_single(&alx->hw.pdev->dev,
61 dma_unmap_addr(txb, dma),
62 dma_unmap_len(txb, size),
63 DMA_TO_DEVICE);
64 dma_unmap_len_set(txb, size, 0);
65 }
66
67 if (txb->skb) {
68 dev_kfree_skb_any(txb->skb);
69 txb->skb = NULL;
70 }
71}
72
73static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
74{
75 struct alx_rx_queue *rxq = &alx->rxq;
76 struct sk_buff *skb;
77 struct alx_buffer *cur_buf;
78 dma_addr_t dma;
79 u16 cur, next, count = 0;
80
81 next = cur = rxq->write_idx;
82 if (++next == alx->rx_ringsz)
83 next = 0;
84 cur_buf = &rxq->bufs[cur];
85
86 while (!cur_buf->skb && next != rxq->read_idx) {
87 struct alx_rfd *rfd = &rxq->rfd[cur];
88
89 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size, gfp);
90 if (!skb)
91 break;
92 dma = dma_map_single(&alx->hw.pdev->dev,
93 skb->data, alx->rxbuf_size,
94 DMA_FROM_DEVICE);
95 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
96 dev_kfree_skb(skb);
97 break;
98 }
99
100 /* Unfortunately, RX descriptor buffers must be 4-byte
101 * aligned, so we can't use IP alignment.
102 */
103 if (WARN_ON(dma & 3)) {
104 dev_kfree_skb(skb);
105 break;
106 }
107
108 cur_buf->skb = skb;
109 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
110 dma_unmap_addr_set(cur_buf, dma, dma);
111 rfd->addr = cpu_to_le64(dma);
112
113 cur = next;
114 if (++next == alx->rx_ringsz)
115 next = 0;
116 cur_buf = &rxq->bufs[cur];
117 count++;
118 }
119
120 if (count) {
121 /* flush all updates before updating hardware */
122 wmb();
123 rxq->write_idx = cur;
124 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
125 }
126
127 return count;
128}
129
130static inline int alx_tpd_avail(struct alx_priv *alx)
131{
132 struct alx_tx_queue *txq = &alx->txq;
133
134 if (txq->write_idx >= txq->read_idx)
135 return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1;
136 return txq->read_idx - txq->write_idx - 1;
137}
138
139static bool alx_clean_tx_irq(struct alx_priv *alx)
140{
141 struct alx_tx_queue *txq = &alx->txq;
142 u16 hw_read_idx, sw_read_idx;
143 unsigned int total_bytes = 0, total_packets = 0;
144 int budget = ALX_DEFAULT_TX_WORK;
145
146 sw_read_idx = txq->read_idx;
147 hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX);
148
149 if (sw_read_idx != hw_read_idx) {
150 while (sw_read_idx != hw_read_idx && budget > 0) {
151 struct sk_buff *skb;
152
153 skb = txq->bufs[sw_read_idx].skb;
154 if (skb) {
155 total_bytes += skb->len;
156 total_packets++;
157 budget--;
158 }
159
160 alx_free_txbuf(alx, sw_read_idx);
161
162 if (++sw_read_idx == alx->tx_ringsz)
163 sw_read_idx = 0;
164 }
165 txq->read_idx = sw_read_idx;
166
167 netdev_completed_queue(alx->dev, total_packets, total_bytes);
168 }
169
170 if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) &&
171 alx_tpd_avail(alx) > alx->tx_ringsz/4)
172 netif_wake_queue(alx->dev);
173
174 return sw_read_idx == hw_read_idx;
175}
176
177static void alx_schedule_link_check(struct alx_priv *alx)
178{
179 schedule_work(&alx->link_check_wk);
180}
181
182static void alx_schedule_reset(struct alx_priv *alx)
183{
184 schedule_work(&alx->reset_wk);
185}
186
Eric Dumazet416b16c2015-01-11 10:32:18 -0800187static int alx_clean_rx_irq(struct alx_priv *alx, int budget)
Johannes Bergab69bde2013-06-17 22:44:02 +0200188{
189 struct alx_rx_queue *rxq = &alx->rxq;
190 struct alx_rrd *rrd;
191 struct alx_buffer *rxb;
192 struct sk_buff *skb;
193 u16 length, rfd_cleaned = 0;
Eric Dumazet416b16c2015-01-11 10:32:18 -0800194 int work = 0;
Johannes Bergab69bde2013-06-17 22:44:02 +0200195
Eric Dumazet416b16c2015-01-11 10:32:18 -0800196 while (work < budget) {
Johannes Bergab69bde2013-06-17 22:44:02 +0200197 rrd = &rxq->rrd[rxq->rrd_read_idx];
198 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
199 break;
200 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
201
202 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
203 RRD_SI) != rxq->read_idx ||
204 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
205 RRD_NOR) != 1) {
206 alx_schedule_reset(alx);
Eric Dumazet416b16c2015-01-11 10:32:18 -0800207 return work;
Johannes Bergab69bde2013-06-17 22:44:02 +0200208 }
209
210 rxb = &rxq->bufs[rxq->read_idx];
211 dma_unmap_single(&alx->hw.pdev->dev,
212 dma_unmap_addr(rxb, dma),
213 dma_unmap_len(rxb, size),
214 DMA_FROM_DEVICE);
215 dma_unmap_len_set(rxb, size, 0);
216 skb = rxb->skb;
217 rxb->skb = NULL;
218
219 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
220 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
221 rrd->word3 = 0;
222 dev_kfree_skb_any(skb);
223 goto next_pkt;
224 }
225
226 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
227 RRD_PKTLEN) - ETH_FCS_LEN;
228 skb_put(skb, length);
229 skb->protocol = eth_type_trans(skb, alx->dev);
230
231 skb_checksum_none_assert(skb);
232 if (alx->dev->features & NETIF_F_RXCSUM &&
233 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
234 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
235 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
236 RRD_PID)) {
237 case RRD_PID_IPV6UDP:
238 case RRD_PID_IPV4UDP:
239 case RRD_PID_IPV4TCP:
240 case RRD_PID_IPV6TCP:
241 skb->ip_summed = CHECKSUM_UNNECESSARY;
242 break;
243 }
244 }
245
246 napi_gro_receive(&alx->napi, skb);
Eric Dumazet416b16c2015-01-11 10:32:18 -0800247 work++;
Johannes Bergab69bde2013-06-17 22:44:02 +0200248
249next_pkt:
250 if (++rxq->read_idx == alx->rx_ringsz)
251 rxq->read_idx = 0;
252 if (++rxq->rrd_read_idx == alx->rx_ringsz)
253 rxq->rrd_read_idx = 0;
254
255 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
256 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
257 }
258
259 if (rfd_cleaned)
260 alx_refill_rx_ring(alx, GFP_ATOMIC);
261
Eric Dumazet416b16c2015-01-11 10:32:18 -0800262 return work;
Johannes Bergab69bde2013-06-17 22:44:02 +0200263}
264
265static int alx_poll(struct napi_struct *napi, int budget)
266{
267 struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
268 struct alx_hw *hw = &alx->hw;
Johannes Bergab69bde2013-06-17 22:44:02 +0200269 unsigned long flags;
Eric Dumazet416b16c2015-01-11 10:32:18 -0800270 bool tx_complete;
271 int work;
Johannes Bergab69bde2013-06-17 22:44:02 +0200272
Eric Dumazet416b16c2015-01-11 10:32:18 -0800273 tx_complete = alx_clean_tx_irq(alx);
274 work = alx_clean_rx_irq(alx, budget);
Johannes Bergab69bde2013-06-17 22:44:02 +0200275
Eric Dumazet416b16c2015-01-11 10:32:18 -0800276 if (!tx_complete || work == budget)
277 return budget;
Johannes Bergab69bde2013-06-17 22:44:02 +0200278
279 napi_complete(&alx->napi);
280
281 /* enable interrupt */
282 spin_lock_irqsave(&alx->irq_lock, flags);
283 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
284 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
285 spin_unlock_irqrestore(&alx->irq_lock, flags);
286
287 alx_post_write(hw);
288
Eric Dumazet416b16c2015-01-11 10:32:18 -0800289 return work;
Johannes Bergab69bde2013-06-17 22:44:02 +0200290}
291
292static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
293{
294 struct alx_hw *hw = &alx->hw;
295 bool write_int_mask = false;
296
297 spin_lock(&alx->irq_lock);
298
299 /* ACK interrupt */
300 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
301 intr &= alx->int_mask;
302
303 if (intr & ALX_ISR_FATAL) {
304 netif_warn(alx, hw, alx->dev,
305 "fatal interrupt 0x%x, resetting\n", intr);
306 alx_schedule_reset(alx);
307 goto out;
308 }
309
310 if (intr & ALX_ISR_ALERT)
311 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
312
313 if (intr & ALX_ISR_PHY) {
314 /* suppress PHY interrupt, because the source
315 * is from PHY internal. only the internal status
316 * is cleared, the interrupt status could be cleared.
317 */
318 alx->int_mask &= ~ALX_ISR_PHY;
319 write_int_mask = true;
320 alx_schedule_link_check(alx);
321 }
322
323 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
324 napi_schedule(&alx->napi);
325 /* mask rx/tx interrupt, enable them when napi complete */
326 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
327 write_int_mask = true;
328 }
329
330 if (write_int_mask)
331 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
332
333 alx_write_mem32(hw, ALX_ISR, 0);
334
335 out:
336 spin_unlock(&alx->irq_lock);
337 return IRQ_HANDLED;
338}
339
340static irqreturn_t alx_intr_msi(int irq, void *data)
341{
342 struct alx_priv *alx = data;
343
344 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
345}
346
347static irqreturn_t alx_intr_legacy(int irq, void *data)
348{
349 struct alx_priv *alx = data;
350 struct alx_hw *hw = &alx->hw;
351 u32 intr;
352
353 intr = alx_read_mem32(hw, ALX_ISR);
354
355 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
356 return IRQ_NONE;
357
358 return alx_intr_handle(alx, intr);
359}
360
361static void alx_init_ring_ptrs(struct alx_priv *alx)
362{
363 struct alx_hw *hw = &alx->hw;
364 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
365
366 alx->rxq.read_idx = 0;
367 alx->rxq.write_idx = 0;
368 alx->rxq.rrd_read_idx = 0;
369 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
370 alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma);
371 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
372 alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma);
373 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
374 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
375
376 alx->txq.read_idx = 0;
377 alx->txq.write_idx = 0;
378 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
379 alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma);
380 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
381
382 /* load these pointers into the chip */
383 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
384}
385
386static void alx_free_txring_buf(struct alx_priv *alx)
387{
388 struct alx_tx_queue *txq = &alx->txq;
389 int i;
390
391 if (!txq->bufs)
392 return;
393
394 for (i = 0; i < alx->tx_ringsz; i++)
395 alx_free_txbuf(alx, i);
396
397 memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer));
398 memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd));
399 txq->write_idx = 0;
400 txq->read_idx = 0;
401
402 netdev_reset_queue(alx->dev);
403}
404
405static void alx_free_rxring_buf(struct alx_priv *alx)
406{
407 struct alx_rx_queue *rxq = &alx->rxq;
408 struct alx_buffer *cur_buf;
409 u16 i;
410
411 if (rxq == NULL)
412 return;
413
414 for (i = 0; i < alx->rx_ringsz; i++) {
415 cur_buf = rxq->bufs + i;
416 if (cur_buf->skb) {
417 dma_unmap_single(&alx->hw.pdev->dev,
418 dma_unmap_addr(cur_buf, dma),
419 dma_unmap_len(cur_buf, size),
420 DMA_FROM_DEVICE);
421 dev_kfree_skb(cur_buf->skb);
422 cur_buf->skb = NULL;
423 dma_unmap_len_set(cur_buf, size, 0);
424 dma_unmap_addr_set(cur_buf, dma, 0);
425 }
426 }
427
428 rxq->write_idx = 0;
429 rxq->read_idx = 0;
430 rxq->rrd_read_idx = 0;
431}
432
433static void alx_free_buffers(struct alx_priv *alx)
434{
435 alx_free_txring_buf(alx);
436 alx_free_rxring_buf(alx);
437}
438
439static int alx_reinit_rings(struct alx_priv *alx)
440{
441 alx_free_buffers(alx);
442
443 alx_init_ring_ptrs(alx);
444
445 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
446 return -ENOMEM;
447
448 return 0;
449}
450
451static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
452{
453 u32 crc32, bit, reg;
454
455 crc32 = ether_crc(ETH_ALEN, addr);
456 reg = (crc32 >> 31) & 0x1;
457 bit = (crc32 >> 26) & 0x1F;
458
459 mc_hash[reg] |= BIT(bit);
460}
461
462static void __alx_set_rx_mode(struct net_device *netdev)
463{
464 struct alx_priv *alx = netdev_priv(netdev);
465 struct alx_hw *hw = &alx->hw;
466 struct netdev_hw_addr *ha;
467 u32 mc_hash[2] = {};
468
469 if (!(netdev->flags & IFF_ALLMULTI)) {
470 netdev_for_each_mc_addr(ha, netdev)
471 alx_add_mc_addr(hw, ha->addr, mc_hash);
472
473 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
474 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
475 }
476
477 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
478 if (netdev->flags & IFF_PROMISC)
479 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
480 if (netdev->flags & IFF_ALLMULTI)
481 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
482
483 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
484}
485
486static void alx_set_rx_mode(struct net_device *netdev)
487{
488 __alx_set_rx_mode(netdev);
489}
490
491static int alx_set_mac_address(struct net_device *netdev, void *data)
492{
493 struct alx_priv *alx = netdev_priv(netdev);
494 struct alx_hw *hw = &alx->hw;
495 struct sockaddr *addr = data;
496
497 if (!is_valid_ether_addr(addr->sa_data))
498 return -EADDRNOTAVAIL;
499
500 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
501 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
502
503 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
504 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
505 alx_set_macaddr(hw, hw->mac_addr);
506
507 return 0;
508}
509
510static int alx_alloc_descriptors(struct alx_priv *alx)
511{
512 alx->txq.bufs = kcalloc(alx->tx_ringsz,
513 sizeof(struct alx_buffer),
514 GFP_KERNEL);
515 if (!alx->txq.bufs)
516 return -ENOMEM;
517
518 alx->rxq.bufs = kcalloc(alx->rx_ringsz,
519 sizeof(struct alx_buffer),
520 GFP_KERNEL);
521 if (!alx->rxq.bufs)
522 goto out_free;
523
524 /* physical tx/rx ring descriptors
525 *
526 * Allocate them as a single chunk because they must not cross a
527 * 4G boundary (hardware has a single register for high 32 bits
528 * of addresses only)
529 */
530 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
531 sizeof(struct alx_rrd) * alx->rx_ringsz +
532 sizeof(struct alx_rfd) * alx->rx_ringsz;
533 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
534 alx->descmem.size,
535 &alx->descmem.dma,
536 GFP_KERNEL);
537 if (!alx->descmem.virt)
538 goto out_free;
539
540 alx->txq.tpd = (void *)alx->descmem.virt;
541 alx->txq.tpd_dma = alx->descmem.dma;
542
543 /* alignment requirement for next block */
544 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
545
546 alx->rxq.rrd =
547 (void *)((u8 *)alx->descmem.virt +
548 sizeof(struct alx_txd) * alx->tx_ringsz);
549 alx->rxq.rrd_dma = alx->descmem.dma +
550 sizeof(struct alx_txd) * alx->tx_ringsz;
551
552 /* alignment requirement for next block */
553 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
554
555 alx->rxq.rfd =
556 (void *)((u8 *)alx->descmem.virt +
557 sizeof(struct alx_txd) * alx->tx_ringsz +
558 sizeof(struct alx_rrd) * alx->rx_ringsz);
559 alx->rxq.rfd_dma = alx->descmem.dma +
560 sizeof(struct alx_txd) * alx->tx_ringsz +
561 sizeof(struct alx_rrd) * alx->rx_ringsz;
562
563 return 0;
564out_free:
565 kfree(alx->txq.bufs);
566 kfree(alx->rxq.bufs);
567 return -ENOMEM;
568}
569
570static int alx_alloc_rings(struct alx_priv *alx)
571{
572 int err;
573
574 err = alx_alloc_descriptors(alx);
575 if (err)
576 return err;
577
578 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
579 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
580 alx->tx_ringsz = alx->tx_ringsz;
581
582 netif_napi_add(alx->dev, &alx->napi, alx_poll, 64);
583
584 alx_reinit_rings(alx);
585 return 0;
586}
587
588static void alx_free_rings(struct alx_priv *alx)
589{
590 netif_napi_del(&alx->napi);
591 alx_free_buffers(alx);
592
593 kfree(alx->txq.bufs);
594 kfree(alx->rxq.bufs);
595
596 dma_free_coherent(&alx->hw.pdev->dev,
597 alx->descmem.size,
598 alx->descmem.virt,
599 alx->descmem.dma);
600}
601
602static void alx_config_vector_mapping(struct alx_priv *alx)
603{
604 struct alx_hw *hw = &alx->hw;
605
606 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
607 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
608 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
609}
610
611static void alx_irq_enable(struct alx_priv *alx)
612{
613 struct alx_hw *hw = &alx->hw;
614
615 /* level-1 interrupt switch */
616 alx_write_mem32(hw, ALX_ISR, 0);
617 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
618 alx_post_write(hw);
619}
620
621static void alx_irq_disable(struct alx_priv *alx)
622{
623 struct alx_hw *hw = &alx->hw;
624
625 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
626 alx_write_mem32(hw, ALX_IMR, 0);
627 alx_post_write(hw);
628
629 synchronize_irq(alx->hw.pdev->irq);
630}
631
632static int alx_request_irq(struct alx_priv *alx)
633{
634 struct pci_dev *pdev = alx->hw.pdev;
635 struct alx_hw *hw = &alx->hw;
636 int err;
637 u32 msi_ctrl;
638
639 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
640
641 if (!pci_enable_msi(alx->hw.pdev)) {
642 alx->msi = true;
643
644 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
645 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
646 err = request_irq(pdev->irq, alx_intr_msi, 0,
647 alx->dev->name, alx);
648 if (!err)
649 goto out;
650 /* fall back to legacy interrupt */
651 pci_disable_msi(alx->hw.pdev);
652 }
653
654 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
655 err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
656 alx->dev->name, alx);
657out:
658 if (!err)
659 alx_config_vector_mapping(alx);
660 return err;
661}
662
663static void alx_free_irq(struct alx_priv *alx)
664{
665 struct pci_dev *pdev = alx->hw.pdev;
666
667 free_irq(pdev->irq, alx);
668
669 if (alx->msi) {
670 pci_disable_msi(alx->hw.pdev);
671 alx->msi = false;
672 }
673}
674
675static int alx_identify_hw(struct alx_priv *alx)
676{
677 struct alx_hw *hw = &alx->hw;
678 int rev = alx_hw_revision(hw);
679
680 if (rev > ALX_REV_C0)
681 return -EINVAL;
682
683 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
684
685 return 0;
686}
687
688static int alx_init_sw(struct alx_priv *alx)
689{
690 struct pci_dev *pdev = alx->hw.pdev;
691 struct alx_hw *hw = &alx->hw;
692 int err;
693
694 err = alx_identify_hw(alx);
695 if (err) {
696 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
697 return err;
698 }
699
700 alx->hw.lnk_patch =
701 pdev->device == ALX_DEV_ID_AR8161 &&
702 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
703 pdev->subsystem_device == 0x0091 &&
704 pdev->revision == 0;
705
706 hw->smb_timer = 400;
707 hw->mtu = alx->dev->mtu;
708 alx->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8);
709 alx->tx_ringsz = 256;
710 alx->rx_ringsz = 512;
711 hw->sleep_ctrl = ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_WOL_PHY;
712 hw->imt = 200;
713 alx->int_mask = ALX_ISR_MISC;
714 hw->dma_chnl = hw->max_dma_chnl;
715 hw->ith_tpd = alx->tx_ringsz / 3;
716 hw->link_speed = SPEED_UNKNOWN;
717 hw->adv_cfg = ADVERTISED_Autoneg |
718 ADVERTISED_10baseT_Half |
719 ADVERTISED_10baseT_Full |
720 ADVERTISED_100baseT_Full |
721 ADVERTISED_100baseT_Half |
722 ADVERTISED_1000baseT_Full;
723 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
724
725 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
726 ALX_MAC_CTRL_MHASH_ALG_HI5B |
727 ALX_MAC_CTRL_BRD_EN |
728 ALX_MAC_CTRL_PCRCE |
729 ALX_MAC_CTRL_CRCE |
730 ALX_MAC_CTRL_RXFC_EN |
731 ALX_MAC_CTRL_TXFC_EN |
732 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
733
734 return err;
735}
736
737
738static netdev_features_t alx_fix_features(struct net_device *netdev,
739 netdev_features_t features)
740{
741 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
742 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
743
744 return features;
745}
746
747static void alx_netif_stop(struct alx_priv *alx)
748{
749 alx->dev->trans_start = jiffies;
750 if (netif_carrier_ok(alx->dev)) {
751 netif_carrier_off(alx->dev);
752 netif_tx_disable(alx->dev);
753 napi_disable(&alx->napi);
754 }
755}
756
757static void alx_halt(struct alx_priv *alx)
758{
759 struct alx_hw *hw = &alx->hw;
760
761 alx_netif_stop(alx);
762 hw->link_speed = SPEED_UNKNOWN;
763
764 alx_reset_mac(hw);
765
766 /* disable l0s/l1 */
767 alx_enable_aspm(hw, false, false);
768 alx_irq_disable(alx);
769 alx_free_buffers(alx);
770}
771
772static void alx_configure(struct alx_priv *alx)
773{
774 struct alx_hw *hw = &alx->hw;
775
776 alx_configure_basic(hw);
777 alx_disable_rss(hw);
778 __alx_set_rx_mode(alx->dev);
779
780 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
781}
782
783static void alx_activate(struct alx_priv *alx)
784{
785 /* hardware setting lost, restore it */
786 alx_reinit_rings(alx);
787 alx_configure(alx);
788
789 /* clear old interrupts */
790 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
791
792 alx_irq_enable(alx);
793
794 alx_schedule_link_check(alx);
795}
796
797static void alx_reinit(struct alx_priv *alx)
798{
799 ASSERT_RTNL();
800
801 alx_halt(alx);
802 alx_activate(alx);
803}
804
805static int alx_change_mtu(struct net_device *netdev, int mtu)
806{
807 struct alx_priv *alx = netdev_priv(netdev);
808 int max_frame = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
809
810 if ((max_frame < ALX_MIN_FRAME_SIZE) ||
811 (max_frame > ALX_MAX_FRAME_SIZE))
812 return -EINVAL;
813
814 if (netdev->mtu == mtu)
815 return 0;
816
817 netdev->mtu = mtu;
818 alx->hw.mtu = mtu;
819 alx->rxbuf_size = mtu > ALX_DEF_RXBUF_SIZE ?
820 ALIGN(max_frame, 8) : ALX_DEF_RXBUF_SIZE;
821 netdev_update_features(netdev);
822 if (netif_running(netdev))
823 alx_reinit(alx);
824 return 0;
825}
826
827static void alx_netif_start(struct alx_priv *alx)
828{
829 netif_tx_wake_all_queues(alx->dev);
830 napi_enable(&alx->napi);
831 netif_carrier_on(alx->dev);
832}
833
834static int __alx_open(struct alx_priv *alx, bool resume)
835{
836 int err;
837
838 if (!resume)
839 netif_carrier_off(alx->dev);
840
841 err = alx_alloc_rings(alx);
842 if (err)
843 return err;
844
845 alx_configure(alx);
846
847 err = alx_request_irq(alx);
848 if (err)
849 goto out_free_rings;
850
851 /* clear old interrupts */
852 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
853
854 alx_irq_enable(alx);
855
856 if (!resume)
857 netif_tx_start_all_queues(alx->dev);
858
859 alx_schedule_link_check(alx);
860 return 0;
861
862out_free_rings:
863 alx_free_rings(alx);
864 return err;
865}
866
867static void __alx_stop(struct alx_priv *alx)
868{
869 alx_halt(alx);
870 alx_free_irq(alx);
871 alx_free_rings(alx);
872}
873
874static const char *alx_speed_desc(u16 speed)
875{
876 switch (speed) {
877 case SPEED_1000 + DUPLEX_FULL:
878 return "1 Gbps Full";
879 case SPEED_100 + DUPLEX_FULL:
880 return "100 Mbps Full";
881 case SPEED_100 + DUPLEX_HALF:
882 return "100 Mbps Half";
883 case SPEED_10 + DUPLEX_FULL:
884 return "10 Mbps Full";
885 case SPEED_10 + DUPLEX_HALF:
886 return "10 Mbps Half";
887 default:
888 return "Unknown speed";
889 }
890}
891
892static void alx_check_link(struct alx_priv *alx)
893{
894 struct alx_hw *hw = &alx->hw;
895 unsigned long flags;
896 int speed, old_speed;
897 int err;
898
899 /* clear PHY internal interrupt status, otherwise the main
900 * interrupt status will be asserted forever
901 */
902 alx_clear_phy_intr(hw);
903
904 err = alx_get_phy_link(hw, &speed);
905 if (err < 0)
906 goto reset;
907
908 spin_lock_irqsave(&alx->irq_lock, flags);
909 alx->int_mask |= ALX_ISR_PHY;
910 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
911 spin_unlock_irqrestore(&alx->irq_lock, flags);
912
913 old_speed = hw->link_speed;
914
915 if (old_speed == speed)
916 return;
917 hw->link_speed = speed;
918
919 if (speed != SPEED_UNKNOWN) {
920 netif_info(alx, link, alx->dev,
921 "NIC Up: %s\n", alx_speed_desc(speed));
922 alx_post_phy_link(hw);
923 alx_enable_aspm(hw, true, true);
924 alx_start_mac(hw);
925
926 if (old_speed == SPEED_UNKNOWN)
927 alx_netif_start(alx);
928 } else {
929 /* link is now down */
930 alx_netif_stop(alx);
931 netif_info(alx, link, alx->dev, "Link Down\n");
932 err = alx_reset_mac(hw);
933 if (err)
934 goto reset;
935 alx_irq_disable(alx);
936
937 /* MAC reset causes all HW settings to be lost, restore all */
938 err = alx_reinit_rings(alx);
939 if (err)
940 goto reset;
941 alx_configure(alx);
942 alx_enable_aspm(hw, false, true);
943 alx_post_phy_link(hw);
944 alx_irq_enable(alx);
945 }
946
947 return;
948
949reset:
950 alx_schedule_reset(alx);
951}
952
953static int alx_open(struct net_device *netdev)
954{
955 return __alx_open(netdev_priv(netdev), false);
956}
957
958static int alx_stop(struct net_device *netdev)
959{
960 __alx_stop(netdev_priv(netdev));
961 return 0;
962}
963
964static int __alx_shutdown(struct pci_dev *pdev, bool *wol_en)
965{
966 struct alx_priv *alx = pci_get_drvdata(pdev);
967 struct net_device *netdev = alx->dev;
968 struct alx_hw *hw = &alx->hw;
969 int err, speed;
970
971 netif_device_detach(netdev);
972
973 if (netif_running(netdev))
974 __alx_stop(alx);
975
976#ifdef CONFIG_PM_SLEEP
977 err = pci_save_state(pdev);
978 if (err)
979 return err;
980#endif
981
982 err = alx_select_powersaving_speed(hw, &speed);
983 if (err)
984 return err;
985 err = alx_clear_phy_intr(hw);
986 if (err)
987 return err;
988 err = alx_pre_suspend(hw, speed);
989 if (err)
990 return err;
991 err = alx_config_wol(hw);
992 if (err)
993 return err;
994
995 *wol_en = false;
996 if (hw->sleep_ctrl & ALX_SLEEP_ACTIVE) {
997 netif_info(alx, wol, netdev,
998 "wol: ctrl=%X, speed=%X\n",
999 hw->sleep_ctrl, speed);
1000 device_set_wakeup_enable(&pdev->dev, true);
1001 *wol_en = true;
1002 }
1003
1004 pci_disable_device(pdev);
1005
1006 return 0;
1007}
1008
1009static void alx_shutdown(struct pci_dev *pdev)
1010{
1011 int err;
1012 bool wol_en;
1013
1014 err = __alx_shutdown(pdev, &wol_en);
1015 if (!err) {
1016 pci_wake_from_d3(pdev, wol_en);
1017 pci_set_power_state(pdev, PCI_D3hot);
1018 } else {
1019 dev_err(&pdev->dev, "shutdown fail %d\n", err);
1020 }
1021}
1022
1023static void alx_link_check(struct work_struct *work)
1024{
1025 struct alx_priv *alx;
1026
1027 alx = container_of(work, struct alx_priv, link_check_wk);
1028
1029 rtnl_lock();
1030 alx_check_link(alx);
1031 rtnl_unlock();
1032}
1033
1034static void alx_reset(struct work_struct *work)
1035{
1036 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
1037
1038 rtnl_lock();
1039 alx_reinit(alx);
1040 rtnl_unlock();
1041}
1042
1043static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
1044{
1045 u8 cso, css;
1046
1047 if (skb->ip_summed != CHECKSUM_PARTIAL)
1048 return 0;
1049
1050 cso = skb_checksum_start_offset(skb);
1051 if (cso & 1)
1052 return -EINVAL;
1053
1054 css = cso + skb->csum_offset;
1055 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
1056 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
1057 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1058
1059 return 0;
1060}
1061
1062static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb)
1063{
1064 struct alx_tx_queue *txq = &alx->txq;
1065 struct alx_txd *tpd, *first_tpd;
1066 dma_addr_t dma;
1067 int maplen, f, first_idx = txq->write_idx;
1068
1069 first_tpd = &txq->tpd[txq->write_idx];
1070 tpd = first_tpd;
1071
1072 maplen = skb_headlen(skb);
1073 dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen,
1074 DMA_TO_DEVICE);
1075 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1076 goto err_dma;
1077
1078 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1079 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1080
1081 tpd->adrl.addr = cpu_to_le64(dma);
1082 tpd->len = cpu_to_le16(maplen);
1083
1084 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1085 struct skb_frag_struct *frag;
1086
1087 frag = &skb_shinfo(skb)->frags[f];
1088
1089 if (++txq->write_idx == alx->tx_ringsz)
1090 txq->write_idx = 0;
1091 tpd = &txq->tpd[txq->write_idx];
1092
1093 tpd->word1 = first_tpd->word1;
1094
1095 maplen = skb_frag_size(frag);
1096 dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0,
1097 maplen, DMA_TO_DEVICE);
1098 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1099 goto err_dma;
1100 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1101 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1102
1103 tpd->adrl.addr = cpu_to_le64(dma);
1104 tpd->len = cpu_to_le16(maplen);
1105 }
1106
1107 /* last TPD, set EOP flag and store skb */
1108 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1109 txq->bufs[txq->write_idx].skb = skb;
1110
1111 if (++txq->write_idx == alx->tx_ringsz)
1112 txq->write_idx = 0;
1113
1114 return 0;
1115
1116err_dma:
1117 f = first_idx;
1118 while (f != txq->write_idx) {
1119 alx_free_txbuf(alx, f);
1120 if (++f == alx->tx_ringsz)
1121 f = 0;
1122 }
1123 return -ENOMEM;
1124}
1125
1126static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1127 struct net_device *netdev)
1128{
1129 struct alx_priv *alx = netdev_priv(netdev);
1130 struct alx_tx_queue *txq = &alx->txq;
1131 struct alx_txd *first;
1132 int tpdreq = skb_shinfo(skb)->nr_frags + 1;
1133
1134 if (alx_tpd_avail(alx) < tpdreq) {
1135 netif_stop_queue(alx->dev);
1136 goto drop;
1137 }
1138
1139 first = &txq->tpd[txq->write_idx];
1140 memset(first, 0, sizeof(*first));
1141
1142 if (alx_tx_csum(skb, first))
1143 goto drop;
1144
1145 if (alx_map_tx_skb(alx, skb) < 0)
1146 goto drop;
1147
1148 netdev_sent_queue(alx->dev, skb->len);
1149
1150 /* flush updates before updating hardware */
1151 wmb();
1152 alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx);
1153
1154 if (alx_tpd_avail(alx) < alx->tx_ringsz/8)
1155 netif_stop_queue(alx->dev);
1156
1157 return NETDEV_TX_OK;
1158
1159drop:
1160 dev_kfree_skb(skb);
1161 return NETDEV_TX_OK;
1162}
1163
1164static void alx_tx_timeout(struct net_device *dev)
1165{
1166 struct alx_priv *alx = netdev_priv(dev);
1167
1168 alx_schedule_reset(alx);
1169}
1170
1171static int alx_mdio_read(struct net_device *netdev,
1172 int prtad, int devad, u16 addr)
1173{
1174 struct alx_priv *alx = netdev_priv(netdev);
1175 struct alx_hw *hw = &alx->hw;
1176 u16 val;
1177 int err;
1178
1179 if (prtad != hw->mdio.prtad)
1180 return -EINVAL;
1181
1182 if (devad == MDIO_DEVAD_NONE)
1183 err = alx_read_phy_reg(hw, addr, &val);
1184 else
1185 err = alx_read_phy_ext(hw, devad, addr, &val);
1186
1187 if (err)
1188 return err;
1189 return val;
1190}
1191
1192static int alx_mdio_write(struct net_device *netdev,
1193 int prtad, int devad, u16 addr, u16 val)
1194{
1195 struct alx_priv *alx = netdev_priv(netdev);
1196 struct alx_hw *hw = &alx->hw;
1197
1198 if (prtad != hw->mdio.prtad)
1199 return -EINVAL;
1200
1201 if (devad == MDIO_DEVAD_NONE)
1202 return alx_write_phy_reg(hw, addr, val);
1203
1204 return alx_write_phy_ext(hw, devad, addr, val);
1205}
1206
1207static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1208{
1209 struct alx_priv *alx = netdev_priv(netdev);
1210
1211 if (!netif_running(netdev))
1212 return -EAGAIN;
1213
1214 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1215}
1216
1217#ifdef CONFIG_NET_POLL_CONTROLLER
1218static void alx_poll_controller(struct net_device *netdev)
1219{
1220 struct alx_priv *alx = netdev_priv(netdev);
1221
1222 if (alx->msi)
1223 alx_intr_msi(0, alx);
1224 else
1225 alx_intr_legacy(0, alx);
1226}
1227#endif
1228
1229static const struct net_device_ops alx_netdev_ops = {
1230 .ndo_open = alx_open,
1231 .ndo_stop = alx_stop,
1232 .ndo_start_xmit = alx_start_xmit,
1233 .ndo_set_rx_mode = alx_set_rx_mode,
1234 .ndo_validate_addr = eth_validate_addr,
1235 .ndo_set_mac_address = alx_set_mac_address,
1236 .ndo_change_mtu = alx_change_mtu,
1237 .ndo_do_ioctl = alx_ioctl,
1238 .ndo_tx_timeout = alx_tx_timeout,
1239 .ndo_fix_features = alx_fix_features,
1240#ifdef CONFIG_NET_POLL_CONTROLLER
1241 .ndo_poll_controller = alx_poll_controller,
1242#endif
1243};
1244
1245static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1246{
1247 struct net_device *netdev;
1248 struct alx_priv *alx;
1249 struct alx_hw *hw;
1250 bool phy_configured;
1251 int bars, pm_cap, err;
1252
1253 err = pci_enable_device_mem(pdev);
1254 if (err)
1255 return err;
1256
1257 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1258 * shared register for the high 32 bits, so only a single, aligned,
1259 * 4 GB physical address range can be used for descriptors.
1260 */
1261 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
1262 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
1263 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1264 } else {
1265 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1266 if (err) {
1267 err = dma_set_coherent_mask(&pdev->dev,
1268 DMA_BIT_MASK(32));
1269 if (err) {
1270 dev_err(&pdev->dev,
1271 "No usable DMA config, aborting\n");
1272 goto out_pci_disable;
1273 }
1274 }
1275 }
1276
1277 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1278 err = pci_request_selected_regions(pdev, bars, alx_drv_name);
1279 if (err) {
1280 dev_err(&pdev->dev,
1281 "pci_request_selected_regions failed(bars:%d)\n", bars);
1282 goto out_pci_disable;
1283 }
1284
1285 pci_enable_pcie_error_reporting(pdev);
1286 pci_set_master(pdev);
1287
1288 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1289 if (pm_cap == 0) {
1290 dev_err(&pdev->dev,
1291 "Can't find power management capability, aborting\n");
1292 err = -EIO;
1293 goto out_pci_release;
1294 }
1295
1296 err = pci_set_power_state(pdev, PCI_D0);
1297 if (err)
1298 goto out_pci_release;
1299
1300 netdev = alloc_etherdev(sizeof(*alx));
1301 if (!netdev) {
1302 err = -ENOMEM;
1303 goto out_pci_release;
1304 }
1305
1306 SET_NETDEV_DEV(netdev, &pdev->dev);
1307 alx = netdev_priv(netdev);
Maarten Lankhorst61b6f122013-07-11 15:53:21 +02001308 spin_lock_init(&alx->hw.mdio_lock);
1309 spin_lock_init(&alx->irq_lock);
Johannes Bergab69bde2013-06-17 22:44:02 +02001310 alx->dev = netdev;
1311 alx->hw.pdev = pdev;
1312 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1313 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1314 hw = &alx->hw;
1315 pci_set_drvdata(pdev, alx);
1316
1317 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1318 if (!hw->hw_addr) {
1319 dev_err(&pdev->dev, "cannot map device registers\n");
1320 err = -EIO;
1321 goto out_free_netdev;
1322 }
1323
1324 netdev->netdev_ops = &alx_netdev_ops;
1325 SET_ETHTOOL_OPS(netdev, &alx_ethtool_ops);
1326 netdev->irq = pdev->irq;
1327 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1328
1329 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1330 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1331
1332 err = alx_init_sw(alx);
1333 if (err) {
1334 dev_err(&pdev->dev, "net device private data init failed\n");
1335 goto out_unmap;
1336 }
1337
1338 alx_reset_pcie(hw);
1339
1340 phy_configured = alx_phy_configured(hw);
1341
1342 if (!phy_configured)
1343 alx_reset_phy(hw);
1344
1345 err = alx_reset_mac(hw);
1346 if (err) {
1347 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1348 goto out_unmap;
1349 }
1350
1351 /* setup link to put it in a known good starting state */
1352 if (!phy_configured) {
1353 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1354 if (err) {
1355 dev_err(&pdev->dev,
1356 "failed to configure PHY speed/duplex (err=%d)\n",
1357 err);
1358 goto out_unmap;
1359 }
1360 }
1361
1362 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
1363
1364 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1365 dev_warn(&pdev->dev,
1366 "Invalid permanent address programmed, using random one\n");
1367 eth_hw_addr_random(netdev);
1368 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1369 }
1370
1371 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1372 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
1373 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1374
1375 hw->mdio.prtad = 0;
1376 hw->mdio.mmds = 0;
1377 hw->mdio.dev = netdev;
1378 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1379 MDIO_SUPPORTS_C22 |
1380 MDIO_EMULATE_C22;
1381 hw->mdio.mdio_read = alx_mdio_read;
1382 hw->mdio.mdio_write = alx_mdio_write;
1383
1384 if (!alx_get_phy_info(hw)) {
1385 dev_err(&pdev->dev, "failed to identify PHY\n");
1386 err = -EIO;
1387 goto out_unmap;
1388 }
1389
1390 INIT_WORK(&alx->link_check_wk, alx_link_check);
1391 INIT_WORK(&alx->reset_wk, alx_reset);
Johannes Bergab69bde2013-06-17 22:44:02 +02001392 netif_carrier_off(netdev);
1393
1394 err = register_netdev(netdev);
1395 if (err) {
1396 dev_err(&pdev->dev, "register netdevice failed\n");
1397 goto out_unmap;
1398 }
1399
1400 device_set_wakeup_enable(&pdev->dev, hw->sleep_ctrl);
1401
1402 netdev_info(netdev,
1403 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1404 netdev->dev_addr);
1405
1406 return 0;
1407
1408out_unmap:
1409 iounmap(hw->hw_addr);
1410out_free_netdev:
1411 free_netdev(netdev);
1412out_pci_release:
1413 pci_release_selected_regions(pdev, bars);
1414out_pci_disable:
1415 pci_disable_device(pdev);
1416 return err;
1417}
1418
1419static void alx_remove(struct pci_dev *pdev)
1420{
1421 struct alx_priv *alx = pci_get_drvdata(pdev);
1422 struct alx_hw *hw = &alx->hw;
1423
1424 cancel_work_sync(&alx->link_check_wk);
1425 cancel_work_sync(&alx->reset_wk);
1426
1427 /* restore permanent mac address */
1428 alx_set_macaddr(hw, hw->perm_addr);
1429
1430 unregister_netdev(alx->dev);
1431 iounmap(hw->hw_addr);
1432 pci_release_selected_regions(pdev,
1433 pci_select_bars(pdev, IORESOURCE_MEM));
1434
1435 pci_disable_pcie_error_reporting(pdev);
1436 pci_disable_device(pdev);
1437 pci_set_drvdata(pdev, NULL);
1438
1439 free_netdev(alx->dev);
1440}
1441
1442#ifdef CONFIG_PM_SLEEP
1443static int alx_suspend(struct device *dev)
1444{
1445 struct pci_dev *pdev = to_pci_dev(dev);
1446 int err;
1447 bool wol_en;
1448
1449 err = __alx_shutdown(pdev, &wol_en);
1450 if (err) {
1451 dev_err(&pdev->dev, "shutdown fail in suspend %d\n", err);
1452 return err;
1453 }
1454
1455 if (wol_en) {
1456 pci_prepare_to_sleep(pdev);
1457 } else {
1458 pci_wake_from_d3(pdev, false);
1459 pci_set_power_state(pdev, PCI_D3hot);
1460 }
1461
1462 return 0;
1463}
1464
1465static int alx_resume(struct device *dev)
1466{
1467 struct pci_dev *pdev = to_pci_dev(dev);
1468 struct alx_priv *alx = pci_get_drvdata(pdev);
1469 struct net_device *netdev = alx->dev;
1470 struct alx_hw *hw = &alx->hw;
1471 int err;
1472
1473 pci_set_power_state(pdev, PCI_D0);
1474 pci_restore_state(pdev);
1475 pci_save_state(pdev);
1476
1477 pci_enable_wake(pdev, PCI_D3hot, 0);
1478 pci_enable_wake(pdev, PCI_D3cold, 0);
1479
1480 hw->link_speed = SPEED_UNKNOWN;
1481 alx->int_mask = ALX_ISR_MISC;
1482
1483 alx_reset_pcie(hw);
1484 alx_reset_phy(hw);
1485
1486 err = alx_reset_mac(hw);
1487 if (err) {
1488 netif_err(alx, hw, alx->dev,
1489 "resume:reset_mac fail %d\n", err);
1490 return -EIO;
1491 }
1492
1493 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1494 if (err) {
1495 netif_err(alx, hw, alx->dev,
1496 "resume:setup_speed_duplex fail %d\n", err);
1497 return -EIO;
1498 }
1499
1500 if (netif_running(netdev)) {
1501 err = __alx_open(alx, true);
1502 if (err)
1503 return err;
1504 }
1505
1506 netif_device_attach(netdev);
1507
1508 return err;
1509}
1510#endif
1511
1512static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1513 pci_channel_state_t state)
1514{
1515 struct alx_priv *alx = pci_get_drvdata(pdev);
1516 struct net_device *netdev = alx->dev;
1517 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1518
1519 dev_info(&pdev->dev, "pci error detected\n");
1520
1521 rtnl_lock();
1522
1523 if (netif_running(netdev)) {
1524 netif_device_detach(netdev);
1525 alx_halt(alx);
1526 }
1527
1528 if (state == pci_channel_io_perm_failure)
1529 rc = PCI_ERS_RESULT_DISCONNECT;
1530 else
1531 pci_disable_device(pdev);
1532
1533 rtnl_unlock();
1534
1535 return rc;
1536}
1537
1538static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1539{
1540 struct alx_priv *alx = pci_get_drvdata(pdev);
1541 struct alx_hw *hw = &alx->hw;
1542 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1543
1544 dev_info(&pdev->dev, "pci error slot reset\n");
1545
1546 rtnl_lock();
1547
1548 if (pci_enable_device(pdev)) {
1549 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1550 goto out;
1551 }
1552
1553 pci_set_master(pdev);
1554 pci_enable_wake(pdev, PCI_D3hot, 0);
1555 pci_enable_wake(pdev, PCI_D3cold, 0);
1556
1557 alx_reset_pcie(hw);
1558 if (!alx_reset_mac(hw))
1559 rc = PCI_ERS_RESULT_RECOVERED;
1560out:
1561 pci_cleanup_aer_uncorrect_error_status(pdev);
1562
1563 rtnl_unlock();
1564
1565 return rc;
1566}
1567
1568static void alx_pci_error_resume(struct pci_dev *pdev)
1569{
1570 struct alx_priv *alx = pci_get_drvdata(pdev);
1571 struct net_device *netdev = alx->dev;
1572
1573 dev_info(&pdev->dev, "pci error resume\n");
1574
1575 rtnl_lock();
1576
1577 if (netif_running(netdev)) {
1578 alx_activate(alx);
1579 netif_device_attach(netdev);
1580 }
1581
1582 rtnl_unlock();
1583}
1584
1585static const struct pci_error_handlers alx_err_handlers = {
1586 .error_detected = alx_pci_error_detected,
1587 .slot_reset = alx_pci_error_slot_reset,
1588 .resume = alx_pci_error_resume,
1589};
1590
1591#ifdef CONFIG_PM_SLEEP
1592static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1593#define ALX_PM_OPS (&alx_pm_ops)
1594#else
1595#define ALX_PM_OPS NULL
1596#endif
1597
1598static DEFINE_PCI_DEVICE_TABLE(alx_pci_tbl) = {
1599 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
1600 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1601 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
1602 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1603 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
1604 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1605 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
1606 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
1607 {}
1608};
1609
1610static struct pci_driver alx_driver = {
1611 .name = alx_drv_name,
1612 .id_table = alx_pci_tbl,
1613 .probe = alx_probe,
1614 .remove = alx_remove,
1615 .shutdown = alx_shutdown,
1616 .err_handler = &alx_err_handlers,
1617 .driver.pm = ALX_PM_OPS,
1618};
1619
1620module_pci_driver(alx_driver);
1621MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
1622MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
1623MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
1624MODULE_DESCRIPTION(
1625 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
1626MODULE_LICENSE("GPL");