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Wei WANGff984e52012-10-29 13:49:38 +08001/* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
Wei WANG433e0752012-11-20 11:24:44 +080024#include <linux/slab.h>
Wei WANGff984e52012-10-29 13:49:38 +080025#include <linux/highmem.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/sd.h>
31#include <linux/mmc/card.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35/* SD Tuning Data Structure
36 * Record continuous timing phase path
37 */
38struct timing_phase_path {
39 int start;
40 int end;
41 int mid;
42 int len;
43};
44
45struct realtek_pci_sdmmc {
46 struct platform_device *pdev;
47 struct rtsx_pcr *pcr;
48 struct mmc_host *mmc;
49 struct mmc_request *mrq;
50
51 struct mutex host_mutex;
52
53 u8 ssc_depth;
54 unsigned int clock;
55 bool vpclk;
56 bool double_clk;
57 bool eject;
58 bool initial_mode;
59 bool ddr_mode;
Wei WANGd88691b2013-03-08 15:05:57 +080060 int power_state;
61#define SDMMC_POWER_ON 1
62#define SDMMC_POWER_OFF 0
Wei WANGff984e52012-10-29 13:49:38 +080063};
64
65static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
66{
67 return &(host->pdev->dev);
68}
69
70static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
71{
72 rtsx_pci_write_register(host->pcr, CARD_STOP,
73 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
74}
75
76#ifdef DEBUG
77static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
78{
79 struct rtsx_pcr *pcr = host->pcr;
80 u16 i;
81 u8 *ptr;
82
83 /* Print SD host internal registers */
84 rtsx_pci_init_cmd(pcr);
85 for (i = 0xFDA0; i <= 0xFDAE; i++)
86 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
87 for (i = 0xFD52; i <= 0xFD69; i++)
88 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
89 rtsx_pci_send_cmd(pcr, 100);
90
91 ptr = rtsx_pci_get_cmd_data(pcr);
92 for (i = 0xFDA0; i <= 0xFDAE; i++)
93 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
94 for (i = 0xFD52; i <= 0xFD69; i++)
95 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
96}
97#else
98#define sd_print_debug_regs(host)
99#endif /* DEBUG */
100
101static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
102 u8 *buf, int buf_len, int timeout)
103{
104 struct rtsx_pcr *pcr = host->pcr;
105 int err, i;
106 u8 trans_mode;
107
108 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
109
110 if (!buf)
111 buf_len = 0;
112
113 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
114 trans_mode = SD_TM_AUTO_TUNING;
115 else
116 trans_mode = SD_TM_NORMAL_READ;
117
118 rtsx_pci_init_cmd(pcr);
119
120 for (i = 0; i < 5; i++)
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
122
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
125 0xFF, (u8)(byte_cnt >> 8));
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
128
129 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
130 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
131 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
132 if (trans_mode != SD_TM_AUTO_TUNING)
133 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
134 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
135
136 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
137 0xFF, trans_mode | SD_TRANSFER_START);
138 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
139 SD_TRANSFER_END, SD_TRANSFER_END);
140
141 err = rtsx_pci_send_cmd(pcr, timeout);
142 if (err < 0) {
143 sd_print_debug_regs(host);
144 dev_dbg(sdmmc_dev(host),
145 "rtsx_pci_send_cmd fail (err = %d)\n", err);
146 return err;
147 }
148
149 if (buf && buf_len) {
150 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
151 if (err < 0) {
152 dev_dbg(sdmmc_dev(host),
153 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
154 return err;
155 }
156 }
157
158 return 0;
159}
160
161static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
162 u8 *buf, int buf_len, int timeout)
163{
164 struct rtsx_pcr *pcr = host->pcr;
165 int err, i;
166 u8 trans_mode;
167
168 if (!buf)
169 buf_len = 0;
170
171 if (buf && buf_len) {
172 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
173 if (err < 0) {
174 dev_dbg(sdmmc_dev(host),
175 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
176 return err;
177 }
178 }
179
180 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
181 rtsx_pci_init_cmd(pcr);
182
183 if (cmd) {
184 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
185 cmd[0] - 0x40);
186
187 for (i = 0; i < 5; i++)
188 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
189 SD_CMD0 + i, 0xFF, cmd[i]);
190 }
191
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
194 0xFF, (u8)(byte_cnt >> 8));
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
197
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
199 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
200 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
201
202 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
203 trans_mode | SD_TRANSFER_START);
204 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
205 SD_TRANSFER_END, SD_TRANSFER_END);
206
207 err = rtsx_pci_send_cmd(pcr, timeout);
208 if (err < 0) {
209 sd_print_debug_regs(host);
210 dev_dbg(sdmmc_dev(host),
211 "rtsx_pci_send_cmd fail (err = %d)\n", err);
212 return err;
213 }
214
215 return 0;
216}
217
218static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
219 struct mmc_command *cmd)
220{
221 struct rtsx_pcr *pcr = host->pcr;
222 u8 cmd_idx = (u8)cmd->opcode;
223 u32 arg = cmd->arg;
224 int err = 0;
225 int timeout = 100;
226 int i;
227 u8 *ptr;
228 int stat_idx = 0;
229 u8 rsp_type;
230 int rsp_len = 5;
231
232 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
233 __func__, cmd_idx, arg);
234
235 /* Response type:
236 * R0
237 * R1, R5, R6, R7
238 * R1b
239 * R2
240 * R3, R4
241 */
242 switch (mmc_resp_type(cmd)) {
243 case MMC_RSP_NONE:
244 rsp_type = SD_RSP_TYPE_R0;
245 rsp_len = 0;
246 break;
247 case MMC_RSP_R1:
248 rsp_type = SD_RSP_TYPE_R1;
249 break;
Micky Ching8ccd5df2014-03-27 13:35:04 +0800250 case MMC_RSP_R1 & ~MMC_RSP_CRC:
251 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
252 break;
Wei WANGff984e52012-10-29 13:49:38 +0800253 case MMC_RSP_R1B:
254 rsp_type = SD_RSP_TYPE_R1b;
255 break;
256 case MMC_RSP_R2:
257 rsp_type = SD_RSP_TYPE_R2;
258 rsp_len = 16;
259 break;
260 case MMC_RSP_R3:
261 rsp_type = SD_RSP_TYPE_R3;
262 break;
263 default:
264 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
265 err = -EINVAL;
266 goto out;
267 }
268
269 if (rsp_type == SD_RSP_TYPE_R1b)
270 timeout = 3000;
271
272 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
273 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
274 0xFF, SD_CLK_TOGGLE_EN);
275 if (err < 0)
276 goto out;
277 }
278
279 rtsx_pci_init_cmd(pcr);
280
281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
285 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
286
287 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
288 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
289 0x01, PINGPONG_BUFFER);
290 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
291 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
292 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
293 SD_TRANSFER_END | SD_STAT_IDLE,
294 SD_TRANSFER_END | SD_STAT_IDLE);
295
296 if (rsp_type == SD_RSP_TYPE_R2) {
297 /* Read data from ping-pong buffer */
298 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
299 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
300 stat_idx = 16;
301 } else if (rsp_type != SD_RSP_TYPE_R0) {
302 /* Read data from SD_CMDx registers */
303 for (i = SD_CMD0; i <= SD_CMD4; i++)
304 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
305 stat_idx = 5;
306 }
307
308 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
309
310 err = rtsx_pci_send_cmd(pcr, timeout);
311 if (err < 0) {
312 sd_print_debug_regs(host);
313 sd_clear_error(host);
314 dev_dbg(sdmmc_dev(host),
315 "rtsx_pci_send_cmd error (err = %d)\n", err);
316 goto out;
317 }
318
319 if (rsp_type == SD_RSP_TYPE_R0) {
320 err = 0;
321 goto out;
322 }
323
324 /* Eliminate returned value of CHECK_REG_CMD */
325 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
326
327 /* Check (Start,Transmission) bit of Response */
328 if ((ptr[0] & 0xC0) != 0) {
329 err = -EILSEQ;
330 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
331 goto out;
332 }
333
334 /* Check CRC7 */
335 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
336 if (ptr[stat_idx] & SD_CRC7_ERR) {
337 err = -EILSEQ;
338 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
339 goto out;
340 }
341 }
342
343 if (rsp_type == SD_RSP_TYPE_R2) {
Roger Tsengb6e03bb2014-08-15 14:06:00 +0800344 /*
345 * The controller offloads the last byte {CRC-7, end bit 1'b1}
346 * of response type R2. Assign dummy CRC, 0, and end bit to the
347 * byte(ptr[16], goes into the LSB of resp[3] later).
348 */
349 ptr[16] = 1;
350
Wei WANGff984e52012-10-29 13:49:38 +0800351 for (i = 0; i < 4; i++) {
352 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
353 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
354 i, cmd->resp[i]);
355 }
356 } else {
357 cmd->resp[0] = get_unaligned_be32(ptr + 1);
358 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
359 cmd->resp[0]);
360 }
361
362out:
363 cmd->error = err;
364}
365
366static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
367{
368 struct rtsx_pcr *pcr = host->pcr;
369 struct mmc_host *mmc = host->mmc;
370 struct mmc_card *card = mmc->card;
371 struct mmc_data *data = mrq->data;
372 int uhs = mmc_sd_card_uhs(card);
373 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
374 u8 cfg2, trans_mode;
375 int err;
376 size_t data_len = data->blksz * data->blocks;
377
378 if (read) {
379 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
380 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
381 trans_mode = SD_TM_AUTO_READ_3;
382 } else {
383 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
384 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
385 trans_mode = SD_TM_AUTO_WRITE_3;
386 }
387
388 if (!uhs)
389 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
390
391 rtsx_pci_init_cmd(pcr);
392
393 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
394 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
395 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
396 0xFF, (u8)data->blocks);
397 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
398 0xFF, (u8)(data->blocks >> 8));
Wei WANGff984e52012-10-29 13:49:38 +0800399
400 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
401 DMA_DONE_INT, DMA_DONE_INT);
402 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
403 0xFF, (u8)(data_len >> 24));
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
405 0xFF, (u8)(data_len >> 16));
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
407 0xFF, (u8)(data_len >> 8));
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
409 if (read) {
410 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
411 0x03 | DMA_PACK_SIZE_MASK,
412 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
413 } else {
414 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
415 0x03 | DMA_PACK_SIZE_MASK,
416 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
417 }
418
419 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
420 0x01, RING_BUFFER);
421
Wei WANG38d324df2012-11-20 11:24:36 +0800422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
Wei WANGff984e52012-10-29 13:49:38 +0800423 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
424 trans_mode | SD_TRANSFER_START);
425 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
426 SD_TRANSFER_END, SD_TRANSFER_END);
427
428 rtsx_pci_send_cmd_no_wait(pcr);
429
430 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
431 if (err < 0) {
432 sd_clear_error(host);
433 return err;
434 }
435
436 return 0;
437}
438
439static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
440{
441 rtsx_pci_write_register(host->pcr, SD_CFG1,
442 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
443}
444
445static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
446{
447 rtsx_pci_write_register(host->pcr, SD_CFG1,
448 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
449}
450
451static void sd_normal_rw(struct realtek_pci_sdmmc *host,
452 struct mmc_request *mrq)
453{
454 struct mmc_command *cmd = mrq->cmd;
455 struct mmc_data *data = mrq->data;
456 u8 _cmd[5], *buf;
457
458 _cmd[0] = 0x40 | (u8)cmd->opcode;
459 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
460
461 buf = kzalloc(data->blksz, GFP_NOIO);
462 if (!buf) {
463 cmd->error = -ENOMEM;
464 return;
465 }
466
467 if (data->flags & MMC_DATA_READ) {
468 if (host->initial_mode)
469 sd_disable_initial_mode(host);
470
471 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
472 data->blksz, 200);
473
474 if (host->initial_mode)
475 sd_enable_initial_mode(host);
476
477 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
478 } else {
479 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
480
481 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
482 data->blksz, 200);
483 }
484
485 kfree(buf);
486}
487
488static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point)
489{
490 struct rtsx_pcr *pcr = host->pcr;
491 int err;
492
493 dev_dbg(sdmmc_dev(host), "%s: sample_point = %d\n",
494 __func__, sample_point);
495
496 rtsx_pci_init_cmd(pcr);
497
498 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
499 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point);
500 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
501 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
502 PHASE_NOT_RESET, PHASE_NOT_RESET);
503 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
504 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
505
506 err = rtsx_pci_send_cmd(pcr, 100);
507 if (err < 0)
508 return err;
509
510 return 0;
511}
512
513static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
514{
515 struct timing_phase_path path[MAX_PHASE + 1];
516 int i, j, cont_path_cnt;
517 int new_block, max_len, final_path_idx;
518 u8 final_phase = 0xFF;
519
520 /* Parse phase_map, take it as a bit-ring */
521 cont_path_cnt = 0;
522 new_block = 1;
523 j = 0;
524 for (i = 0; i < MAX_PHASE + 1; i++) {
525 if (phase_map & (1 << i)) {
526 if (new_block) {
527 new_block = 0;
528 j = cont_path_cnt++;
529 path[j].start = i;
530 path[j].end = i;
531 } else {
532 path[j].end = i;
533 }
534 } else {
535 new_block = 1;
536 if (cont_path_cnt) {
537 /* Calculate path length and middle point */
538 int idx = cont_path_cnt - 1;
539 path[idx].len =
540 path[idx].end - path[idx].start + 1;
541 path[idx].mid =
542 path[idx].start + path[idx].len / 2;
543 }
544 }
545 }
546
547 if (cont_path_cnt == 0) {
548 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
549 goto finish;
550 } else {
551 /* Calculate last continuous path length and middle point */
552 int idx = cont_path_cnt - 1;
553 path[idx].len = path[idx].end - path[idx].start + 1;
554 path[idx].mid = path[idx].start + path[idx].len / 2;
555 }
556
557 /* Connect the first and last continuous paths if they are adjacent */
558 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
559 /* Using negative index */
560 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
561 path[0].len += path[cont_path_cnt - 1].len;
562 path[0].mid = path[0].start + path[0].len / 2;
563 /* Convert negative middle point index to positive one */
564 if (path[0].mid < 0)
565 path[0].mid += MAX_PHASE + 1;
566 cont_path_cnt--;
567 }
568
569 /* Choose the longest continuous phase path */
570 max_len = 0;
571 final_phase = 0;
572 final_path_idx = 0;
573 for (i = 0; i < cont_path_cnt; i++) {
574 if (path[i].len > max_len) {
575 max_len = path[i].len;
576 final_phase = (u8)path[i].mid;
577 final_path_idx = i;
578 }
579
580 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
581 i, path[i].start);
582 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
583 i, path[i].end);
584 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
585 i, path[i].len);
586 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
587 i, path[i].mid);
588 }
589
590finish:
591 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
592 return final_phase;
593}
594
595static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
596{
597 int err, i;
598 u8 val = 0;
599
600 for (i = 0; i < 100; i++) {
601 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
602 if (val & SD_DATA_IDLE)
603 return;
604
605 udelay(100);
606 }
607}
608
609static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
610 u8 opcode, u8 sample_point)
611{
612 int err;
613 u8 cmd[5] = {0};
614
615 err = sd_change_phase(host, sample_point);
616 if (err < 0)
617 return err;
618
619 cmd[0] = 0x40 | opcode;
620 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
621 if (err < 0) {
622 /* Wait till SD DATA IDLE */
623 sd_wait_data_idle(host);
624 sd_clear_error(host);
625 return err;
626 }
627
628 return 0;
629}
630
631static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
632 u8 opcode, u32 *phase_map)
633{
634 int err, i;
635 u32 raw_phase_map = 0;
636
637 for (i = MAX_PHASE; i >= 0; i--) {
638 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
639 if (err == 0)
640 raw_phase_map |= 1 << i;
641 }
642
643 if (phase_map)
644 *phase_map = raw_phase_map;
645
646 return 0;
647}
648
649static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
650{
651 int err, i;
652 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
653 u8 final_phase;
654
655 for (i = 0; i < RX_TUNING_CNT; i++) {
656 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
657 if (err < 0)
658 return err;
659
660 if (raw_phase_map[i] == 0)
661 break;
662 }
663
664 phase_map = 0xFFFFFFFF;
665 for (i = 0; i < RX_TUNING_CNT; i++) {
666 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
667 i, raw_phase_map[i]);
668 phase_map &= raw_phase_map[i];
669 }
670 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
671
672 if (phase_map) {
673 final_phase = sd_search_final_phase(host, phase_map);
674 if (final_phase == 0xFF)
675 return -EINVAL;
676
677 err = sd_change_phase(host, final_phase);
678 if (err < 0)
679 return err;
680 } else {
681 return -EINVAL;
682 }
683
684 return 0;
685}
686
687static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
688{
689 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
690 struct rtsx_pcr *pcr = host->pcr;
691 struct mmc_command *cmd = mrq->cmd;
692 struct mmc_data *data = mrq->data;
693 unsigned int data_size = 0;
Wei WANGc3481952013-02-08 15:24:27 +0800694 int err;
Wei WANGff984e52012-10-29 13:49:38 +0800695
696 if (host->eject) {
697 cmd->error = -ENOMEDIUM;
698 goto finish;
699 }
700
Wei WANGc3481952013-02-08 15:24:27 +0800701 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
702 if (err) {
703 cmd->error = err;
704 goto finish;
705 }
706
Wei WANGff984e52012-10-29 13:49:38 +0800707 mutex_lock(&pcr->pcr_mutex);
708
709 rtsx_pci_start_run(pcr);
710
711 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
712 host->initial_mode, host->double_clk, host->vpclk);
713 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
714 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
715 CARD_SHARE_MASK, CARD_SHARE_48_SD);
716
717 mutex_lock(&host->host_mutex);
718 host->mrq = mrq;
719 mutex_unlock(&host->host_mutex);
720
721 if (mrq->data)
722 data_size = data->blocks * data->blksz;
723
724 if (!data_size || mmc_op_multi(cmd->opcode) ||
725 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
726 (cmd->opcode == MMC_WRITE_BLOCK)) {
727 sd_send_cmd_get_rsp(host, cmd);
728
729 if (!cmd->error && data_size) {
730 sd_rw_multi(host, mrq);
731
732 if (mmc_op_multi(cmd->opcode) && mrq->stop)
733 sd_send_cmd_get_rsp(host, mrq->stop);
734 }
735 } else {
736 sd_normal_rw(host, mrq);
737 }
738
739 if (mrq->data) {
740 if (cmd->error || data->error)
741 data->bytes_xfered = 0;
742 else
743 data->bytes_xfered = data->blocks * data->blksz;
744 }
745
746 mutex_unlock(&pcr->pcr_mutex);
747
748finish:
749 if (cmd->error)
750 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
751
752 mutex_lock(&host->host_mutex);
753 host->mrq = NULL;
754 mutex_unlock(&host->host_mutex);
755
756 mmc_request_done(mmc, mrq);
757}
758
759static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
760 unsigned char bus_width)
761{
762 int err = 0;
763 u8 width[] = {
764 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
765 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
766 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
767 };
768
769 if (bus_width <= MMC_BUS_WIDTH_8)
770 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
771 0x03, width[bus_width]);
772
773 return err;
774}
775
776static int sd_power_on(struct realtek_pci_sdmmc *host)
777{
778 struct rtsx_pcr *pcr = host->pcr;
779 int err;
780
Wei WANGd88691b2013-03-08 15:05:57 +0800781 if (host->power_state == SDMMC_POWER_ON)
782 return 0;
783
Wei WANGff984e52012-10-29 13:49:38 +0800784 rtsx_pci_init_cmd(pcr);
785 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
786 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
787 CARD_SHARE_MASK, CARD_SHARE_48_SD);
788 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
789 SD_CLK_EN, SD_CLK_EN);
790 err = rtsx_pci_send_cmd(pcr, 100);
791 if (err < 0)
792 return err;
793
794 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
795 if (err < 0)
796 return err;
797
798 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
799 if (err < 0)
800 return err;
801
802 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
803 if (err < 0)
804 return err;
805
Wei WANGd88691b2013-03-08 15:05:57 +0800806 host->power_state = SDMMC_POWER_ON;
Wei WANGff984e52012-10-29 13:49:38 +0800807 return 0;
808}
809
810static int sd_power_off(struct realtek_pci_sdmmc *host)
811{
812 struct rtsx_pcr *pcr = host->pcr;
813 int err;
814
Wei WANGd88691b2013-03-08 15:05:57 +0800815 host->power_state = SDMMC_POWER_OFF;
816
Wei WANGff984e52012-10-29 13:49:38 +0800817 rtsx_pci_init_cmd(pcr);
818
819 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
820 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
821
822 err = rtsx_pci_send_cmd(pcr, 100);
823 if (err < 0)
824 return err;
825
826 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
827 if (err < 0)
828 return err;
829
830 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
831}
832
833static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
834 unsigned char power_mode)
835{
836 int err;
837
838 if (power_mode == MMC_POWER_OFF)
839 err = sd_power_off(host);
840 else
841 err = sd_power_on(host);
842
843 return err;
844}
845
846static int sd_set_timing(struct realtek_pci_sdmmc *host,
847 unsigned char timing, bool *ddr_mode)
848{
849 struct rtsx_pcr *pcr = host->pcr;
850 int err = 0;
851
852 *ddr_mode = false;
853
854 rtsx_pci_init_cmd(pcr);
855
856 switch (timing) {
857 case MMC_TIMING_UHS_SDR104:
858 case MMC_TIMING_UHS_SDR50:
859 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
860 0x0C | SD_ASYNC_FIFO_NOT_RST,
861 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
862 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
863 CLK_LOW_FREQ, CLK_LOW_FREQ);
864 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
865 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
866 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
867 break;
868
869 case MMC_TIMING_UHS_DDR50:
870 *ddr_mode = true;
871
872 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
873 0x0C | SD_ASYNC_FIFO_NOT_RST,
874 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
875 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
876 CLK_LOW_FREQ, CLK_LOW_FREQ);
877 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
878 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
879 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
880 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
881 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
882 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
883 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
884 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
885 break;
886
887 case MMC_TIMING_MMC_HS:
888 case MMC_TIMING_SD_HS:
889 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
890 0x0C, SD_20_MODE);
891 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
892 CLK_LOW_FREQ, CLK_LOW_FREQ);
893 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
894 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
896 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
897 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
898 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
899 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
900 break;
901
902 default:
903 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
904 SD_CFG1, 0x0C, SD_20_MODE);
905 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
906 CLK_LOW_FREQ, CLK_LOW_FREQ);
907 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
908 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
909 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
910 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
911 SD_PUSH_POINT_CTL, 0xFF, 0);
912 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
913 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
914 break;
915 }
916
917 err = rtsx_pci_send_cmd(pcr, 100);
918
919 return err;
920}
921
922static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
923{
924 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
925 struct rtsx_pcr *pcr = host->pcr;
926
927 if (host->eject)
928 return;
929
Wei WANGc3481952013-02-08 15:24:27 +0800930 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
931 return;
932
Wei WANGff984e52012-10-29 13:49:38 +0800933 mutex_lock(&pcr->pcr_mutex);
934
935 rtsx_pci_start_run(pcr);
936
937 sd_set_bus_width(host, ios->bus_width);
938 sd_set_power_mode(host, ios->power_mode);
939 sd_set_timing(host, ios->timing, &host->ddr_mode);
940
941 host->vpclk = false;
942 host->double_clk = true;
943
944 switch (ios->timing) {
945 case MMC_TIMING_UHS_SDR104:
946 case MMC_TIMING_UHS_SDR50:
947 host->ssc_depth = RTSX_SSC_DEPTH_2M;
948 host->vpclk = true;
949 host->double_clk = false;
950 break;
951 case MMC_TIMING_UHS_DDR50:
952 case MMC_TIMING_UHS_SDR25:
953 host->ssc_depth = RTSX_SSC_DEPTH_1M;
954 break;
955 default:
956 host->ssc_depth = RTSX_SSC_DEPTH_500K;
957 break;
958 }
959
960 host->initial_mode = (ios->clock <= 1000000) ? true : false;
961
962 host->clock = ios->clock;
963 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
964 host->initial_mode, host->double_clk, host->vpclk);
965
966 mutex_unlock(&pcr->pcr_mutex);
967}
968
969static int sdmmc_get_ro(struct mmc_host *mmc)
970{
971 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
972 struct rtsx_pcr *pcr = host->pcr;
973 int ro = 0;
974 u32 val;
975
976 if (host->eject)
977 return -ENOMEDIUM;
978
979 mutex_lock(&pcr->pcr_mutex);
980
981 rtsx_pci_start_run(pcr);
982
983 /* Check SD mechanical write-protect switch */
984 val = rtsx_pci_readl(pcr, RTSX_BIPR);
985 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
986 if (val & SD_WRITE_PROTECT)
987 ro = 1;
988
989 mutex_unlock(&pcr->pcr_mutex);
990
991 return ro;
992}
993
994static int sdmmc_get_cd(struct mmc_host *mmc)
995{
996 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
997 struct rtsx_pcr *pcr = host->pcr;
998 int cd = 0;
999 u32 val;
1000
1001 if (host->eject)
1002 return -ENOMEDIUM;
1003
1004 mutex_lock(&pcr->pcr_mutex);
1005
1006 rtsx_pci_start_run(pcr);
1007
1008 /* Check SD card detect */
1009 val = rtsx_pci_card_exist(pcr);
1010 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1011 if (val & SD_EXIST)
1012 cd = 1;
1013
1014 mutex_unlock(&pcr->pcr_mutex);
1015
1016 return cd;
1017}
1018
1019static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1020{
1021 struct rtsx_pcr *pcr = host->pcr;
1022 int err;
1023 u8 stat;
1024
1025 /* Reference to Signal Voltage Switch Sequence in SD spec.
1026 * Wait for a period of time so that the card can drive SD_CMD and
1027 * SD_DAT[3:0] to low after sending back CMD11 response.
1028 */
1029 mdelay(1);
1030
1031 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1032 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1033 * abort the voltage switch sequence;
1034 */
1035 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1036 if (err < 0)
1037 return err;
1038
1039 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1040 SD_DAT1_STATUS | SD_DAT0_STATUS))
1041 return -EINVAL;
1042
1043 /* Stop toggle SD clock */
1044 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1045 0xFF, SD_CLK_FORCE_STOP);
1046 if (err < 0)
1047 return err;
1048
1049 return 0;
1050}
1051
1052static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1053{
1054 struct rtsx_pcr *pcr = host->pcr;
1055 int err;
1056 u8 stat, mask, val;
1057
1058 /* Wait 1.8V output of voltage regulator in card stable */
1059 msleep(50);
1060
1061 /* Toggle SD clock again */
1062 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1063 if (err < 0)
1064 return err;
1065
1066 /* Wait for a period of time so that the card can drive
1067 * SD_DAT[3:0] to high at 1.8V
1068 */
1069 msleep(20);
1070
1071 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1072 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1073 if (err < 0)
1074 return err;
1075
1076 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1077 SD_DAT1_STATUS | SD_DAT0_STATUS;
1078 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1079 SD_DAT1_STATUS | SD_DAT0_STATUS;
1080 if ((stat & mask) != val) {
1081 dev_dbg(sdmmc_dev(host),
1082 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1083 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1084 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1085 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1086 return -EINVAL;
1087 }
1088
1089 return 0;
1090}
1091
Wei WANGff984e52012-10-29 13:49:38 +08001092static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1093{
1094 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1095 struct rtsx_pcr *pcr = host->pcr;
1096 int err = 0;
1097 u8 voltage;
1098
1099 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1100 __func__, ios->signal_voltage);
1101
1102 if (host->eject)
1103 return -ENOMEDIUM;
1104
Wei WANGc3481952013-02-08 15:24:27 +08001105 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1106 if (err)
1107 return err;
1108
Wei WANGff984e52012-10-29 13:49:38 +08001109 mutex_lock(&pcr->pcr_mutex);
1110
1111 rtsx_pci_start_run(pcr);
1112
1113 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
Wei WANGef85e732013-01-23 09:51:05 +08001114 voltage = OUTPUT_3V3;
Wei WANGff984e52012-10-29 13:49:38 +08001115 else
Wei WANGef85e732013-01-23 09:51:05 +08001116 voltage = OUTPUT_1V8;
Wei WANGff984e52012-10-29 13:49:38 +08001117
Wei WANGef85e732013-01-23 09:51:05 +08001118 if (voltage == OUTPUT_1V8) {
Wei WANGff984e52012-10-29 13:49:38 +08001119 err = sd_wait_voltage_stable_1(host);
1120 if (err < 0)
1121 goto out;
1122 }
1123
Wei WANGef85e732013-01-23 09:51:05 +08001124 err = rtsx_pci_switch_output_voltage(pcr, voltage);
Wei WANGff984e52012-10-29 13:49:38 +08001125 if (err < 0)
1126 goto out;
1127
Wei WANGef85e732013-01-23 09:51:05 +08001128 if (voltage == OUTPUT_1V8) {
Wei WANGff984e52012-10-29 13:49:38 +08001129 err = sd_wait_voltage_stable_2(host);
1130 if (err < 0)
1131 goto out;
1132 }
1133
1134 /* Stop toggle SD clock in idle */
1135 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1136 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1137
1138out:
1139 mutex_unlock(&pcr->pcr_mutex);
1140
1141 return err;
1142}
1143
1144static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1145{
1146 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1147 struct rtsx_pcr *pcr = host->pcr;
1148 int err = 0;
1149
1150 if (host->eject)
1151 return -ENOMEDIUM;
1152
Wei WANGc3481952013-02-08 15:24:27 +08001153 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1154 if (err)
1155 return err;
1156
Wei WANGff984e52012-10-29 13:49:38 +08001157 mutex_lock(&pcr->pcr_mutex);
1158
1159 rtsx_pci_start_run(pcr);
1160
1161 if (!host->ddr_mode)
1162 err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK);
1163
1164 mutex_unlock(&pcr->pcr_mutex);
1165
1166 return err;
1167}
1168
1169static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1170 .request = sdmmc_request,
1171 .set_ios = sdmmc_set_ios,
1172 .get_ro = sdmmc_get_ro,
1173 .get_cd = sdmmc_get_cd,
1174 .start_signal_voltage_switch = sdmmc_switch_voltage,
1175 .execute_tuning = sdmmc_execute_tuning,
1176};
1177
1178#ifdef CONFIG_PM
1179static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1180 pm_message_t state)
1181{
1182 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1183 struct mmc_host *mmc = host->mmc;
1184 int err;
1185
1186 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1187
1188 err = mmc_suspend_host(mmc);
1189 if (err)
1190 return err;
1191
1192 return 0;
1193}
1194
1195static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1196{
1197 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1198 struct mmc_host *mmc = host->mmc;
1199
1200 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1201
1202 return mmc_resume_host(mmc);
1203}
1204#else /* CONFIG_PM */
1205#define rtsx_pci_sdmmc_suspend NULL
1206#define rtsx_pci_sdmmc_resume NULL
1207#endif /* CONFIG_PM */
1208
1209static void init_extra_caps(struct realtek_pci_sdmmc *host)
1210{
1211 struct mmc_host *mmc = host->mmc;
1212 struct rtsx_pcr *pcr = host->pcr;
1213
1214 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1215
1216 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1217 mmc->caps |= MMC_CAP_UHS_SDR50;
1218 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1219 mmc->caps |= MMC_CAP_UHS_SDR104;
1220 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1221 mmc->caps |= MMC_CAP_UHS_DDR50;
1222 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1223 mmc->caps |= MMC_CAP_1_8V_DDR;
1224 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1225 mmc->caps |= MMC_CAP_8_BIT_DATA;
1226}
1227
1228static void realtek_init_host(struct realtek_pci_sdmmc *host)
1229{
1230 struct mmc_host *mmc = host->mmc;
1231
1232 mmc->f_min = 250000;
1233 mmc->f_max = 208000000;
1234 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1235 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1236 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1237 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1238 mmc->max_current_330 = 400;
1239 mmc->max_current_180 = 800;
1240 mmc->ops = &realtek_pci_sdmmc_ops;
1241
1242 init_extra_caps(host);
1243
1244 mmc->max_segs = 256;
1245 mmc->max_seg_size = 65536;
1246 mmc->max_blk_size = 512;
1247 mmc->max_blk_count = 65535;
1248 mmc->max_req_size = 524288;
1249}
1250
1251static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1252{
1253 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1254
1255 mmc_detect_change(host->mmc, 0);
1256}
1257
1258static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1259{
1260 struct mmc_host *mmc;
1261 struct realtek_pci_sdmmc *host;
1262 struct rtsx_pcr *pcr;
1263 struct pcr_handle *handle = pdev->dev.platform_data;
1264
1265 if (!handle)
1266 return -ENXIO;
1267
1268 pcr = handle->pcr;
1269 if (!pcr)
1270 return -ENXIO;
1271
1272 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1273
1274 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1275 if (!mmc)
1276 return -ENOMEM;
1277
1278 host = mmc_priv(mmc);
1279 host->pcr = pcr;
1280 host->mmc = mmc;
1281 host->pdev = pdev;
Wei WANGd88691b2013-03-08 15:05:57 +08001282 host->power_state = SDMMC_POWER_OFF;
Wei WANGff984e52012-10-29 13:49:38 +08001283 platform_set_drvdata(pdev, host);
1284 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1285 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1286
1287 mutex_init(&host->host_mutex);
1288
1289 realtek_init_host(host);
1290
1291 mmc_add_host(mmc);
1292
1293 return 0;
1294}
1295
1296static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1297{
1298 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1299 struct rtsx_pcr *pcr;
1300 struct mmc_host *mmc;
1301
1302 if (!host)
1303 return 0;
1304
1305 pcr = host->pcr;
1306 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1307 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1308 mmc = host->mmc;
1309 host->eject = true;
1310
1311 mutex_lock(&host->host_mutex);
1312 if (host->mrq) {
1313 dev_dbg(&(pdev->dev),
1314 "%s: Controller removed during transfer\n",
1315 mmc_hostname(mmc));
1316
1317 rtsx_pci_complete_unfinished_transfer(pcr);
1318
1319 host->mrq->cmd->error = -ENOMEDIUM;
1320 if (host->mrq->stop)
1321 host->mrq->stop->error = -ENOMEDIUM;
1322 mmc_request_done(mmc, host->mrq);
1323 }
1324 mutex_unlock(&host->host_mutex);
1325
1326 mmc_remove_host(mmc);
1327 mmc_free_host(mmc);
1328
1329 platform_set_drvdata(pdev, NULL);
1330
1331 dev_dbg(&(pdev->dev),
1332 ": Realtek PCI-E SDMMC controller has been removed\n");
1333
1334 return 0;
1335}
1336
1337static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1338 {
1339 .name = DRV_NAME_RTSX_PCI_SDMMC,
1340 }, {
1341 /* sentinel */
1342 }
1343};
1344MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1345
1346static struct platform_driver rtsx_pci_sdmmc_driver = {
1347 .probe = rtsx_pci_sdmmc_drv_probe,
1348 .remove = rtsx_pci_sdmmc_drv_remove,
1349 .id_table = rtsx_pci_sdmmc_ids,
1350 .suspend = rtsx_pci_sdmmc_suspend,
1351 .resume = rtsx_pci_sdmmc_resume,
1352 .driver = {
1353 .owner = THIS_MODULE,
1354 .name = DRV_NAME_RTSX_PCI_SDMMC,
1355 },
1356};
1357module_platform_driver(rtsx_pci_sdmmc_driver);
1358
1359MODULE_LICENSE("GPL");
1360MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1361MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");