blob: ebf8450a2a09cc21046bca6481c2175f465918f0 [file] [log] [blame]
Mika Westerbergd16a5aa2014-03-20 22:04:23 +08001/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
Alan Cox093e00b2014-04-18 19:17:40 +08009 * Author: Alan Cox <alan@linux.intel.com>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
Thierry Redinge0c86a32014-08-23 00:22:45 +020016#include <linux/io.h>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080017#include <linux/kernel.h>
18#include <linux/module.h>
Qipeng Zhaf080be22015-10-26 12:58:27 +020019#include <linux/pm_runtime.h>
qipeng.zha883e4d02015-11-17 17:20:15 +080020#include <linux/time.h>
Alan Cox093e00b2014-04-18 19:17:40 +080021
Andy Shevchenkoc558e392014-08-19 19:17:35 +030022#include "pwm-lpss.h"
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080023
24#define PWM 0x00000000
25#define PWM_ENABLE BIT(31)
26#define PWM_SW_UPDATE BIT(30)
27#define PWM_BASE_UNIT_SHIFT 8
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080028#define PWM_ON_TIME_DIV_MASK 0x000000ff
29#define PWM_DIVISION_CORRECTION 0x2
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080030
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030031/* Size of each PWM register space if multiple */
32#define PWM_SIZE 0x400
33
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080034struct pwm_lpss_chip {
35 struct pwm_chip chip;
36 void __iomem *regs;
qipeng.zha883e4d02015-11-17 17:20:15 +080037 const struct pwm_lpss_boardinfo *info;
Alan Cox093e00b2014-04-18 19:17:40 +080038};
39
Alan Cox093e00b2014-04-18 19:17:40 +080040/* BayTrail */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030041const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030042 .clk_rate = 25000000,
43 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080044 .base_unit_bits = 16,
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080045};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030046EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080047
Alan Cox373c5782014-08-19 17:18:29 +030048/* Braswell */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030049const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030050 .clk_rate = 19200000,
51 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080052 .base_unit_bits = 16,
Alan Cox373c5782014-08-19 17:18:29 +030053};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030054EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
Alan Cox373c5782014-08-19 17:18:29 +030055
Mika Westerberg87219cb2015-10-20 16:53:06 +030056/* Broxton */
57const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
58 .clk_rate = 19200000,
59 .npwm = 4,
qipeng.zha883e4d02015-11-17 17:20:15 +080060 .base_unit_bits = 22,
Mika Westerberg87219cb2015-10-20 16:53:06 +030061};
62EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
63
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080064static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_lpss_chip, chip);
67}
68
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030069static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
70{
71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
72
73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
74}
75
76static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
77{
78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
79
80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
81}
82
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080083static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
84 int duty_ns, int period_ns)
85{
86 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
87 u8 on_time_div;
qipeng.zha883e4d02015-11-17 17:20:15 +080088 unsigned long c, base_unit_range;
89 unsigned long long base_unit, freq = NSEC_PER_SEC;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080090 u32 ctrl;
91
92 do_div(freq, period_ns);
93
qipeng.zha883e4d02015-11-17 17:20:15 +080094 /*
95 * The equation is:
96 * base_unit = ((freq / c) * base_unit_range) + correction
97 */
98 base_unit_range = BIT(lpwm->info->base_unit_bits);
99 base_unit = freq * base_unit_range;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800100
qipeng.zha883e4d02015-11-17 17:20:15 +0800101 c = lpwm->info->clk_rate;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800102 if (!c)
103 return -EINVAL;
104
105 do_div(base_unit, c);
106 base_unit += PWM_DIVISION_CORRECTION;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800107
108 if (duty_ns <= 0)
109 duty_ns = 1;
110 on_time_div = 255 - (255 * duty_ns / period_ns);
111
Qipeng Zhaf080be22015-10-26 12:58:27 +0200112 pm_runtime_get_sync(chip->dev);
113
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300114 ctrl = pwm_lpss_read(pwm);
qipeng.zha883e4d02015-11-17 17:20:15 +0800115 ctrl &= ~PWM_ON_TIME_DIV_MASK;
116 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
117 base_unit &= (base_unit_range - 1);
118 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800119 ctrl |= on_time_div;
120 /* request PWM to update on next cycle */
121 ctrl |= PWM_SW_UPDATE;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300122 pwm_lpss_write(pwm, ctrl);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800123
Qipeng Zhaf080be22015-10-26 12:58:27 +0200124 pm_runtime_put(chip->dev);
125
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800126 return 0;
127}
128
129static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
130{
Qipeng Zhaf080be22015-10-26 12:58:27 +0200131 pm_runtime_get_sync(chip->dev);
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300132 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800133 return 0;
134}
135
136static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
137{
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300138 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
Qipeng Zhaf080be22015-10-26 12:58:27 +0200139 pm_runtime_put(chip->dev);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800140}
141
142static const struct pwm_ops pwm_lpss_ops = {
143 .config = pwm_lpss_config,
144 .enable = pwm_lpss_enable,
145 .disable = pwm_lpss_disable,
146 .owner = THIS_MODULE,
147};
148
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300149struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
150 const struct pwm_lpss_boardinfo *info)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800151{
152 struct pwm_lpss_chip *lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800153 int ret;
154
Alan Cox093e00b2014-04-18 19:17:40 +0800155 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800156 if (!lpwm)
Alan Cox093e00b2014-04-18 19:17:40 +0800157 return ERR_PTR(-ENOMEM);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800158
Alan Cox093e00b2014-04-18 19:17:40 +0800159 lpwm->regs = devm_ioremap_resource(dev, r);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800160 if (IS_ERR(lpwm->regs))
Thierry Reding89c03392014-05-07 10:27:57 +0200161 return ERR_CAST(lpwm->regs);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800162
qipeng.zha883e4d02015-11-17 17:20:15 +0800163 lpwm->info = info;
Alan Cox093e00b2014-04-18 19:17:40 +0800164 lpwm->chip.dev = dev;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800165 lpwm->chip.ops = &pwm_lpss_ops;
166 lpwm->chip.base = -1;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300167 lpwm->chip.npwm = info->npwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800168
169 ret = pwmchip_add(&lpwm->chip);
170 if (ret) {
Alan Cox093e00b2014-04-18 19:17:40 +0800171 dev_err(dev, "failed to add PWM chip: %d\n", ret);
172 return ERR_PTR(ret);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800173 }
174
Alan Cox093e00b2014-04-18 19:17:40 +0800175 return lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800176}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300177EXPORT_SYMBOL_GPL(pwm_lpss_probe);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800178
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300179int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800180{
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800181 return pwmchip_remove(&lpwm->chip);
182}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300183EXPORT_SYMBOL_GPL(pwm_lpss_remove);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800184
185MODULE_DESCRIPTION("PWM driver for Intel LPSS");
186MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
187MODULE_LICENSE("GPL v2");