Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Intel Low Power Subsystem PWM controller driver |
| 3 | * |
| 4 | * Copyright (C) 2014, Intel Corporation |
| 5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
| 6 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> |
| 7 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> |
| 8 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 9 | * Author: Alan Cox <alan@linux.intel.com> |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Thierry Reding | e0c86a3 | 2014-08-23 00:22:45 +0200 | [diff] [blame] | 16 | #include <linux/io.h> |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 19 | #include <linux/pm_runtime.h> |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 20 | #include <linux/time.h> |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 21 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 22 | #include "pwm-lpss.h" |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 23 | |
| 24 | #define PWM 0x00000000 |
| 25 | #define PWM_ENABLE BIT(31) |
| 26 | #define PWM_SW_UPDATE BIT(30) |
| 27 | #define PWM_BASE_UNIT_SHIFT 8 |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 28 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
| 29 | #define PWM_DIVISION_CORRECTION 0x2 |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 30 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 31 | /* Size of each PWM register space if multiple */ |
| 32 | #define PWM_SIZE 0x400 |
| 33 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 34 | struct pwm_lpss_chip { |
| 35 | struct pwm_chip chip; |
| 36 | void __iomem *regs; |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 37 | const struct pwm_lpss_boardinfo *info; |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 38 | }; |
| 39 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 40 | /* BayTrail */ |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 41 | const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 42 | .clk_rate = 25000000, |
| 43 | .npwm = 1, |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 44 | .base_unit_bits = 16, |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 45 | }; |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 46 | EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 47 | |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 48 | /* Braswell */ |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 49 | const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 50 | .clk_rate = 19200000, |
| 51 | .npwm = 1, |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 52 | .base_unit_bits = 16, |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 53 | }; |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 54 | EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 55 | |
Mika Westerberg | 87219cb | 2015-10-20 16:53:06 +0300 | [diff] [blame] | 56 | /* Broxton */ |
| 57 | const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = { |
| 58 | .clk_rate = 19200000, |
| 59 | .npwm = 4, |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 60 | .base_unit_bits = 22, |
Mika Westerberg | 87219cb | 2015-10-20 16:53:06 +0300 | [diff] [blame] | 61 | }; |
| 62 | EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info); |
| 63 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 64 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
| 65 | { |
| 66 | return container_of(chip, struct pwm_lpss_chip, chip); |
| 67 | } |
| 68 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 69 | static inline u32 pwm_lpss_read(const struct pwm_device *pwm) |
| 70 | { |
| 71 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
| 72 | |
| 73 | return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); |
| 74 | } |
| 75 | |
| 76 | static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) |
| 77 | { |
| 78 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
| 79 | |
| 80 | writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); |
| 81 | } |
| 82 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 83 | static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 84 | int duty_ns, int period_ns) |
| 85 | { |
| 86 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
| 87 | u8 on_time_div; |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 88 | unsigned long c, base_unit_range; |
| 89 | unsigned long long base_unit, freq = NSEC_PER_SEC; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 90 | u32 ctrl; |
| 91 | |
| 92 | do_div(freq, period_ns); |
| 93 | |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 94 | /* |
| 95 | * The equation is: |
| 96 | * base_unit = ((freq / c) * base_unit_range) + correction |
| 97 | */ |
| 98 | base_unit_range = BIT(lpwm->info->base_unit_bits); |
| 99 | base_unit = freq * base_unit_range; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 100 | |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 101 | c = lpwm->info->clk_rate; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 102 | if (!c) |
| 103 | return -EINVAL; |
| 104 | |
| 105 | do_div(base_unit, c); |
| 106 | base_unit += PWM_DIVISION_CORRECTION; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 107 | |
| 108 | if (duty_ns <= 0) |
| 109 | duty_ns = 1; |
| 110 | on_time_div = 255 - (255 * duty_ns / period_ns); |
| 111 | |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 112 | pm_runtime_get_sync(chip->dev); |
| 113 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 114 | ctrl = pwm_lpss_read(pwm); |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 115 | ctrl &= ~PWM_ON_TIME_DIV_MASK; |
| 116 | ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); |
| 117 | base_unit &= (base_unit_range - 1); |
| 118 | ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 119 | ctrl |= on_time_div; |
| 120 | /* request PWM to update on next cycle */ |
| 121 | ctrl |= PWM_SW_UPDATE; |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 122 | pwm_lpss_write(pwm, ctrl); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 123 | |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 124 | pm_runtime_put(chip->dev); |
| 125 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 130 | { |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 131 | pm_runtime_get_sync(chip->dev); |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 132 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 137 | { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 138 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 139 | pm_runtime_put(chip->dev); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static const struct pwm_ops pwm_lpss_ops = { |
| 143 | .config = pwm_lpss_config, |
| 144 | .enable = pwm_lpss_enable, |
| 145 | .disable = pwm_lpss_disable, |
| 146 | .owner = THIS_MODULE, |
| 147 | }; |
| 148 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 149 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
| 150 | const struct pwm_lpss_boardinfo *info) |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 151 | { |
| 152 | struct pwm_lpss_chip *lpwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 153 | int ret; |
| 154 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 155 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 156 | if (!lpwm) |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 157 | return ERR_PTR(-ENOMEM); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 158 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 159 | lpwm->regs = devm_ioremap_resource(dev, r); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 160 | if (IS_ERR(lpwm->regs)) |
Thierry Reding | 89c0339 | 2014-05-07 10:27:57 +0200 | [diff] [blame] | 161 | return ERR_CAST(lpwm->regs); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 162 | |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame^] | 163 | lpwm->info = info; |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 164 | lpwm->chip.dev = dev; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 165 | lpwm->chip.ops = &pwm_lpss_ops; |
| 166 | lpwm->chip.base = -1; |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 167 | lpwm->chip.npwm = info->npwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 168 | |
| 169 | ret = pwmchip_add(&lpwm->chip); |
| 170 | if (ret) { |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 171 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
| 172 | return ERR_PTR(ret); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 173 | } |
| 174 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 175 | return lpwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 176 | } |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 177 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 178 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 179 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 180 | { |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 181 | return pwmchip_remove(&lpwm->chip); |
| 182 | } |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 183 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 184 | |
| 185 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); |
| 186 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
| 187 | MODULE_LICENSE("GPL v2"); |