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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#undef DEBUG
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110022#undef DEBUG_LOW
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/sched.h>
27#include <linux/proc_fs.h>
28#include <linux/stat.h>
29#include <linux/sysctl.h>
30#include <linux/ctype.h>
31#include <linux/cache.h>
32#include <linux/init.h>
33#include <linux/signal.h>
David S. Millerd9b2b2a2008-02-13 16:56:49 -080034#include <linux/lmb.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <asm/processor.h>
37#include <asm/pgtable.h>
38#include <asm/mmu.h>
39#include <asm/mmu_context.h>
40#include <asm/page.h>
41#include <asm/types.h>
42#include <asm/system.h>
43#include <asm/uaccess.h>
44#include <asm/machdep.h>
David S. Millerd9b2b2a2008-02-13 16:56:49 -080045#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <asm/abs_addr.h>
47#include <asm/tlbflush.h>
48#include <asm/io.h>
49#include <asm/eeh.h>
50#include <asm/tlb.h>
51#include <asm/cacheflush.h>
52#include <asm/cputable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/sections.h>
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +100054#include <asm/spu.h>
will schmidtaa39be02007-10-30 06:24:19 +110055#include <asm/udbg.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
57#ifdef DEBUG
58#define DBG(fmt...) udbg_printf(fmt)
59#else
60#define DBG(fmt...)
61#endif
62
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110063#ifdef DEBUG_LOW
64#define DBG_LOW(fmt...) udbg_printf(fmt)
65#else
66#define DBG_LOW(fmt...)
67#endif
68
69#define KB (1024)
70#define MB (1024*KB)
Jon Tollefson658013e2008-07-23 21:27:54 -070071#define GB (1024L*MB)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110072
Linus Torvalds1da177e2005-04-16 15:20:36 -070073/*
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
76 *
77 * Execution context:
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
82 *
83 */
84
85#ifdef CONFIG_U3_DART
86extern unsigned long dart_tablebase;
87#endif /* CONFIG_U3_DART */
88
Paul Mackerras799d6042005-11-10 13:37:51 +110089static unsigned long _SDR1;
90struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91
David Gibson8e561e72007-06-13 14:52:56 +100092struct hash_pte *htab_address;
Michael Ellerman337a7122006-02-21 17:22:55 +110093unsigned long htab_size_bytes;
David Gibson96e28442005-07-13 01:11:42 -070094unsigned long htab_hash_mask;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110095int mmu_linear_psize = MMU_PAGE_4K;
96int mmu_virtual_psize = MMU_PAGE_4K;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +100097int mmu_vmalloc_psize = MMU_PAGE_4K;
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +100098#ifdef CONFIG_SPARSEMEM_VMEMMAP
99int mmu_vmemmap_psize = MMU_PAGE_4K;
100#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000101int mmu_io_psize = MMU_PAGE_4K;
Paul Mackerras1189be62007-10-11 20:37:10 +1000102int mmu_kernel_ssize = MMU_SEGSIZE_256M;
103int mmu_highuser_ssize = MMU_SEGSIZE_256M;
Michael Neuling584f8b72007-12-06 17:24:48 +1100104u16 mmu_slb_size = 64;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100105#ifdef CONFIG_HUGETLB_PAGE
106int mmu_huge_psize = MMU_PAGE_16M;
107unsigned int HPAGE_SHIFT;
108#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000109#ifdef CONFIG_PPC_64K_PAGES
110int mmu_ci_restrictions;
111#endif
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000112#ifdef CONFIG_DEBUG_PAGEALLOC
113static u8 *linear_map_hash_slots;
114static unsigned long linear_map_hash_count;
Michael Ellermaned166692007-04-18 11:50:09 +1000115static DEFINE_SPINLOCK(linear_map_hash_lock);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000116#endif /* CONFIG_DEBUG_PAGEALLOC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100118/* There are definitions of page sizes arrays to be used when none
119 * is provided by the firmware.
120 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100122/* Pre-POWER4 CPUs (4k pages only)
123 */
Michael Ellerman09de9ff2008-05-08 14:27:07 +1000124static struct mmu_psize_def mmu_psize_defaults_old[] = {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100125 [MMU_PAGE_4K] = {
126 .shift = 12,
127 .sllp = 0,
128 .penc = 0,
129 .avpnm = 0,
130 .tlbiel = 0,
131 },
132};
133
134/* POWER4, GPUL, POWER5
135 *
136 * Support for 16Mb large pages
137 */
Michael Ellerman09de9ff2008-05-08 14:27:07 +1000138static struct mmu_psize_def mmu_psize_defaults_gp[] = {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100139 [MMU_PAGE_4K] = {
140 .shift = 12,
141 .sllp = 0,
142 .penc = 0,
143 .avpnm = 0,
144 .tlbiel = 1,
145 },
146 [MMU_PAGE_16M] = {
147 .shift = 24,
148 .sllp = SLB_VSID_L,
149 .penc = 0,
150 .avpnm = 0x1UL,
151 .tlbiel = 0,
152 },
153};
154
155
156int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
Paul Mackerras1189be62007-10-11 20:37:10 +1000157 unsigned long pstart, unsigned long mode,
158 int psize, int ssize)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100160 unsigned long vaddr, paddr;
161 unsigned int step, shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 unsigned long tmp_mode;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100163 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100165 shift = mmu_psize_defs[psize].shift;
166 step = 1 << shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100168 for (vaddr = vstart, paddr = pstart; vaddr < vend;
169 vaddr += step, paddr += step) {
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000170 unsigned long hash, hpteg;
Paul Mackerras1189be62007-10-11 20:37:10 +1000171 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
172 unsigned long va = hpt_va(vaddr, vsid, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 tmp_mode = mode;
175
176 /* Make non-kernel text non-executable */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100177 if (!in_kernel_text(vaddr))
178 tmp_mode = mode | HPTE_R_N;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179
Paul Mackerras1189be62007-10-11 20:37:10 +1000180 hash = hpt_hash(va, shift, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
182
Michael Ellermanc30a4df2006-06-23 18:16:39 +1000183 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
184
185 BUG_ON(!ppc_md.hpte_insert);
186 ret = ppc_md.hpte_insert(hpteg, va, paddr,
Paul Mackerras1189be62007-10-11 20:37:10 +1000187 tmp_mode, HPTE_V_BOLTED, psize, ssize);
Michael Ellermanc30a4df2006-06-23 18:16:39 +1000188
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100189 if (ret < 0)
190 break;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000191#ifdef CONFIG_DEBUG_PAGEALLOC
192 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
193 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
194#endif /* CONFIG_DEBUG_PAGEALLOC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100196 return ret < 0 ? ret : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197}
198
Stephen Rothwellae86f002008-03-27 16:08:57 +1100199#ifdef CONFIG_MEMORY_HOTPLUG
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100200static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100201 int psize, int ssize)
202{
203 unsigned long vaddr;
204 unsigned int step, shift;
205
206 shift = mmu_psize_defs[psize].shift;
207 step = 1 << shift;
208
209 if (!ppc_md.hpte_removebolted) {
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100210 printk(KERN_WARNING "Platform doesn't implement "
211 "hpte_removebolted\n");
212 return -EINVAL;
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100213 }
214
215 for (vaddr = vstart; vaddr < vend; vaddr += step)
216 ppc_md.hpte_removebolted(vaddr, psize, ssize);
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100217
218 return 0;
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100219}
Stephen Rothwellae86f002008-03-27 16:08:57 +1100220#endif /* CONFIG_MEMORY_HOTPLUG */
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100221
Paul Mackerras1189be62007-10-11 20:37:10 +1000222static int __init htab_dt_scan_seg_sizes(unsigned long node,
223 const char *uname, int depth,
224 void *data)
225{
226 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
227 u32 *prop;
228 unsigned long size = 0;
229
230 /* We are scanning "cpu" nodes only */
231 if (type == NULL || strcmp(type, "cpu") != 0)
232 return 0;
233
234 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
235 &size);
236 if (prop == NULL)
237 return 0;
238 for (; size >= 4; size -= 4, ++prop) {
239 if (prop[0] == 40) {
240 DBG("1T segment support detected\n");
241 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
Olof Johanssonf5534002007-10-12 16:44:55 +1000242 return 1;
Paul Mackerras1189be62007-10-11 20:37:10 +1000243 }
Paul Mackerras1189be62007-10-11 20:37:10 +1000244 }
Olof Johanssonf66bce52007-10-16 00:58:59 +1000245 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
Paul Mackerras1189be62007-10-11 20:37:10 +1000246 return 0;
247}
248
249static void __init htab_init_seg_sizes(void)
250{
251 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
252}
253
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100254static int __init htab_dt_scan_page_sizes(unsigned long node,
255 const char *uname, int depth,
256 void *data)
257{
258 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
259 u32 *prop;
260 unsigned long size = 0;
261
262 /* We are scanning "cpu" nodes only */
263 if (type == NULL || strcmp(type, "cpu") != 0)
264 return 0;
265
266 prop = (u32 *)of_get_flat_dt_prop(node,
267 "ibm,segment-page-sizes", &size);
268 if (prop != NULL) {
269 DBG("Page sizes from device-tree:\n");
270 size /= 4;
271 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
272 while(size > 0) {
273 unsigned int shift = prop[0];
274 unsigned int slbenc = prop[1];
275 unsigned int lpnum = prop[2];
276 unsigned int lpenc = 0;
277 struct mmu_psize_def *def;
278 int idx = -1;
279
280 size -= 3; prop += 3;
281 while(size > 0 && lpnum) {
282 if (prop[0] == shift)
283 lpenc = prop[1];
284 prop += 2; size -= 2;
285 lpnum--;
286 }
287 switch(shift) {
288 case 0xc:
289 idx = MMU_PAGE_4K;
290 break;
291 case 0x10:
292 idx = MMU_PAGE_64K;
293 break;
294 case 0x14:
295 idx = MMU_PAGE_1M;
296 break;
297 case 0x18:
298 idx = MMU_PAGE_16M;
299 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
300 break;
301 case 0x22:
302 idx = MMU_PAGE_16G;
303 break;
304 }
305 if (idx < 0)
306 continue;
307 def = &mmu_psize_defs[idx];
308 def->shift = shift;
309 if (shift <= 23)
310 def->avpnm = 0;
311 else
312 def->avpnm = (1 << (shift - 23)) - 1;
313 def->sllp = slbenc;
314 def->penc = lpenc;
315 /* We don't know for sure what's up with tlbiel, so
316 * for now we only set it for 4K and 64K pages
317 */
318 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
319 def->tlbiel = 1;
320 else
321 def->tlbiel = 0;
322
323 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
324 "tlbiel=%d, penc=%d\n",
325 idx, shift, def->sllp, def->avpnm, def->tlbiel,
326 def->penc);
327 }
328 return 1;
329 }
330 return 0;
331}
332
Jon Tollefson658013e2008-07-23 21:27:54 -0700333/* Scan for 16G memory blocks that have been set aside for huge pages
334 * and reserve those blocks for 16G huge pages.
335 */
336static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
337 const char *uname, int depth,
338 void *data) {
339 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
340 unsigned long *addr_prop;
341 u32 *page_count_prop;
342 unsigned int expected_pages;
343 long unsigned int phys_addr;
344 long unsigned int block_size;
345
346 /* We are scanning "memory" nodes only */
347 if (type == NULL || strcmp(type, "memory") != 0)
348 return 0;
349
350 /* This property is the log base 2 of the number of virtual pages that
351 * will represent this memory block. */
352 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
353 if (page_count_prop == NULL)
354 return 0;
355 expected_pages = (1 << page_count_prop[0]);
356 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
357 if (addr_prop == NULL)
358 return 0;
359 phys_addr = addr_prop[0];
360 block_size = addr_prop[1];
361 if (block_size != (16 * GB))
362 return 0;
363 printk(KERN_INFO "Huge page(16GB) memory: "
364 "addr = 0x%lX size = 0x%lX pages = %d\n",
365 phys_addr, block_size, expected_pages);
366 lmb_reserve(phys_addr, block_size * expected_pages);
367 add_gpage(phys_addr, block_size, expected_pages);
368 return 0;
369}
370
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100371static void __init htab_init_page_sizes(void)
372{
373 int rc;
374
375 /* Default to 4K pages only */
376 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
377 sizeof(mmu_psize_defaults_old));
378
379 /*
380 * Try to find the available page sizes in the device-tree
381 */
382 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
383 if (rc != 0) /* Found */
384 goto found;
385
386 /*
387 * Not in the device-tree, let's fallback on known size
388 * list for 16M capable GP & GR
389 */
Stephen Rothwell04704662006-11-30 11:46:22 +1100390 if (cpu_has_feature(CPU_FTR_16M_PAGE))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100391 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
392 sizeof(mmu_psize_defaults_gp));
393 found:
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000394#ifndef CONFIG_DEBUG_PAGEALLOC
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100395 /*
396 * Pick a size for the linear mapping. Currently, we only support
397 * 16M, 1M and 4K which is the default
398 */
399 if (mmu_psize_defs[MMU_PAGE_16M].shift)
400 mmu_linear_psize = MMU_PAGE_16M;
401 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
402 mmu_linear_psize = MMU_PAGE_1M;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000403#endif /* CONFIG_DEBUG_PAGEALLOC */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100404
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000405#ifdef CONFIG_PPC_64K_PAGES
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100406 /*
407 * Pick a size for the ordinary pages. Default is 4K, we support
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000408 * 64K for user mappings and vmalloc if supported by the processor.
409 * We only use 64k for ioremap if the processor
410 * (and firmware) support cache-inhibited large pages.
411 * If not, we use 4k and set mmu_ci_restrictions so that
412 * hash_page knows to switch processes that use cache-inhibited
413 * mappings to 4k pages.
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100414 */
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000415 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100416 mmu_virtual_psize = MMU_PAGE_64K;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000417 mmu_vmalloc_psize = MMU_PAGE_64K;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000418 if (mmu_linear_psize == MMU_PAGE_4K)
419 mmu_linear_psize = MMU_PAGE_64K;
Paul Mackerrascfe666b2008-03-24 17:41:22 +1100420 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
421 /*
422 * Don't use 64k pages for ioremap on pSeries, since
423 * that would stop us accessing the HEA ethernet.
424 */
425 if (!machine_is(pseries))
426 mmu_io_psize = MMU_PAGE_64K;
427 } else
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000428 mmu_ci_restrictions = 1;
429 }
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000430#endif /* CONFIG_PPC_64K_PAGES */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100431
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000432#ifdef CONFIG_SPARSEMEM_VMEMMAP
433 /* We try to use 16M pages for vmemmap if that is supported
434 * and we have at least 1G of RAM at boot
435 */
436 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
437 lmb_phys_mem_size() >= 0x40000000)
438 mmu_vmemmap_psize = MMU_PAGE_16M;
439 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
440 mmu_vmemmap_psize = MMU_PAGE_64K;
441 else
442 mmu_vmemmap_psize = MMU_PAGE_4K;
443#endif /* CONFIG_SPARSEMEM_VMEMMAP */
444
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000445 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000446 "virtual = %d, io = %d"
447#ifdef CONFIG_SPARSEMEM_VMEMMAP
448 ", vmemmap = %d"
449#endif
450 "\n",
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100451 mmu_psize_defs[mmu_linear_psize].shift,
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000452 mmu_psize_defs[mmu_virtual_psize].shift,
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000453 mmu_psize_defs[mmu_io_psize].shift
454#ifdef CONFIG_SPARSEMEM_VMEMMAP
455 ,mmu_psize_defs[mmu_vmemmap_psize].shift
456#endif
457 );
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100458
459#ifdef CONFIG_HUGETLB_PAGE
Jon Tollefson658013e2008-07-23 21:27:54 -0700460 /* Reserve 16G huge page memory sections for huge pages */
461 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
462
463/* Init large page size. Currently, we pick 16M or 1M depending
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100464 * on what is available
465 */
466 if (mmu_psize_defs[MMU_PAGE_16M].shift)
Jon Tollefson4ec161c2008-01-04 09:59:50 +1100467 set_huge_psize(MMU_PAGE_16M);
David Gibson7d24f0b2005-11-07 00:57:52 -0800468 /* With 4k/4level pagetables, we can't (for now) cope with a
469 * huge page size < PMD_SIZE */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100470 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
Jon Tollefson4ec161c2008-01-04 09:59:50 +1100471 set_huge_psize(MMU_PAGE_1M);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100472#endif /* CONFIG_HUGETLB_PAGE */
473}
474
475static int __init htab_dt_scan_pftsize(unsigned long node,
476 const char *uname, int depth,
477 void *data)
478{
479 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
480 u32 *prop;
481
482 /* We are scanning "cpu" nodes only */
483 if (type == NULL || strcmp(type, "cpu") != 0)
484 return 0;
485
486 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
487 if (prop != NULL) {
488 /* pft_size[0] is the NUMA CEC cookie */
489 ppc64_pft_size = prop[1];
490 return 1;
491 }
492 return 0;
493}
494
495static unsigned long __init htab_get_table_size(void)
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000496{
Paul Mackerras799d6042005-11-10 13:37:51 +1100497 unsigned long mem_size, rnd_mem_size, pteg_count;
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000498
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100499 /* If hash size isn't already provided by the platform, we try to
Adrian Bunk943ffb52006-01-10 00:10:13 +0100500 * retrieve it from the device-tree. If it's not there neither, we
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100501 * calculate it now based on the total RAM size
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000502 */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100503 if (ppc64_pft_size == 0)
504 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000505 if (ppc64_pft_size)
506 return 1UL << ppc64_pft_size;
507
508 /* round mem_size up to next power of 2 */
Paul Mackerras799d6042005-11-10 13:37:51 +1100509 mem_size = lmb_phys_mem_size();
510 rnd_mem_size = 1UL << __ilog2(mem_size);
511 if (rnd_mem_size < mem_size)
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000512 rnd_mem_size <<= 1;
513
514 /* # pages / 2 */
515 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
516
517 return pteg_count << 7;
518}
519
Mike Kravetz54b79242005-11-07 16:25:48 -0800520#ifdef CONFIG_MEMORY_HOTPLUG
521void create_section_mapping(unsigned long start, unsigned long end)
522{
Michael Ellermancaf80e52006-03-21 20:45:51 +1100523 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
Mike Kravetz54b79242005-11-07 16:25:48 -0800524 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
Paul Mackerras1189be62007-10-11 20:37:10 +1000525 mmu_linear_psize, mmu_kernel_ssize));
Mike Kravetz54b79242005-11-07 16:25:48 -0800526}
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100527
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100528int remove_section_mapping(unsigned long start, unsigned long end)
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100529{
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100530 return htab_remove_mapping(start, end, mmu_linear_psize,
531 mmu_kernel_ssize);
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100532}
Mike Kravetz54b79242005-11-07 16:25:48 -0800533#endif /* CONFIG_MEMORY_HOTPLUG */
534
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000535static inline void make_bl(unsigned int *insn_addr, void *func)
536{
537 unsigned long funcp = *((unsigned long *)func);
538 int offset = funcp - (unsigned long)insn_addr;
539
540 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
541 flush_icache_range((unsigned long)insn_addr, 4+
542 (unsigned long)insn_addr);
543}
544
545static void __init htab_finish_init(void)
546{
547 extern unsigned int *htab_call_hpte_insert1;
548 extern unsigned int *htab_call_hpte_insert2;
549 extern unsigned int *htab_call_hpte_remove;
550 extern unsigned int *htab_call_hpte_updatepp;
551
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000552#ifdef CONFIG_PPC_HAS_HASH_64K
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000553 extern unsigned int *ht64_call_hpte_insert1;
554 extern unsigned int *ht64_call_hpte_insert2;
555 extern unsigned int *ht64_call_hpte_remove;
556 extern unsigned int *ht64_call_hpte_updatepp;
557
558 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
559 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
560 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
561 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
Jon Tollefson5b825832007-05-17 04:43:02 +1000562#endif /* CONFIG_PPC_HAS_HASH_64K */
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000563
564 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
565 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
566 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
567 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
568}
569
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570void __init htab_initialize(void)
571{
Michael Ellerman337a7122006-02-21 17:22:55 +1100572 unsigned long table;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 unsigned long pteg_count;
574 unsigned long mode_rw;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100575 unsigned long base = 0, size = 0, limit;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100576 int i;
577
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 DBG(" -> htab_initialize()\n");
579
Paul Mackerras1189be62007-10-11 20:37:10 +1000580 /* Initialize segment sizes */
581 htab_init_seg_sizes();
582
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100583 /* Initialize page sizes */
584 htab_init_page_sizes();
585
Paul Mackerras1189be62007-10-11 20:37:10 +1000586 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
587 mmu_kernel_ssize = MMU_SEGSIZE_1T;
588 mmu_highuser_ssize = MMU_SEGSIZE_1T;
589 printk(KERN_INFO "Using 1TB segments\n");
590 }
591
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 /*
593 * Calculate the required size of the htab. We want the number of
594 * PTEGs to equal one half the number of real pages.
595 */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100596 htab_size_bytes = htab_get_table_size();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 pteg_count = htab_size_bytes >> 7;
598
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 htab_hash_mask = pteg_count - 1;
600
Michael Ellerman57cfb812006-03-21 20:45:59 +1100601 if (firmware_has_feature(FW_FEATURE_LPAR)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602 /* Using a hypervisor which owns the htab */
603 htab_address = NULL;
604 _SDR1 = 0;
605 } else {
606 /* Find storage for the HPT. Must be contiguous in
Michael Ellerman41d824b2008-01-30 01:13:59 +1100607 * the absolute address space. On cell we want it to be
Michael Ellerman31bf1112008-03-12 18:03:24 +1100608 * in the first 2 Gig so we can use it for IOMMU hacks.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 */
Michael Ellerman41d824b2008-01-30 01:13:59 +1100610 if (machine_is(cell))
Michael Ellerman31bf1112008-03-12 18:03:24 +1100611 limit = 0x80000000;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100612 else
613 limit = 0;
614
615 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616
617 DBG("Hash table allocated at %lx, size: %lx\n", table,
618 htab_size_bytes);
619
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 htab_address = abs_to_virt(table);
621
622 /* htab absolute addr + encoded htabsize */
623 _SDR1 = table + __ilog2(pteg_count) - 11;
624
625 /* Initialize the HPT with no entries */
626 memset((void *)table, 0, htab_size_bytes);
Paul Mackerras799d6042005-11-10 13:37:51 +1100627
628 /* Set SDR1 */
629 mtspr(SPRN_SDR1, _SDR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 }
631
Anton Blanchard515bae92005-06-21 17:15:55 -0700632 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000634#ifdef CONFIG_DEBUG_PAGEALLOC
635 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
636 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
637 1, lmb.rmo_size));
638 memset(linear_map_hash_slots, 0, linear_map_hash_count);
639#endif /* CONFIG_DEBUG_PAGEALLOC */
640
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 /* On U3 based machines, we need to reserve the DART area and
642 * _NOT_ map it to avoid cache paradoxes as it's remapped non
643 * cacheable later on
644 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645
646 /* create bolted the linear mapping in the hash table */
647 for (i=0; i < lmb.memory.cnt; i++) {
Michael Ellermanb5666f72005-12-05 10:24:33 -0600648 base = (unsigned long)__va(lmb.memory.region[i].base);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 size = lmb.memory.region[i].size;
650
651 DBG("creating mapping for region: %lx : %lx\n", base, size);
652
653#ifdef CONFIG_U3_DART
654 /* Do not map the DART space. Fortunately, it will be aligned
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100655 * in such a way that it will not cross two lmb regions and
656 * will fit within a single 16Mb page.
657 * The DART space is assumed to be a full 16Mb region even if
658 * we only use 2Mb of that space. We will use more of it later
659 * for AGP GART. We have to use a full 16Mb large page.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 */
661 DBG("DART base: %lx\n", dart_tablebase);
662
663 if (dart_tablebase != 0 && dart_tablebase >= base
664 && dart_tablebase < (base + size)) {
Michael Ellermancaf80e52006-03-21 20:45:51 +1100665 unsigned long dart_table_end = dart_tablebase + 16 * MB;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 if (base != dart_tablebase)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100667 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
Michael Ellermancaf80e52006-03-21 20:45:51 +1100668 __pa(base), mode_rw,
Paul Mackerras1189be62007-10-11 20:37:10 +1000669 mmu_linear_psize,
670 mmu_kernel_ssize));
Michael Ellermancaf80e52006-03-21 20:45:51 +1100671 if ((base + size) > dart_table_end)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100672 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
Michael Ellermancaf80e52006-03-21 20:45:51 +1100673 base + size,
674 __pa(dart_table_end),
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100675 mode_rw,
Paul Mackerras1189be62007-10-11 20:37:10 +1000676 mmu_linear_psize,
677 mmu_kernel_ssize));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 continue;
679 }
680#endif /* CONFIG_U3_DART */
Michael Ellermancaf80e52006-03-21 20:45:51 +1100681 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
Paul Mackerras1189be62007-10-11 20:37:10 +1000682 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100683 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684
685 /*
686 * If we have a memory_limit and we've allocated TCEs then we need to
687 * explicitly map the TCE area at the top of RAM. We also cope with the
688 * case that the TCEs start below memory_limit.
689 * tce_alloc_start/end are 16MB aligned so the mapping should work
690 * for either 4K or 16MB pages.
691 */
692 if (tce_alloc_start) {
Michael Ellermanb5666f72005-12-05 10:24:33 -0600693 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
694 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695
696 if (base + size >= tce_alloc_start)
697 tce_alloc_start = base + size + 1;
698
Michael Ellermancaf80e52006-03-21 20:45:51 +1100699 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
700 __pa(tce_alloc_start), mode_rw,
Paul Mackerras1189be62007-10-11 20:37:10 +1000701 mmu_linear_psize, mmu_kernel_ssize));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 }
703
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000704 htab_finish_init();
705
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 DBG(" <- htab_initialize()\n");
707}
708#undef KB
709#undef MB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710
Anton Blancharde597cb322005-12-29 10:46:29 +1100711void htab_initialize_secondary(void)
Paul Mackerras799d6042005-11-10 13:37:51 +1100712{
Michael Ellerman57cfb812006-03-21 20:45:59 +1100713 if (!firmware_has_feature(FW_FEATURE_LPAR))
Paul Mackerras799d6042005-11-10 13:37:51 +1100714 mtspr(SPRN_SDR1, _SDR1);
715}
716
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717/*
718 * Called by asm hashtable.S for doing lazy icache flush
719 */
720unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
721{
722 struct page *page;
723
Benjamin Herrenschmidt76c8e252005-11-08 11:21:05 +1100724 if (!pfn_valid(pte_pfn(pte)))
725 return pp;
726
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 page = pte_page(pte);
728
729 /* page is dirty */
730 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
731 if (trap == 0x400) {
732 __flush_dcache_icache(page_address(page));
733 set_bit(PG_arch_1, &page->flags);
734 } else
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100735 pp |= HPTE_R_N;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 }
737 return pp;
738}
739
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000740#ifdef CONFIG_PPC_MM_SLICES
741unsigned int get_paca_psize(unsigned long addr)
742{
743 unsigned long index, slices;
744
745 if (addr < SLICE_LOW_TOP) {
746 slices = get_paca()->context.low_slices_psize;
747 index = GET_LOW_SLICE_INDEX(addr);
748 } else {
749 slices = get_paca()->context.high_slices_psize;
750 index = GET_HIGH_SLICE_INDEX(addr);
751 }
752 return (slices >> (index * 4)) & 0xF;
753}
754
755#else
756unsigned int get_paca_psize(unsigned long addr)
757{
758 return get_paca()->context.user_psize;
759}
760#endif
761
Paul Mackerras721151d2007-04-03 21:24:02 +1000762/*
763 * Demote a segment to using 4k pages.
764 * For now this makes the whole process use 4k pages.
765 */
Paul Mackerras721151d2007-04-03 21:24:02 +1000766#ifdef CONFIG_PPC_64K_PAGES
Paul Mackerrasfa282372008-01-24 08:35:13 +1100767void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000768{
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000769 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
Paul Mackerras721151d2007-04-03 21:24:02 +1000770 return;
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000771 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
Geert Uytterhoeven1e57ba82007-07-17 02:35:38 +1000772#ifdef CONFIG_SPU_BASE
Paul Mackerras721151d2007-04-03 21:24:02 +1000773 spu_flush_all_slbs(mm);
774#endif
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000775 if (get_paca_psize(addr) != MMU_PAGE_4K) {
Paul Mackerrasfa282372008-01-24 08:35:13 +1100776 get_paca()->context = mm->context;
777 slb_flush_and_rebolt();
778 }
Paul Mackerras721151d2007-04-03 21:24:02 +1000779}
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000780#endif /* CONFIG_PPC_64K_PAGES */
Paul Mackerras721151d2007-04-03 21:24:02 +1000781
Paul Mackerrasfa282372008-01-24 08:35:13 +1100782#ifdef CONFIG_PPC_SUBPAGE_PROT
783/*
784 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
785 * Userspace sets the subpage permissions using the subpage_prot system call.
786 *
787 * Result is 0: full permissions, _PAGE_RW: read-only,
788 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
789 */
790static int subpage_protection(pgd_t *pgdir, unsigned long ea)
791{
792 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
793 u32 spp = 0;
794 u32 **sbpm, *sbpp;
795
796 if (ea >= spt->maxaddr)
797 return 0;
798 if (ea < 0x100000000) {
799 /* addresses below 4GB use spt->low_prot */
800 sbpm = spt->low_prot;
801 } else {
802 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
803 if (!sbpm)
804 return 0;
805 }
806 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
807 if (!sbpp)
808 return 0;
809 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
810
811 /* extract 2-bit bitfield for this 4k subpage */
812 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
813
814 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
815 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
816 return spp;
817}
818
819#else /* CONFIG_PPC_SUBPAGE_PROT */
820static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
821{
822 return 0;
823}
824#endif
825
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826/* Result code is:
827 * 0 - handled
828 * 1 - normal page fault
829 * -1 - critical hash insertion error
Paul Mackerrasfa282372008-01-24 08:35:13 +1100830 * -2 - access not permitted by subpage protection mechanism
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 */
832int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
833{
834 void *pgdir;
835 unsigned long vsid;
836 struct mm_struct *mm;
837 pte_t *ptep;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 cpumask_t tmp;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100839 int rc, user_region = 0, local = 0;
Paul Mackerras1189be62007-10-11 20:37:10 +1000840 int psize, ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100842 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
843 ea, access, trap);
David Gibson1f8d4192005-05-05 16:15:13 -0700844
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100845 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
846 DBG_LOW(" out of pgtable range !\n");
847 return 1;
848 }
849
850 /* Get region & vsid */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 switch (REGION_ID(ea)) {
852 case USER_REGION_ID:
853 user_region = 1;
854 mm = current->mm;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100855 if (! mm) {
856 DBG_LOW(" user region with no mm !\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 return 1;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100858 }
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000859 psize = get_slice_psize(mm, ea);
Paul Mackerras1189be62007-10-11 20:37:10 +1000860 ssize = user_segment_size(ea);
861 vsid = get_vsid(mm->context.id, ea, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 case VMALLOC_REGION_ID:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 mm = &init_mm;
Paul Mackerras1189be62007-10-11 20:37:10 +1000865 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000866 if (ea < VMALLOC_END)
867 psize = mmu_vmalloc_psize;
868 else
869 psize = mmu_io_psize;
Paul Mackerras1189be62007-10-11 20:37:10 +1000870 ssize = mmu_kernel_ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872 default:
873 /* Not a valid range
874 * Send the problem up to do_page_fault
875 */
876 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100878 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100880 /* Get pgdir */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 pgdir = mm->pgd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 if (pgdir == NULL)
883 return 1;
884
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100885 /* Check CPU locality */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 tmp = cpumask_of_cpu(smp_processor_id());
887 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
888 local = 1;
889
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +1000890#ifdef CONFIG_HUGETLB_PAGE
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100891 /* Handle hugepage regions */
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000892 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100893 DBG_LOW(" -> huge page !\n");
David Gibsoncbf52af2005-12-09 14:20:52 +1100894 return hash_huge_page(mm, access, ea, vsid, local, trap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895 }
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +1000896#endif /* CONFIG_HUGETLB_PAGE */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000898#ifndef CONFIG_PPC_64K_PAGES
899 /* If we use 4K pages and our psize is not 4K, then we are hitting
900 * a special driver mapping, we need to align the address before
901 * we fetch the PTE
902 */
903 if (psize != MMU_PAGE_4K)
904 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
905#endif /* CONFIG_PPC_64K_PAGES */
906
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100907 /* Get PTE and page size from page tables */
908 ptep = find_linux_pte(pgdir, ea);
909 if (ptep == NULL || !pte_present(*ptep)) {
910 DBG_LOW(" no PTE !\n");
911 return 1;
912 }
913
914#ifndef CONFIG_PPC_64K_PAGES
915 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
916#else
917 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
918 pte_val(*(ptep + PTRS_PER_PTE)));
919#endif
920 /* Pre-check access permissions (will be re-checked atomically
921 * in __hash_page_XX but this pre-check is a fast path
922 */
923 if (access & ~pte_val(*ptep)) {
924 DBG_LOW(" no access !\n");
925 return 1;
926 }
927
928 /* Do actual hashing */
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000929#ifdef CONFIG_PPC_64K_PAGES
Paul Mackerras721151d2007-04-03 21:24:02 +1000930 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000931 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
Paul Mackerras721151d2007-04-03 21:24:02 +1000932 demote_segment_4k(mm, ea);
933 psize = MMU_PAGE_4K;
934 }
935
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000936 /* If this PTE is non-cacheable and we have restrictions on
937 * using non cacheable large pages, then we switch to 4k
938 */
939 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
940 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
941 if (user_region) {
942 demote_segment_4k(mm, ea);
943 psize = MMU_PAGE_4K;
944 } else if (ea < VMALLOC_END) {
945 /*
946 * some driver did a non-cacheable mapping
947 * in vmalloc space, so switch vmalloc
948 * to 4k pages
949 */
950 printk(KERN_ALERT "Reducing vmalloc segment "
951 "to 4kB pages because of "
952 "non-cacheable mapping\n");
953 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
Geert Uytterhoeven1e57ba82007-07-17 02:35:38 +1000954#ifdef CONFIG_SPU_BASE
Benjamin Herrenschmidt94b2a432007-03-10 00:05:37 +0100955 spu_flush_all_slbs(mm);
956#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000957 }
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000958 }
959 if (user_region) {
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000960 if (psize != get_paca_psize(ea)) {
Benjamin Herrenschmidtf6ab0b92007-10-29 12:05:18 +1100961 get_paca()->context = mm->context;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000962 slb_flush_and_rebolt();
963 }
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000964 } else if (get_paca()->vmalloc_sllp !=
965 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
966 get_paca()->vmalloc_sllp =
967 mmu_psize_defs[mmu_vmalloc_psize].sllp;
Michael Neuling67439b72007-08-03 11:55:39 +1000968 slb_vmalloc_update();
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000969 }
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000970#endif /* CONFIG_PPC_64K_PAGES */
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000971
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000972#ifdef CONFIG_PPC_HAS_HASH_64K
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000973 if (psize == MMU_PAGE_64K)
Paul Mackerras1189be62007-10-11 20:37:10 +1000974 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100975 else
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000976#endif /* CONFIG_PPC_HAS_HASH_64K */
Paul Mackerrasfa282372008-01-24 08:35:13 +1100977 {
978 int spp = subpage_protection(pgdir, ea);
979 if (access & spp)
980 rc = -2;
981 else
982 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
983 local, ssize, spp);
984 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100985
986#ifndef CONFIG_PPC_64K_PAGES
987 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
988#else
989 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
990 pte_val(*(ptep + PTRS_PER_PTE)));
991#endif
992 DBG_LOW(" -> rc=%d\n", rc);
993 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994}
Arnd Bergmann67207b92005-11-15 15:53:48 -0500995EXPORT_SYMBOL_GPL(hash_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100997void hash_preload(struct mm_struct *mm, unsigned long ea,
998 unsigned long access, unsigned long trap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001000 unsigned long vsid;
1001 void *pgdir;
1002 pte_t *ptep;
1003 cpumask_t mask;
1004 unsigned long flags;
1005 int local = 0;
Paul Mackerras1189be62007-10-11 20:37:10 +10001006 int ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +10001008 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1009
1010#ifdef CONFIG_PPC_MM_SLICES
1011 /* We only prefault standard pages for now */
Ilpo Järvinen2b02d132007-08-16 08:03:35 +10001012 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001013 return;
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +10001014#endif
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001015
1016 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1017 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1018
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001019 /* Get Linux PTE if available */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001020 pgdir = mm->pgd;
1021 if (pgdir == NULL)
1022 return;
1023 ptep = find_linux_pte(pgdir, ea);
1024 if (!ptep)
1025 return;
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001026
1027#ifdef CONFIG_PPC_64K_PAGES
1028 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1029 * a 64K kernel), then we don't preload, hash_page() will take
1030 * care of it once we actually try to access the page.
1031 * That way we don't have to duplicate all of the logic for segment
1032 * page size demotion here
1033 */
1034 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1035 return;
1036#endif /* CONFIG_PPC_64K_PAGES */
1037
1038 /* Get VSID */
Paul Mackerras1189be62007-10-11 20:37:10 +10001039 ssize = user_segment_size(ea);
1040 vsid = get_vsid(mm->context.id, ea, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001041
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001042 /* Hash doesn't like irqs */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001043 local_irq_save(flags);
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001044
1045 /* Is that local to this CPU ? */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001046 mask = cpumask_of_cpu(smp_processor_id());
1047 if (cpus_equal(mm->cpu_vm_mask, mask))
1048 local = 1;
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001049
1050 /* Hash it in */
1051#ifdef CONFIG_PPC_HAS_HASH_64K
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001052 if (mm->context.user_psize == MMU_PAGE_64K)
Paul Mackerras1189be62007-10-11 20:37:10 +10001053 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054 else
Jon Tollefson5b825832007-05-17 04:43:02 +10001055#endif /* CONFIG_PPC_HAS_HASH_64K */
Paul Mackerrasfa282372008-01-24 08:35:13 +11001056 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1057 subpage_protection(pgdir, ea));
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001058
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001059 local_irq_restore(flags);
1060}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061
Benjamin Herrenschmidtf6ab0b92007-10-29 12:05:18 +11001062/* WARNING: This is called from hash_low_64.S, if you change this prototype,
1063 * do not forget to update the assembly call site !
1064 */
Paul Mackerras1189be62007-10-11 20:37:10 +10001065void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1066 int local)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001067{
1068 unsigned long hash, index, shift, hidx, slot;
1069
1070 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1071 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
Paul Mackerras1189be62007-10-11 20:37:10 +10001072 hash = hpt_hash(va, shift, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001073 hidx = __rpte_to_hidx(pte, index);
1074 if (hidx & _PTEIDX_SECONDARY)
1075 hash = ~hash;
1076 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1077 slot += hidx & _PTEIDX_GROUP_IX;
1078 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
Paul Mackerras1189be62007-10-11 20:37:10 +10001079 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001080 } pte_iterate_hashed_end();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081}
1082
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001083void flush_hash_range(unsigned long number, int local)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001085 if (ppc_md.flush_hash_range)
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001086 ppc_md.flush_hash_range(number, local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001087 else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088 int i;
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001089 struct ppc64_tlb_batch *batch =
1090 &__get_cpu_var(ppc64_tlb_batch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091
1092 for (i = 0; i < number; i++)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001093 flush_hash_page(batch->vaddr[i], batch->pte[i],
Paul Mackerras1189be62007-10-11 20:37:10 +10001094 batch->psize, batch->ssize, local);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 }
1096}
1097
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098/*
1099 * low_hash_fault is called when we the low level hash code failed
1100 * to instert a PTE due to an hypervisor error
1101 */
Paul Mackerrasfa282372008-01-24 08:35:13 +11001102void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103{
1104 if (user_mode(regs)) {
Paul Mackerrasfa282372008-01-24 08:35:13 +11001105#ifdef CONFIG_PPC_SUBPAGE_PROT
1106 if (rc == -2)
1107 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1108 else
1109#endif
1110 _exception(SIGBUS, regs, BUS_ADRERR, address);
1111 } else
1112 bad_page_fault(regs, address, SIGBUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113}
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001114
1115#ifdef CONFIG_DEBUG_PAGEALLOC
1116static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1117{
Paul Mackerras1189be62007-10-11 20:37:10 +10001118 unsigned long hash, hpteg;
1119 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1120 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001121 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
1122 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
1123 int ret;
1124
Paul Mackerras1189be62007-10-11 20:37:10 +10001125 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001126 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1127
1128 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
Paul Mackerras1189be62007-10-11 20:37:10 +10001129 mode, HPTE_V_BOLTED,
1130 mmu_linear_psize, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001131 BUG_ON (ret < 0);
1132 spin_lock(&linear_map_hash_lock);
1133 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1134 linear_map_hash_slots[lmi] = ret | 0x80;
1135 spin_unlock(&linear_map_hash_lock);
1136}
1137
1138static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1139{
Paul Mackerras1189be62007-10-11 20:37:10 +10001140 unsigned long hash, hidx, slot;
1141 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1142 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001143
Paul Mackerras1189be62007-10-11 20:37:10 +10001144 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001145 spin_lock(&linear_map_hash_lock);
1146 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1147 hidx = linear_map_hash_slots[lmi] & 0x7f;
1148 linear_map_hash_slots[lmi] = 0;
1149 spin_unlock(&linear_map_hash_lock);
1150 if (hidx & _PTEIDX_SECONDARY)
1151 hash = ~hash;
1152 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1153 slot += hidx & _PTEIDX_GROUP_IX;
Paul Mackerras1189be62007-10-11 20:37:10 +10001154 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001155}
1156
1157void kernel_map_pages(struct page *page, int numpages, int enable)
1158{
1159 unsigned long flags, vaddr, lmi;
1160 int i;
1161
1162 local_irq_save(flags);
1163 for (i = 0; i < numpages; i++, page++) {
1164 vaddr = (unsigned long)page_address(page);
1165 lmi = __pa(vaddr) >> PAGE_SHIFT;
1166 if (lmi >= linear_map_hash_count)
1167 continue;
1168 if (enable)
1169 kernel_map_linear_page(vaddr, lmi);
1170 else
1171 kernel_unmap_linear_page(vaddr, lmi);
1172 }
1173 local_irq_restore(flags);
1174}
1175#endif /* CONFIG_DEBUG_PAGEALLOC */