Linaro Git Browser
Code Review Sign In
review.linaro.org / kernel / linux-linaro-stable.git / 5b03df9ace680d7cdd34a69dfd85ca5f74159d18 / . / arch / arm / boot / dts / dove.dtsi
blob: b524ee377f83e7accba619ead05cd854a3920743 [file] [log] [blame]
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC";
6
Sebastian Hesselbarth138ee962012-09-25 02:02:16 +0200[diff] [blame]7 soc@f1000000 {
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]8 compatible = "simple-bus";
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]9 #address-cells = <1>;
10 #size-cells = <1>;
Sebastian Hesselbarth138ee962012-09-25 02:02:16 +0200[diff] [blame]11 interrupt-parent = <&intc>;
12
13 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
14 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
15 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
16 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
17 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
18 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
19 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
20 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]21
Sebastian Hesselbarthfd57c652012-09-25 02:02:14 +0200[diff] [blame]22 l2: l2-cache {
23 compatible = "marvell,tauros2-cache";
24 marvell,tauros2-cache-features = <0>;
25 };
26
Sebastian Hesselbarth138ee962012-09-25 02:02:16 +0200[diff] [blame]27 intc: interrupt-controller {
28 compatible = "marvell,orion-intc";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0x20204 0x04>, <0x20214 0x04>;
32 };
33
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]34 core_clk: core-clocks@d0214 {
35 compatible = "marvell,dove-core-clock";
36 reg = <0xd0214 0x4>;
37 #clock-cells = <1>;
38 };
39
40 gate_clk: clock-gating-control@d0038 {
41 compatible = "marvell,dove-gating-clock";
42 reg = <0xd0038 0x4>;
43 clocks = <&core_clk 0>;
44 #clock-cells = <1>;
45 };
46
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]47 uart0: serial@12000 {
48 compatible = "ns16550a";
49 reg = <0x12000 0x100>;
50 reg-shift = <2>;
51 interrupts = <7>;
52 clock-frequency = <166666667>;
53 status = "disabled";
54 };
55
56 uart1: serial@12100 {
57 compatible = "ns16550a";
58 reg = <0x12100 0x100>;
59 reg-shift = <2>;
60 interrupts = <8>;
61 clock-frequency = <166666667>;
62 status = "disabled";
63 };
64
65 uart2: serial@12200 {
66 compatible = "ns16550a";
67 reg = <0x12000 0x100>;
68 reg-shift = <2>;
69 interrupts = <9>;
70 clock-frequency = <166666667>;
71 status = "disabled";
72 };
73
74 uart3: serial@12300 {
75 compatible = "ns16550a";
76 reg = <0x12100 0x100>;
77 reg-shift = <2>;
78 interrupts = <10>;
79 clock-frequency = <166666667>;
80 status = "disabled";
81 };
82
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]83 gpio0: gpio@d0400 {
84 compatible = "marvell,orion-gpio";
85 #gpio-cells = <2>;
86 gpio-controller;
87 reg = <0xd0400 0x20>;
88 ngpio = <32>;
89 interrupts = <12>, <13>, <14>, <60>;
90 };
91
92 gpio1: gpio@d0420 {
93 compatible = "marvell,orion-gpio";
94 #gpio-cells = <2>;
95 gpio-controller;
96 reg = <0xd0420 0x20>;
97 ngpio = <32>;
98 interrupts = <61>;
99 };
100
101 gpio2: gpio@e8400 {
102 compatible = "marvell,orion-gpio";
103 #gpio-cells = <2>;
104 gpio-controller;
105 reg = <0xe8400 0x0c>;
106 ngpio = <8>;
107 };
108
109 spi0: spi@10600 {
110 compatible = "marvell,orion-spi";
111 #address-cells = <1>;
112 #size-cells = <0>;
113 cell-index = <0>;
114 interrupts = <6>;
115 reg = <0x10600 0x28>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]116 clocks = <&core_clk 0>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]117 status = "disabled";
118 };
119
120 spi1: spi@14600 {
121 compatible = "marvell,orion-spi";
122 #address-cells = <1>;
123 #size-cells = <0>;
124 cell-index = <1>;
125 interrupts = <5>;
126 reg = <0x14600 0x28>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]127 clocks = <&core_clk 0>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]128 status = "disabled";
129 };
130
131 i2c0: i2c@11000 {
132 compatible = "marvell,mv64xxx-i2c";
133 reg = <0x11000 0x20>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 interrupts = <11>;
137 clock-frequency = <400000>;
138 timeout-ms = <1000>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]139 clocks = <&core_clk 0>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]140 status = "disabled";
141 };
142
143 sdio0: sdio@92000 {
144 compatible = "marvell,dove-sdhci";
145 reg = <0x92000 0x100>;
146 interrupts = <35>, <37>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]147 clocks = <&gate_clk 8>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]148 status = "disabled";
149 };
150
151 sdio1: sdio@90000 {
152 compatible = "marvell,dove-sdhci";
153 reg = <0x90000 0x100>;
154 interrupts = <36>, <38>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]155 clocks = <&gate_clk 9>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]156 status = "disabled";
157 };
158
159 sata0: sata@a0000 {
160 compatible = "marvell,orion-sata";
161 reg = <0xa0000 0x2400>;
162 interrupts = <62>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]163 clocks = <&gate_clk 3>;
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]164 nr-ports = <1>;
165 status = "disabled";
166 };
Sebastian Hesselbartha458926e2012-09-25 02:02:18 +0200[diff] [blame]167
168 crypto: crypto@30000 {
169 compatible = "marvell,orion-crypto";
170 reg = <0x30000 0x10000>,
171 <0xc8000000 0x800>;
172 reg-names = "regs", "sram";
173 interrupts = <31>;
Sebastian Hesselbarth5b03df92012-11-17 15:22:27 +0100[diff] [blame^]174 clocks = <&gate_clk 15>;
Sebastian Hesselbartha458926e2012-09-25 02:02:18 +0200[diff] [blame]175 status = "okay";
176 };
Sebastian Hesselbarth80a8b542012-08-15 19:07:34 +0200[diff] [blame]177 };
178};