Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * |
| 6 | * Rami Rosen <rosenr@marvell.com> |
| 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 15 | #include <linux/netdevice.h> |
| 16 | #include <linux/etherdevice.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/skbuff.h> |
| 19 | #include <linux/inetdevice.h> |
| 20 | #include <linux/mbus.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <net/ip.h> |
| 24 | #include <net/ipv6.h> |
| 25 | #include <linux/of.h> |
| 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/of_mdio.h> |
| 28 | #include <linux/of_net.h> |
| 29 | #include <linux/of_address.h> |
| 30 | #include <linux/phy.h> |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 31 | #include <linux/clk.h> |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 32 | |
| 33 | /* Registers */ |
| 34 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) |
| 35 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) |
| 36 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
| 37 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) |
| 38 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) |
| 39 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) |
| 40 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) |
| 41 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) |
| 42 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 |
| 43 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) |
| 44 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) |
| 45 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff |
| 46 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) |
| 47 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 |
| 48 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 |
| 49 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
| 50 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) |
| 51 | #define MVNETA_PHY_ADDR 0x2000 |
| 52 | #define MVNETA_PHY_ADDR_MASK 0x1f |
| 53 | #define MVNETA_MBUS_RETRY 0x2010 |
| 54 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 |
| 55 | #define MVNETA_UNIT_CONTROL 0x20B0 |
| 56 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) |
| 57 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) |
| 58 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) |
| 59 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) |
| 60 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 |
| 61 | #define MVNETA_PORT_CONFIG 0x2400 |
| 62 | #define MVNETA_UNI_PROMISC_MODE BIT(0) |
| 63 | #define MVNETA_DEF_RXQ(q) ((q) << 1) |
| 64 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) |
| 65 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) |
| 66 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) |
| 67 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) |
| 68 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) |
| 69 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) |
| 70 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ |
| 71 | MVNETA_DEF_RXQ_ARP(q) | \ |
| 72 | MVNETA_DEF_RXQ_TCP(q) | \ |
| 73 | MVNETA_DEF_RXQ_UDP(q) | \ |
| 74 | MVNETA_DEF_RXQ_BPDU(q) | \ |
| 75 | MVNETA_TX_UNSET_ERR_SUM | \ |
| 76 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) |
| 77 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 |
| 78 | #define MVNETA_MAC_ADDR_LOW 0x2414 |
| 79 | #define MVNETA_MAC_ADDR_HIGH 0x2418 |
| 80 | #define MVNETA_SDMA_CONFIG 0x241c |
| 81 | #define MVNETA_SDMA_BRST_SIZE_16 4 |
| 82 | #define MVNETA_NO_DESC_SWAP 0x0 |
| 83 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
| 84 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) |
| 85 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) |
| 86 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
| 87 | #define MVNETA_PORT_STATUS 0x2444 |
| 88 | #define MVNETA_TX_IN_PRGRS BIT(1) |
| 89 | #define MVNETA_TX_FIFO_EMPTY BIT(8) |
| 90 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c |
| 91 | #define MVNETA_TYPE_PRIO 0x24bc |
| 92 | #define MVNETA_FORCE_UNI BIT(21) |
| 93 | #define MVNETA_TXQ_CMD_1 0x24e4 |
| 94 | #define MVNETA_TXQ_CMD 0x2448 |
| 95 | #define MVNETA_TXQ_DISABLE_SHIFT 8 |
| 96 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff |
| 97 | #define MVNETA_ACC_MODE 0x2500 |
| 98 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
| 99 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff |
| 100 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 |
| 101 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
willy tarreau | 15ca23f | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 102 | |
| 103 | /* Exception Interrupt Port/Queue Cause register */ |
| 104 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 105 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 106 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
willy tarreau | 15ca23f | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 107 | |
| 108 | /* bits 0..7 = TXQ SENT, one bit per queue. |
| 109 | * bits 8..15 = RXQ OCCUP, one bit per queue. |
| 110 | * bits 16..23 = RXQ FREE, one bit per queue. |
| 111 | * bit 29 = OLD_REG_SUM, see old reg ? |
| 112 | * bit 30 = TX_ERR_SUM, one bit for 4 ports |
| 113 | * bit 31 = MISC_SUM, one bit for 4 ports |
| 114 | */ |
| 115 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) |
| 116 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) |
| 117 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) |
| 118 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) |
| 119 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 120 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
| 121 | #define MVNETA_INTR_OLD_MASK 0x25ac |
willy tarreau | 15ca23f | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 122 | |
| 123 | /* Data Path Port/Queue Cause Register */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 124 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
| 125 | #define MVNETA_INTR_MISC_MASK 0x25b4 |
willy tarreau | 15ca23f | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 126 | |
| 127 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) |
| 128 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) |
| 129 | #define MVNETA_CAUSE_PTP BIT(4) |
| 130 | |
| 131 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) |
| 132 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) |
| 133 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) |
| 134 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) |
| 135 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) |
| 136 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) |
| 137 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) |
| 138 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) |
| 139 | |
| 140 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 |
| 141 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) |
| 142 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) |
| 143 | |
| 144 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 |
| 145 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) |
| 146 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) |
| 147 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 148 | #define MVNETA_INTR_ENABLE 0x25b8 |
| 149 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 |
willy tarreau | 15ca23f | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 150 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF |
| 151 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 152 | #define MVNETA_RXQ_CMD 0x2680 |
| 153 | #define MVNETA_RXQ_DISABLE_SHIFT 8 |
| 154 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff |
| 155 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) |
| 156 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) |
| 157 | #define MVNETA_GMAC_CTRL_0 0x2c00 |
| 158 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 |
| 159 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc |
| 160 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) |
| 161 | #define MVNETA_GMAC_CTRL_2 0x2c08 |
Thomas Petazzoni | d113edc | 2014-03-26 00:25:41 +0100 | [diff] [blame] | 162 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 163 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
| 164 | #define MVNETA_GMAC2_PORT_RESET BIT(6) |
| 165 | #define MVNETA_GMAC_STATUS 0x2c10 |
| 166 | #define MVNETA_GMAC_LINK_UP BIT(0) |
| 167 | #define MVNETA_GMAC_SPEED_1000 BIT(1) |
| 168 | #define MVNETA_GMAC_SPEED_100 BIT(2) |
| 169 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) |
| 170 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) |
| 171 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) |
| 172 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) |
| 173 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) |
| 174 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c |
| 175 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) |
| 176 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) |
| 177 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
| 178 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) |
Thomas Petazzoni | 4c54b9d | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 179 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 180 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
Thomas Petazzoni | 4c54b9d | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 181 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 182 | #define MVNETA_MIB_COUNTERS_BASE 0x3080 |
| 183 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
| 184 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 |
| 185 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 |
| 186 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 |
| 187 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) |
| 188 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) |
| 189 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 |
| 190 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) |
| 191 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) |
| 192 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 |
| 193 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
| 194 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 |
| 195 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 |
| 196 | #define MVNETA_PORT_TX_RESET 0x3cf0 |
| 197 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) |
| 198 | #define MVNETA_TX_MTU 0x3e0c |
| 199 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 |
| 200 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff |
| 201 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) |
| 202 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff |
| 203 | |
| 204 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
| 205 | |
| 206 | /* Descriptor ring Macros */ |
| 207 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ |
| 208 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) |
| 209 | |
| 210 | /* Various constants */ |
| 211 | |
| 212 | /* Coalescing */ |
willy tarreau | 8df2d2d | 2014-12-02 08:13:04 +0100 | [diff] [blame] | 213 | #define MVNETA_TXDONE_COAL_PKTS 1 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 214 | #define MVNETA_RX_COAL_PKTS 32 |
| 215 | #define MVNETA_RX_COAL_USEC 100 |
| 216 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 217 | /* Napi polling weight */ |
| 218 | #define MVNETA_RX_POLL_WEIGHT 64 |
| 219 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 220 | /* The two bytes Marvell header. Either contains a special value used |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 221 | * by Marvell switches when a specific hardware mode is enabled (not |
| 222 | * supported by this driver) or is filled automatically by zeroes on |
| 223 | * the RX side. Those two bytes being at the front of the Ethernet |
| 224 | * header, they allow to have the IP header aligned on a 4 bytes |
| 225 | * boundary automatically: the hardware skips those two bytes on its |
| 226 | * own. |
| 227 | */ |
| 228 | #define MVNETA_MH_SIZE 2 |
| 229 | |
| 230 | #define MVNETA_VLAN_TAG_LEN 4 |
| 231 | |
| 232 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 |
| 233 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
| 234 | #define MVNETA_ACC_MODE_EXT 1 |
| 235 | |
| 236 | /* Timeout constants */ |
| 237 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 |
| 238 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 |
| 239 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 |
| 240 | |
| 241 | #define MVNETA_TX_MTU_MAX 0x3ffff |
| 242 | |
| 243 | /* Max number of Rx descriptors */ |
| 244 | #define MVNETA_MAX_RXD 128 |
| 245 | |
| 246 | /* Max number of Tx descriptors */ |
| 247 | #define MVNETA_MAX_TXD 532 |
| 248 | |
| 249 | /* descriptor aligned size */ |
| 250 | #define MVNETA_DESC_ALIGNED_SIZE 32 |
| 251 | |
| 252 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
| 253 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ |
| 254 | ETH_HLEN + ETH_FCS_LEN, \ |
| 255 | MVNETA_CPU_D_CACHE_LINE_SIZE) |
| 256 | |
| 257 | #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) |
| 258 | |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 259 | struct mvneta_pcpu_stats { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 260 | struct u64_stats_sync syncp; |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 261 | u64 rx_packets; |
| 262 | u64 rx_bytes; |
| 263 | u64 tx_packets; |
| 264 | u64 tx_bytes; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 265 | }; |
| 266 | |
| 267 | struct mvneta_port { |
| 268 | int pkt_size; |
| 269 | void __iomem *base; |
| 270 | struct mvneta_rx_queue *rxqs; |
| 271 | struct mvneta_tx_queue *txqs; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 272 | struct net_device *dev; |
| 273 | |
| 274 | u32 cause_rx_tx; |
| 275 | struct napi_struct napi; |
| 276 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 277 | /* Napi weight */ |
| 278 | int weight; |
| 279 | |
| 280 | /* Core clock */ |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 281 | struct clk *clk; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 282 | u8 mcast_count[256]; |
| 283 | u16 tx_ring_size; |
| 284 | u16 rx_ring_size; |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 285 | struct mvneta_pcpu_stats *stats; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 286 | |
| 287 | struct mii_bus *mii_bus; |
| 288 | struct phy_device *phy_dev; |
| 289 | phy_interface_t phy_interface; |
| 290 | struct device_node *phy_node; |
| 291 | unsigned int link; |
| 292 | unsigned int duplex; |
| 293 | unsigned int speed; |
| 294 | }; |
| 295 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 296 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 297 | * layout of the transmit and reception DMA descriptors, and their |
| 298 | * layout is therefore defined by the hardware design |
| 299 | */ |
| 300 | struct mvneta_tx_desc { |
| 301 | u32 command; /* Options used by HW for packet transmitting.*/ |
| 302 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
| 303 | #define MVNETA_TX_IP_HLEN_SHIFT 8 |
| 304 | #define MVNETA_TX_L4_UDP BIT(16) |
| 305 | #define MVNETA_TX_L3_IP6 BIT(17) |
| 306 | #define MVNETA_TXD_IP_CSUM BIT(18) |
| 307 | #define MVNETA_TXD_Z_PAD BIT(19) |
| 308 | #define MVNETA_TXD_L_DESC BIT(20) |
| 309 | #define MVNETA_TXD_F_DESC BIT(21) |
| 310 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ |
| 311 | MVNETA_TXD_L_DESC | \ |
| 312 | MVNETA_TXD_F_DESC) |
| 313 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) |
| 314 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) |
| 315 | |
| 316 | u16 reserverd1; /* csum_l4 (for future use) */ |
| 317 | u16 data_size; /* Data size of transmitted packet in bytes */ |
| 318 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ |
| 319 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ |
| 320 | u32 reserved3[4]; /* Reserved - (for future use) */ |
| 321 | }; |
| 322 | |
| 323 | struct mvneta_rx_desc { |
| 324 | u32 status; /* Info about received packet */ |
| 325 | #define MVNETA_RXD_ERR_CRC 0x0 |
| 326 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
| 327 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) |
| 328 | #define MVNETA_RXD_ERR_LEN BIT(18) |
| 329 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) |
| 330 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) |
| 331 | #define MVNETA_RXD_L3_IP4 BIT(25) |
| 332 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) |
| 333 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) |
| 334 | |
| 335 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
| 336 | u16 data_size; /* Size of received packet in bytes */ |
| 337 | u32 buf_phys_addr; /* Physical address of the buffer */ |
| 338 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ |
| 339 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
| 340 | u16 reserved3; /* prefetch_cmd, for future use */ |
| 341 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ |
| 342 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
| 343 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ |
| 344 | }; |
| 345 | |
| 346 | struct mvneta_tx_queue { |
| 347 | /* Number of this TX queue, in the range 0-7 */ |
| 348 | u8 id; |
| 349 | |
| 350 | /* Number of TX DMA descriptors in the descriptor ring */ |
| 351 | int size; |
| 352 | |
| 353 | /* Number of currently used TX DMA descriptor in the |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 354 | * descriptor ring |
| 355 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 356 | int count; |
| 357 | |
| 358 | /* Array of transmitted skb */ |
| 359 | struct sk_buff **tx_skb; |
| 360 | |
| 361 | /* Index of last TX DMA descriptor that was inserted */ |
| 362 | int txq_put_index; |
| 363 | |
| 364 | /* Index of the TX DMA descriptor to be cleaned up */ |
| 365 | int txq_get_index; |
| 366 | |
| 367 | u32 done_pkts_coal; |
| 368 | |
| 369 | /* Virtual address of the TX DMA descriptors array */ |
| 370 | struct mvneta_tx_desc *descs; |
| 371 | |
| 372 | /* DMA address of the TX DMA descriptors array */ |
| 373 | dma_addr_t descs_phys; |
| 374 | |
| 375 | /* Index of the last TX DMA descriptor */ |
| 376 | int last_desc; |
| 377 | |
| 378 | /* Index of the next TX DMA descriptor to process */ |
| 379 | int next_desc_to_proc; |
| 380 | }; |
| 381 | |
| 382 | struct mvneta_rx_queue { |
| 383 | /* rx queue number, in the range 0-7 */ |
| 384 | u8 id; |
| 385 | |
| 386 | /* num of rx descriptors in the rx descriptor ring */ |
| 387 | int size; |
| 388 | |
| 389 | /* counter of times when mvneta_refill() failed */ |
| 390 | int missed; |
| 391 | |
| 392 | u32 pkts_coal; |
| 393 | u32 time_coal; |
| 394 | |
| 395 | /* Virtual address of the RX DMA descriptors array */ |
| 396 | struct mvneta_rx_desc *descs; |
| 397 | |
| 398 | /* DMA address of the RX DMA descriptors array */ |
| 399 | dma_addr_t descs_phys; |
| 400 | |
| 401 | /* Index of the last RX DMA descriptor */ |
| 402 | int last_desc; |
| 403 | |
| 404 | /* Index of the next RX DMA descriptor to process */ |
| 405 | int next_desc_to_proc; |
| 406 | }; |
| 407 | |
| 408 | static int rxq_number = 8; |
| 409 | static int txq_number = 8; |
| 410 | |
| 411 | static int rxq_def; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 412 | |
| 413 | #define MVNETA_DRIVER_NAME "mvneta" |
| 414 | #define MVNETA_DRIVER_VERSION "1.0" |
| 415 | |
| 416 | /* Utility/helper methods */ |
| 417 | |
| 418 | /* Write helper method */ |
| 419 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) |
| 420 | { |
| 421 | writel(data, pp->base + offset); |
| 422 | } |
| 423 | |
| 424 | /* Read helper method */ |
| 425 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) |
| 426 | { |
| 427 | return readl(pp->base + offset); |
| 428 | } |
| 429 | |
| 430 | /* Increment txq get counter */ |
| 431 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) |
| 432 | { |
| 433 | txq->txq_get_index++; |
| 434 | if (txq->txq_get_index == txq->size) |
| 435 | txq->txq_get_index = 0; |
| 436 | } |
| 437 | |
| 438 | /* Increment txq put counter */ |
| 439 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) |
| 440 | { |
| 441 | txq->txq_put_index++; |
| 442 | if (txq->txq_put_index == txq->size) |
| 443 | txq->txq_put_index = 0; |
| 444 | } |
| 445 | |
| 446 | |
| 447 | /* Clear all MIB counters */ |
| 448 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) |
| 449 | { |
| 450 | int i; |
| 451 | u32 dummy; |
| 452 | |
| 453 | /* Perform dummy reads from MIB counters */ |
| 454 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) |
| 455 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); |
| 456 | } |
| 457 | |
| 458 | /* Get System Network Statistics */ |
| 459 | struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, |
| 460 | struct rtnl_link_stats64 *stats) |
| 461 | { |
| 462 | struct mvneta_port *pp = netdev_priv(dev); |
| 463 | unsigned int start; |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 464 | int cpu; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 465 | |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 466 | for_each_possible_cpu(cpu) { |
| 467 | struct mvneta_pcpu_stats *cpu_stats; |
| 468 | u64 rx_packets; |
| 469 | u64 rx_bytes; |
| 470 | u64 tx_packets; |
| 471 | u64 tx_bytes; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 472 | |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 473 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
| 474 | do { |
| 475 | start = u64_stats_fetch_begin_bh(&cpu_stats->syncp); |
| 476 | rx_packets = cpu_stats->rx_packets; |
| 477 | rx_bytes = cpu_stats->rx_bytes; |
| 478 | tx_packets = cpu_stats->tx_packets; |
| 479 | tx_bytes = cpu_stats->tx_bytes; |
| 480 | } while (u64_stats_fetch_retry_bh(&cpu_stats->syncp, start)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 481 | |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 482 | stats->rx_packets += rx_packets; |
| 483 | stats->rx_bytes += rx_bytes; |
| 484 | stats->tx_packets += tx_packets; |
| 485 | stats->tx_bytes += tx_bytes; |
| 486 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 487 | |
| 488 | stats->rx_errors = dev->stats.rx_errors; |
| 489 | stats->rx_dropped = dev->stats.rx_dropped; |
| 490 | |
| 491 | stats->tx_dropped = dev->stats.tx_dropped; |
| 492 | |
| 493 | return stats; |
| 494 | } |
| 495 | |
| 496 | /* Rx descriptors helper methods */ |
| 497 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 498 | /* Checks whether the given RX descriptor is both the first and the |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 499 | * last descriptor for the RX packet. Each RX packet is currently |
| 500 | * received through a single RX descriptor, so not having each RX |
| 501 | * descriptor with its first and last bits set is an error |
| 502 | */ |
| 503 | static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc *desc) |
| 504 | { |
| 505 | return (desc->status & MVNETA_RXD_FIRST_LAST_DESC) == |
| 506 | MVNETA_RXD_FIRST_LAST_DESC; |
| 507 | } |
| 508 | |
| 509 | /* Add number of descriptors ready to receive new packets */ |
| 510 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, |
| 511 | struct mvneta_rx_queue *rxq, |
| 512 | int ndescs) |
| 513 | { |
| 514 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 515 | * be added at once |
| 516 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 517 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
| 518 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), |
| 519 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << |
| 520 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); |
| 521 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; |
| 522 | } |
| 523 | |
| 524 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), |
| 525 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); |
| 526 | } |
| 527 | |
| 528 | /* Get number of RX descriptors occupied by received packets */ |
| 529 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, |
| 530 | struct mvneta_rx_queue *rxq) |
| 531 | { |
| 532 | u32 val; |
| 533 | |
| 534 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); |
| 535 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; |
| 536 | } |
| 537 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 538 | /* Update num of rx desc called upon return from rx path or |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 539 | * from mvneta_rxq_drop_pkts(). |
| 540 | */ |
| 541 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, |
| 542 | struct mvneta_rx_queue *rxq, |
| 543 | int rx_done, int rx_filled) |
| 544 | { |
| 545 | u32 val; |
| 546 | |
| 547 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { |
| 548 | val = rx_done | |
| 549 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); |
| 550 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); |
| 551 | return; |
| 552 | } |
| 553 | |
| 554 | /* Only 255 descriptors can be added at once */ |
| 555 | while ((rx_done > 0) || (rx_filled > 0)) { |
| 556 | if (rx_done <= 0xff) { |
| 557 | val = rx_done; |
| 558 | rx_done = 0; |
| 559 | } else { |
| 560 | val = 0xff; |
| 561 | rx_done -= 0xff; |
| 562 | } |
| 563 | if (rx_filled <= 0xff) { |
| 564 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; |
| 565 | rx_filled = 0; |
| 566 | } else { |
| 567 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; |
| 568 | rx_filled -= 0xff; |
| 569 | } |
| 570 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | /* Get pointer to next RX descriptor to be processed by SW */ |
| 575 | static struct mvneta_rx_desc * |
| 576 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) |
| 577 | { |
| 578 | int rx_desc = rxq->next_desc_to_proc; |
| 579 | |
| 580 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); |
| 581 | return rxq->descs + rx_desc; |
| 582 | } |
| 583 | |
| 584 | /* Change maximum receive size of the port. */ |
| 585 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) |
| 586 | { |
| 587 | u32 val; |
| 588 | |
| 589 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
| 590 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; |
| 591 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << |
| 592 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; |
| 593 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); |
| 594 | } |
| 595 | |
| 596 | |
| 597 | /* Set rx queue offset */ |
| 598 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, |
| 599 | struct mvneta_rx_queue *rxq, |
| 600 | int offset) |
| 601 | { |
| 602 | u32 val; |
| 603 | |
| 604 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); |
| 605 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; |
| 606 | |
| 607 | /* Offset is in */ |
| 608 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); |
| 609 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); |
| 610 | } |
| 611 | |
| 612 | |
| 613 | /* Tx descriptors helper methods */ |
| 614 | |
| 615 | /* Update HW with number of TX descriptors to be sent */ |
| 616 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, |
| 617 | struct mvneta_tx_queue *txq, |
| 618 | int pend_desc) |
| 619 | { |
| 620 | u32 val; |
| 621 | |
| 622 | /* Only 255 descriptors can be added at once ; Assume caller |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 623 | * process TX desriptors in quanta less than 256 |
| 624 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 625 | val = pend_desc; |
| 626 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
| 627 | } |
| 628 | |
| 629 | /* Get pointer to next TX descriptor to be processed (send) by HW */ |
| 630 | static struct mvneta_tx_desc * |
| 631 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) |
| 632 | { |
| 633 | int tx_desc = txq->next_desc_to_proc; |
| 634 | |
| 635 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); |
| 636 | return txq->descs + tx_desc; |
| 637 | } |
| 638 | |
| 639 | /* Release the last allocated TX descriptor. Useful to handle DMA |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 640 | * mapping failures in the TX path. |
| 641 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 642 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
| 643 | { |
| 644 | if (txq->next_desc_to_proc == 0) |
| 645 | txq->next_desc_to_proc = txq->last_desc - 1; |
| 646 | else |
| 647 | txq->next_desc_to_proc--; |
| 648 | } |
| 649 | |
| 650 | /* Set rxq buf size */ |
| 651 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, |
| 652 | struct mvneta_rx_queue *rxq, |
| 653 | int buf_size) |
| 654 | { |
| 655 | u32 val; |
| 656 | |
| 657 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); |
| 658 | |
| 659 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; |
| 660 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); |
| 661 | |
| 662 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); |
| 663 | } |
| 664 | |
| 665 | /* Disable buffer management (BM) */ |
| 666 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, |
| 667 | struct mvneta_rx_queue *rxq) |
| 668 | { |
| 669 | u32 val; |
| 670 | |
| 671 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); |
| 672 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; |
| 673 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); |
| 674 | } |
| 675 | |
| 676 | |
| 677 | |
| 678 | /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 679 | static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 680 | { |
| 681 | u32 val; |
| 682 | |
| 683 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
| 684 | |
| 685 | if (enable) |
| 686 | val |= MVNETA_GMAC2_PORT_RGMII; |
| 687 | else |
| 688 | val &= ~MVNETA_GMAC2_PORT_RGMII; |
| 689 | |
| 690 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); |
| 691 | } |
| 692 | |
| 693 | /* Config SGMII port */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 694 | static void mvneta_port_sgmii_config(struct mvneta_port *pp) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 695 | { |
| 696 | u32 val; |
| 697 | |
| 698 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
Thomas Petazzoni | d113edc | 2014-03-26 00:25:41 +0100 | [diff] [blame] | 699 | val |= MVNETA_GMAC2_PCS_ENABLE; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 700 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); |
| 701 | } |
| 702 | |
| 703 | /* Start the Ethernet port RX and TX activity */ |
| 704 | static void mvneta_port_up(struct mvneta_port *pp) |
| 705 | { |
| 706 | int queue; |
| 707 | u32 q_map; |
| 708 | |
| 709 | /* Enable all initialized TXs. */ |
| 710 | mvneta_mib_counters_clear(pp); |
| 711 | q_map = 0; |
| 712 | for (queue = 0; queue < txq_number; queue++) { |
| 713 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; |
| 714 | if (txq->descs != NULL) |
| 715 | q_map |= (1 << queue); |
| 716 | } |
| 717 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); |
| 718 | |
| 719 | /* Enable all initialized RXQs. */ |
| 720 | q_map = 0; |
| 721 | for (queue = 0; queue < rxq_number; queue++) { |
| 722 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; |
| 723 | if (rxq->descs != NULL) |
| 724 | q_map |= (1 << queue); |
| 725 | } |
| 726 | |
| 727 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); |
| 728 | } |
| 729 | |
| 730 | /* Stop the Ethernet port activity */ |
| 731 | static void mvneta_port_down(struct mvneta_port *pp) |
| 732 | { |
| 733 | u32 val; |
| 734 | int count; |
| 735 | |
| 736 | /* Stop Rx port activity. Check port Rx activity. */ |
| 737 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; |
| 738 | |
| 739 | /* Issue stop command for active channels only */ |
| 740 | if (val != 0) |
| 741 | mvreg_write(pp, MVNETA_RXQ_CMD, |
| 742 | val << MVNETA_RXQ_DISABLE_SHIFT); |
| 743 | |
| 744 | /* Wait for all Rx activity to terminate. */ |
| 745 | count = 0; |
| 746 | do { |
| 747 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { |
| 748 | netdev_warn(pp->dev, |
| 749 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", |
| 750 | val); |
| 751 | break; |
| 752 | } |
| 753 | mdelay(1); |
| 754 | |
| 755 | val = mvreg_read(pp, MVNETA_RXQ_CMD); |
| 756 | } while (val & 0xff); |
| 757 | |
| 758 | /* Stop Tx port activity. Check port Tx activity. Issue stop |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 759 | * command for active channels only |
| 760 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 761 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
| 762 | |
| 763 | if (val != 0) |
| 764 | mvreg_write(pp, MVNETA_TXQ_CMD, |
| 765 | (val << MVNETA_TXQ_DISABLE_SHIFT)); |
| 766 | |
| 767 | /* Wait for all Tx activity to terminate. */ |
| 768 | count = 0; |
| 769 | do { |
| 770 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { |
| 771 | netdev_warn(pp->dev, |
| 772 | "TIMEOUT for TX stopped status=0x%08x\n", |
| 773 | val); |
| 774 | break; |
| 775 | } |
| 776 | mdelay(1); |
| 777 | |
| 778 | /* Check TX Command reg that all Txqs are stopped */ |
| 779 | val = mvreg_read(pp, MVNETA_TXQ_CMD); |
| 780 | |
| 781 | } while (val & 0xff); |
| 782 | |
| 783 | /* Double check to verify that TX FIFO is empty */ |
| 784 | count = 0; |
| 785 | do { |
| 786 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { |
| 787 | netdev_warn(pp->dev, |
| 788 | "TX FIFO empty timeout status=0x08%x\n", |
| 789 | val); |
| 790 | break; |
| 791 | } |
| 792 | mdelay(1); |
| 793 | |
| 794 | val = mvreg_read(pp, MVNETA_PORT_STATUS); |
| 795 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && |
| 796 | (val & MVNETA_TX_IN_PRGRS)); |
| 797 | |
| 798 | udelay(200); |
| 799 | } |
| 800 | |
| 801 | /* Enable the port by setting the port enable bit of the MAC control register */ |
| 802 | static void mvneta_port_enable(struct mvneta_port *pp) |
| 803 | { |
| 804 | u32 val; |
| 805 | |
| 806 | /* Enable port */ |
| 807 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
| 808 | val |= MVNETA_GMAC0_PORT_ENABLE; |
| 809 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); |
| 810 | } |
| 811 | |
| 812 | /* Disable the port and wait for about 200 usec before retuning */ |
| 813 | static void mvneta_port_disable(struct mvneta_port *pp) |
| 814 | { |
| 815 | u32 val; |
| 816 | |
| 817 | /* Reset the Enable bit in the Serial Control Register */ |
| 818 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
| 819 | val &= ~MVNETA_GMAC0_PORT_ENABLE; |
| 820 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); |
| 821 | |
| 822 | udelay(200); |
| 823 | } |
| 824 | |
| 825 | /* Multicast tables methods */ |
| 826 | |
| 827 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ |
| 828 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) |
| 829 | { |
| 830 | int offset; |
| 831 | u32 val; |
| 832 | |
| 833 | if (queue == -1) { |
| 834 | val = 0; |
| 835 | } else { |
| 836 | val = 0x1 | (queue << 1); |
| 837 | val |= (val << 24) | (val << 16) | (val << 8); |
| 838 | } |
| 839 | |
| 840 | for (offset = 0; offset <= 0xc; offset += 4) |
| 841 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); |
| 842 | } |
| 843 | |
| 844 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ |
| 845 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) |
| 846 | { |
| 847 | int offset; |
| 848 | u32 val; |
| 849 | |
| 850 | if (queue == -1) { |
| 851 | val = 0; |
| 852 | } else { |
| 853 | val = 0x1 | (queue << 1); |
| 854 | val |= (val << 24) | (val << 16) | (val << 8); |
| 855 | } |
| 856 | |
| 857 | for (offset = 0; offset <= 0xfc; offset += 4) |
| 858 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); |
| 859 | |
| 860 | } |
| 861 | |
| 862 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ |
| 863 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) |
| 864 | { |
| 865 | int offset; |
| 866 | u32 val; |
| 867 | |
| 868 | if (queue == -1) { |
| 869 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); |
| 870 | val = 0; |
| 871 | } else { |
| 872 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); |
| 873 | val = 0x1 | (queue << 1); |
| 874 | val |= (val << 24) | (val << 16) | (val << 8); |
| 875 | } |
| 876 | |
| 877 | for (offset = 0; offset <= 0xfc; offset += 4) |
| 878 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); |
| 879 | } |
| 880 | |
| 881 | /* This method sets defaults to the NETA port: |
| 882 | * Clears interrupt Cause and Mask registers. |
| 883 | * Clears all MAC tables. |
| 884 | * Sets defaults to all registers. |
| 885 | * Resets RX and TX descriptor rings. |
| 886 | * Resets PHY. |
| 887 | * This method can be called after mvneta_port_down() to return the port |
| 888 | * settings to defaults. |
| 889 | */ |
| 890 | static void mvneta_defaults_set(struct mvneta_port *pp) |
| 891 | { |
| 892 | int cpu; |
| 893 | int queue; |
| 894 | u32 val; |
| 895 | |
| 896 | /* Clear all Cause registers */ |
| 897 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); |
| 898 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); |
| 899 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); |
| 900 | |
| 901 | /* Mask all interrupts */ |
| 902 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 903 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); |
| 904 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); |
| 905 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
| 906 | |
| 907 | /* Enable MBUS Retry bit16 */ |
| 908 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); |
| 909 | |
| 910 | /* Set CPU queue access map - all CPUs have access to all RX |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 911 | * queues and to all TX queues |
| 912 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 913 | for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) |
| 914 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), |
| 915 | (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | |
| 916 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); |
| 917 | |
| 918 | /* Reset RX and TX DMAs */ |
| 919 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); |
| 920 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); |
| 921 | |
| 922 | /* Disable Legacy WRR, Disable EJP, Release from reset */ |
| 923 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); |
| 924 | for (queue = 0; queue < txq_number; queue++) { |
| 925 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); |
| 926 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); |
| 927 | } |
| 928 | |
| 929 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); |
| 930 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); |
| 931 | |
| 932 | /* Set Port Acceleration Mode */ |
| 933 | val = MVNETA_ACC_MODE_EXT; |
| 934 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
| 935 | |
| 936 | /* Update val of portCfg register accordingly with all RxQueue types */ |
| 937 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); |
| 938 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
| 939 | |
| 940 | val = 0; |
| 941 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); |
| 942 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); |
| 943 | |
| 944 | /* Build PORT_SDMA_CONFIG_REG */ |
| 945 | val = 0; |
| 946 | |
| 947 | /* Default burst size */ |
| 948 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); |
| 949 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); |
| 950 | |
| 951 | val |= (MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP | |
| 952 | MVNETA_NO_DESC_SWAP); |
| 953 | |
| 954 | /* Assign port SDMA configuration */ |
| 955 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); |
| 956 | |
Thomas Petazzoni | 4c54b9d | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 957 | /* Disable PHY polling in hardware, since we're using the |
| 958 | * kernel phylib to do this. |
| 959 | */ |
| 960 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); |
| 961 | val &= ~MVNETA_PHY_POLLING_ENABLE; |
| 962 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); |
| 963 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 964 | mvneta_set_ucast_table(pp, -1); |
| 965 | mvneta_set_special_mcast_table(pp, -1); |
| 966 | mvneta_set_other_mcast_table(pp, -1); |
| 967 | |
| 968 | /* Set port interrupt enable register - default enable all */ |
| 969 | mvreg_write(pp, MVNETA_INTR_ENABLE, |
| 970 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK |
| 971 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); |
| 972 | } |
| 973 | |
| 974 | /* Set max sizes for tx queues */ |
| 975 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) |
| 976 | |
| 977 | { |
| 978 | u32 val, size, mtu; |
| 979 | int queue; |
| 980 | |
| 981 | mtu = max_tx_size * 8; |
| 982 | if (mtu > MVNETA_TX_MTU_MAX) |
| 983 | mtu = MVNETA_TX_MTU_MAX; |
| 984 | |
| 985 | /* Set MTU */ |
| 986 | val = mvreg_read(pp, MVNETA_TX_MTU); |
| 987 | val &= ~MVNETA_TX_MTU_MAX; |
| 988 | val |= mtu; |
| 989 | mvreg_write(pp, MVNETA_TX_MTU, val); |
| 990 | |
| 991 | /* TX token size and all TXQs token size must be larger that MTU */ |
| 992 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); |
| 993 | |
| 994 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; |
| 995 | if (size < mtu) { |
| 996 | size = mtu; |
| 997 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; |
| 998 | val |= size; |
| 999 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); |
| 1000 | } |
| 1001 | for (queue = 0; queue < txq_number; queue++) { |
| 1002 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); |
| 1003 | |
| 1004 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; |
| 1005 | if (size < mtu) { |
| 1006 | size = mtu; |
| 1007 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; |
| 1008 | val |= size; |
| 1009 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); |
| 1010 | } |
| 1011 | } |
| 1012 | } |
| 1013 | |
| 1014 | /* Set unicast address */ |
| 1015 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, |
| 1016 | int queue) |
| 1017 | { |
| 1018 | unsigned int unicast_reg; |
| 1019 | unsigned int tbl_offset; |
| 1020 | unsigned int reg_offset; |
| 1021 | |
| 1022 | /* Locate the Unicast table entry */ |
| 1023 | last_nibble = (0xf & last_nibble); |
| 1024 | |
| 1025 | /* offset from unicast tbl base */ |
| 1026 | tbl_offset = (last_nibble / 4) * 4; |
| 1027 | |
| 1028 | /* offset within the above reg */ |
| 1029 | reg_offset = last_nibble % 4; |
| 1030 | |
| 1031 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); |
| 1032 | |
| 1033 | if (queue == -1) { |
| 1034 | /* Clear accepts frame bit at specified unicast DA tbl entry */ |
| 1035 | unicast_reg &= ~(0xff << (8 * reg_offset)); |
| 1036 | } else { |
| 1037 | unicast_reg &= ~(0xff << (8 * reg_offset)); |
| 1038 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); |
| 1039 | } |
| 1040 | |
| 1041 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); |
| 1042 | } |
| 1043 | |
| 1044 | /* Set mac address */ |
| 1045 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, |
| 1046 | int queue) |
| 1047 | { |
| 1048 | unsigned int mac_h; |
| 1049 | unsigned int mac_l; |
| 1050 | |
| 1051 | if (queue != -1) { |
| 1052 | mac_l = (addr[4] << 8) | (addr[5]); |
| 1053 | mac_h = (addr[0] << 24) | (addr[1] << 16) | |
| 1054 | (addr[2] << 8) | (addr[3] << 0); |
| 1055 | |
| 1056 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); |
| 1057 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); |
| 1058 | } |
| 1059 | |
| 1060 | /* Accept frames of this address */ |
| 1061 | mvneta_set_ucast_addr(pp, addr[5], queue); |
| 1062 | } |
| 1063 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1064 | /* Set the number of packets that will be received before RX interrupt |
| 1065 | * will be generated by HW. |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1066 | */ |
| 1067 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, |
| 1068 | struct mvneta_rx_queue *rxq, u32 value) |
| 1069 | { |
| 1070 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), |
| 1071 | value | MVNETA_RXQ_NON_OCCUPIED(0)); |
| 1072 | rxq->pkts_coal = value; |
| 1073 | } |
| 1074 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1075 | /* Set the time delay in usec before RX interrupt will be generated by |
| 1076 | * HW. |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1077 | */ |
| 1078 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, |
| 1079 | struct mvneta_rx_queue *rxq, u32 value) |
| 1080 | { |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 1081 | u32 val; |
| 1082 | unsigned long clk_rate; |
| 1083 | |
| 1084 | clk_rate = clk_get_rate(pp->clk); |
| 1085 | val = (clk_rate / 1000000) * value; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1086 | |
| 1087 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); |
| 1088 | rxq->time_coal = value; |
| 1089 | } |
| 1090 | |
| 1091 | /* Set threshold for TX_DONE pkts coalescing */ |
| 1092 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, |
| 1093 | struct mvneta_tx_queue *txq, u32 value) |
| 1094 | { |
| 1095 | u32 val; |
| 1096 | |
| 1097 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); |
| 1098 | |
| 1099 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; |
| 1100 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); |
| 1101 | |
| 1102 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); |
| 1103 | |
| 1104 | txq->done_pkts_coal = value; |
| 1105 | } |
| 1106 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1107 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
| 1108 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, |
| 1109 | u32 phys_addr, u32 cookie) |
| 1110 | { |
| 1111 | rx_desc->buf_cookie = cookie; |
| 1112 | rx_desc->buf_phys_addr = phys_addr; |
| 1113 | } |
| 1114 | |
| 1115 | /* Decrement sent descriptors counter */ |
| 1116 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, |
| 1117 | struct mvneta_tx_queue *txq, |
| 1118 | int sent_desc) |
| 1119 | { |
| 1120 | u32 val; |
| 1121 | |
| 1122 | /* Only 255 TX descriptors can be updated at once */ |
| 1123 | while (sent_desc > 0xff) { |
| 1124 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; |
| 1125 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
| 1126 | sent_desc = sent_desc - 0xff; |
| 1127 | } |
| 1128 | |
| 1129 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; |
| 1130 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
| 1131 | } |
| 1132 | |
| 1133 | /* Get number of TX descriptors already sent by HW */ |
| 1134 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, |
| 1135 | struct mvneta_tx_queue *txq) |
| 1136 | { |
| 1137 | u32 val; |
| 1138 | int sent_desc; |
| 1139 | |
| 1140 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); |
| 1141 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> |
| 1142 | MVNETA_TXQ_SENT_DESC_SHIFT; |
| 1143 | |
| 1144 | return sent_desc; |
| 1145 | } |
| 1146 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1147 | /* Get number of sent descriptors and decrement counter. |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1148 | * The number of sent descriptors is returned. |
| 1149 | */ |
| 1150 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, |
| 1151 | struct mvneta_tx_queue *txq) |
| 1152 | { |
| 1153 | int sent_desc; |
| 1154 | |
| 1155 | /* Get number of sent descriptors */ |
| 1156 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); |
| 1157 | |
| 1158 | /* Decrement sent descriptors counter */ |
| 1159 | if (sent_desc) |
| 1160 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); |
| 1161 | |
| 1162 | return sent_desc; |
| 1163 | } |
| 1164 | |
| 1165 | /* Set TXQ descriptors fields relevant for CSUM calculation */ |
| 1166 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, |
| 1167 | int ip_hdr_len, int l4_proto) |
| 1168 | { |
| 1169 | u32 command; |
| 1170 | |
| 1171 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1172 | * G_L4_chk, L4_type; required only for checksum |
| 1173 | * calculation |
| 1174 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1175 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
| 1176 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; |
| 1177 | |
Thomas Fitzsimmons | ba502e1 | 2014-07-08 19:44:07 -0400 | [diff] [blame] | 1178 | if (l3_proto == htons(ETH_P_IP)) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1179 | command |= MVNETA_TXD_IP_CSUM; |
| 1180 | else |
| 1181 | command |= MVNETA_TX_L3_IP6; |
| 1182 | |
| 1183 | if (l4_proto == IPPROTO_TCP) |
| 1184 | command |= MVNETA_TX_L4_CSUM_FULL; |
| 1185 | else if (l4_proto == IPPROTO_UDP) |
| 1186 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; |
| 1187 | else |
| 1188 | command |= MVNETA_TX_L4_CSUM_NOT; |
| 1189 | |
| 1190 | return command; |
| 1191 | } |
| 1192 | |
| 1193 | |
| 1194 | /* Display more error info */ |
| 1195 | static void mvneta_rx_error(struct mvneta_port *pp, |
| 1196 | struct mvneta_rx_desc *rx_desc) |
| 1197 | { |
| 1198 | u32 status = rx_desc->status; |
| 1199 | |
| 1200 | if (!mvneta_rxq_desc_is_first_last(rx_desc)) { |
| 1201 | netdev_err(pp->dev, |
| 1202 | "bad rx status %08x (buffer oversize), size=%d\n", |
| 1203 | rx_desc->status, rx_desc->data_size); |
| 1204 | return; |
| 1205 | } |
| 1206 | |
| 1207 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { |
| 1208 | case MVNETA_RXD_ERR_CRC: |
| 1209 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", |
| 1210 | status, rx_desc->data_size); |
| 1211 | break; |
| 1212 | case MVNETA_RXD_ERR_OVERRUN: |
| 1213 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", |
| 1214 | status, rx_desc->data_size); |
| 1215 | break; |
| 1216 | case MVNETA_RXD_ERR_LEN: |
| 1217 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", |
| 1218 | status, rx_desc->data_size); |
| 1219 | break; |
| 1220 | case MVNETA_RXD_ERR_RESOURCE: |
| 1221 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", |
| 1222 | status, rx_desc->data_size); |
| 1223 | break; |
| 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | /* Handle RX checksum offload */ |
| 1228 | static void mvneta_rx_csum(struct mvneta_port *pp, |
| 1229 | struct mvneta_rx_desc *rx_desc, |
| 1230 | struct sk_buff *skb) |
| 1231 | { |
| 1232 | if ((rx_desc->status & MVNETA_RXD_L3_IP4) && |
| 1233 | (rx_desc->status & MVNETA_RXD_L4_CSUM_OK)) { |
| 1234 | skb->csum = 0; |
| 1235 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1236 | return; |
| 1237 | } |
| 1238 | |
| 1239 | skb->ip_summed = CHECKSUM_NONE; |
| 1240 | } |
| 1241 | |
| 1242 | /* Return tx queue pointer (find last set bit) according to causeTxDone reg */ |
| 1243 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
| 1244 | u32 cause) |
| 1245 | { |
| 1246 | int queue = fls(cause) - 1; |
| 1247 | |
| 1248 | return (queue < 0 || queue >= txq_number) ? NULL : &pp->txqs[queue]; |
| 1249 | } |
| 1250 | |
| 1251 | /* Free tx queue skbuffs */ |
| 1252 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, |
| 1253 | struct mvneta_tx_queue *txq, int num) |
| 1254 | { |
| 1255 | int i; |
| 1256 | |
| 1257 | for (i = 0; i < num; i++) { |
| 1258 | struct mvneta_tx_desc *tx_desc = txq->descs + |
| 1259 | txq->txq_get_index; |
| 1260 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; |
| 1261 | |
| 1262 | mvneta_txq_inc_get(txq); |
| 1263 | |
| 1264 | if (!skb) |
| 1265 | continue; |
| 1266 | |
| 1267 | dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr, |
| 1268 | tx_desc->data_size, DMA_TO_DEVICE); |
| 1269 | dev_kfree_skb_any(skb); |
| 1270 | } |
| 1271 | } |
| 1272 | |
| 1273 | /* Handle end of transmission */ |
| 1274 | static int mvneta_txq_done(struct mvneta_port *pp, |
| 1275 | struct mvneta_tx_queue *txq) |
| 1276 | { |
| 1277 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
| 1278 | int tx_done; |
| 1279 | |
| 1280 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); |
| 1281 | if (tx_done == 0) |
| 1282 | return tx_done; |
| 1283 | mvneta_txq_bufs_free(pp, txq, tx_done); |
| 1284 | |
| 1285 | txq->count -= tx_done; |
| 1286 | |
| 1287 | if (netif_tx_queue_stopped(nq)) { |
| 1288 | if (txq->size - txq->count >= MAX_SKB_FRAGS + 1) |
| 1289 | netif_tx_wake_queue(nq); |
| 1290 | } |
| 1291 | |
| 1292 | return tx_done; |
| 1293 | } |
| 1294 | |
| 1295 | /* Refill processing */ |
| 1296 | static int mvneta_rx_refill(struct mvneta_port *pp, |
| 1297 | struct mvneta_rx_desc *rx_desc) |
| 1298 | |
| 1299 | { |
| 1300 | dma_addr_t phys_addr; |
| 1301 | struct sk_buff *skb; |
| 1302 | |
| 1303 | skb = netdev_alloc_skb(pp->dev, pp->pkt_size); |
| 1304 | if (!skb) |
| 1305 | return -ENOMEM; |
| 1306 | |
| 1307 | phys_addr = dma_map_single(pp->dev->dev.parent, skb->head, |
| 1308 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
| 1309 | DMA_FROM_DEVICE); |
| 1310 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { |
| 1311 | dev_kfree_skb(skb); |
| 1312 | return -ENOMEM; |
| 1313 | } |
| 1314 | |
| 1315 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb); |
| 1316 | |
| 1317 | return 0; |
| 1318 | } |
| 1319 | |
| 1320 | /* Handle tx checksum */ |
| 1321 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) |
| 1322 | { |
| 1323 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 1324 | int ip_hdr_len = 0; |
| 1325 | u8 l4_proto; |
| 1326 | |
| 1327 | if (skb->protocol == htons(ETH_P_IP)) { |
| 1328 | struct iphdr *ip4h = ip_hdr(skb); |
| 1329 | |
| 1330 | /* Calculate IPv4 checksum and L4 checksum */ |
| 1331 | ip_hdr_len = ip4h->ihl; |
| 1332 | l4_proto = ip4h->protocol; |
| 1333 | } else if (skb->protocol == htons(ETH_P_IPV6)) { |
| 1334 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
| 1335 | |
| 1336 | /* Read l4_protocol from one of IPv6 extra headers */ |
| 1337 | if (skb_network_header_len(skb) > 0) |
| 1338 | ip_hdr_len = (skb_network_header_len(skb) >> 2); |
| 1339 | l4_proto = ip6h->nexthdr; |
| 1340 | } else |
| 1341 | return MVNETA_TX_L4_CSUM_NOT; |
| 1342 | |
| 1343 | return mvneta_txq_desc_csum(skb_network_offset(skb), |
| 1344 | skb->protocol, ip_hdr_len, l4_proto); |
| 1345 | } |
| 1346 | |
| 1347 | return MVNETA_TX_L4_CSUM_NOT; |
| 1348 | } |
| 1349 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1350 | /* Returns rx queue pointer (find last set bit) according to causeRxTx |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1351 | * value |
| 1352 | */ |
| 1353 | static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp, |
| 1354 | u32 cause) |
| 1355 | { |
| 1356 | int queue = fls(cause >> 8) - 1; |
| 1357 | |
| 1358 | return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue]; |
| 1359 | } |
| 1360 | |
| 1361 | /* Drop packets received by the RXQ and free buffers */ |
| 1362 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, |
| 1363 | struct mvneta_rx_queue *rxq) |
| 1364 | { |
| 1365 | int rx_done, i; |
| 1366 | |
| 1367 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); |
| 1368 | for (i = 0; i < rxq->size; i++) { |
| 1369 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; |
| 1370 | struct sk_buff *skb = (struct sk_buff *)rx_desc->buf_cookie; |
| 1371 | |
| 1372 | dev_kfree_skb_any(skb); |
| 1373 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
| 1374 | rx_desc->data_size, DMA_FROM_DEVICE); |
| 1375 | } |
| 1376 | |
| 1377 | if (rx_done) |
| 1378 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
| 1379 | } |
| 1380 | |
| 1381 | /* Main rx processing */ |
| 1382 | static int mvneta_rx(struct mvneta_port *pp, int rx_todo, |
| 1383 | struct mvneta_rx_queue *rxq) |
| 1384 | { |
| 1385 | struct net_device *dev = pp->dev; |
| 1386 | int rx_done, rx_filled; |
willy tarreau | 5831364 | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1387 | u32 rcvd_pkts = 0; |
| 1388 | u32 rcvd_bytes = 0; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1389 | |
| 1390 | /* Get number of received packets */ |
| 1391 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); |
| 1392 | |
| 1393 | if (rx_todo > rx_done) |
| 1394 | rx_todo = rx_done; |
| 1395 | |
| 1396 | rx_done = 0; |
| 1397 | rx_filled = 0; |
| 1398 | |
| 1399 | /* Fairness NAPI loop */ |
| 1400 | while (rx_done < rx_todo) { |
| 1401 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); |
| 1402 | struct sk_buff *skb; |
| 1403 | u32 rx_status; |
| 1404 | int rx_bytes, err; |
| 1405 | |
| 1406 | prefetch(rx_desc); |
| 1407 | rx_done++; |
| 1408 | rx_filled++; |
| 1409 | rx_status = rx_desc->status; |
| 1410 | skb = (struct sk_buff *)rx_desc->buf_cookie; |
| 1411 | |
| 1412 | if (!mvneta_rxq_desc_is_first_last(rx_desc) || |
| 1413 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
| 1414 | dev->stats.rx_errors++; |
| 1415 | mvneta_rx_error(pp, rx_desc); |
| 1416 | mvneta_rx_desc_fill(rx_desc, rx_desc->buf_phys_addr, |
| 1417 | (u32)skb); |
| 1418 | continue; |
| 1419 | } |
| 1420 | |
| 1421 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
| 1422 | rx_desc->data_size, DMA_FROM_DEVICE); |
| 1423 | |
| 1424 | rx_bytes = rx_desc->data_size - |
| 1425 | (ETH_FCS_LEN + MVNETA_MH_SIZE); |
willy tarreau | 5831364 | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1426 | rcvd_pkts++; |
| 1427 | rcvd_bytes += rx_bytes; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1428 | |
| 1429 | /* Linux processing */ |
| 1430 | skb_reserve(skb, MVNETA_MH_SIZE); |
| 1431 | skb_put(skb, rx_bytes); |
| 1432 | |
| 1433 | skb->protocol = eth_type_trans(skb, dev); |
| 1434 | |
| 1435 | mvneta_rx_csum(pp, rx_desc, skb); |
| 1436 | |
| 1437 | napi_gro_receive(&pp->napi, skb); |
| 1438 | |
| 1439 | /* Refill processing */ |
| 1440 | err = mvneta_rx_refill(pp, rx_desc); |
| 1441 | if (err) { |
| 1442 | netdev_err(pp->dev, "Linux processing - Can't refill\n"); |
| 1443 | rxq->missed++; |
| 1444 | rx_filled--; |
| 1445 | } |
| 1446 | } |
| 1447 | |
willy tarreau | 5831364 | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1448 | if (rcvd_pkts) { |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1449 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
| 1450 | |
| 1451 | u64_stats_update_begin(&stats->syncp); |
| 1452 | stats->rx_packets += rcvd_pkts; |
| 1453 | stats->rx_bytes += rcvd_bytes; |
| 1454 | u64_stats_update_end(&stats->syncp); |
willy tarreau | 5831364 | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1455 | } |
| 1456 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1457 | /* Update rxq management counters */ |
| 1458 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled); |
| 1459 | |
| 1460 | return rx_done; |
| 1461 | } |
| 1462 | |
| 1463 | /* Handle tx fragmentation processing */ |
| 1464 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, |
| 1465 | struct mvneta_tx_queue *txq) |
| 1466 | { |
| 1467 | struct mvneta_tx_desc *tx_desc; |
| 1468 | int i; |
| 1469 | |
| 1470 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 1471 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 1472 | void *addr = page_address(frag->page.p) + frag->page_offset; |
| 1473 | |
| 1474 | tx_desc = mvneta_txq_next_desc_get(txq); |
| 1475 | tx_desc->data_size = frag->size; |
| 1476 | |
| 1477 | tx_desc->buf_phys_addr = |
| 1478 | dma_map_single(pp->dev->dev.parent, addr, |
| 1479 | tx_desc->data_size, DMA_TO_DEVICE); |
| 1480 | |
| 1481 | if (dma_mapping_error(pp->dev->dev.parent, |
| 1482 | tx_desc->buf_phys_addr)) { |
| 1483 | mvneta_txq_desc_put(txq); |
| 1484 | goto error; |
| 1485 | } |
| 1486 | |
| 1487 | if (i == (skb_shinfo(skb)->nr_frags - 1)) { |
| 1488 | /* Last descriptor */ |
| 1489 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; |
| 1490 | |
| 1491 | txq->tx_skb[txq->txq_put_index] = skb; |
| 1492 | |
| 1493 | mvneta_txq_inc_put(txq); |
| 1494 | } else { |
| 1495 | /* Descriptor in the middle: Not First, Not Last */ |
| 1496 | tx_desc->command = 0; |
| 1497 | |
| 1498 | txq->tx_skb[txq->txq_put_index] = NULL; |
| 1499 | mvneta_txq_inc_put(txq); |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | return 0; |
| 1504 | |
| 1505 | error: |
| 1506 | /* Release all descriptors that were used to map fragments of |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1507 | * this packet, as well as the corresponding DMA mappings |
| 1508 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1509 | for (i = i - 1; i >= 0; i--) { |
| 1510 | tx_desc = txq->descs + i; |
| 1511 | dma_unmap_single(pp->dev->dev.parent, |
| 1512 | tx_desc->buf_phys_addr, |
| 1513 | tx_desc->data_size, |
| 1514 | DMA_TO_DEVICE); |
| 1515 | mvneta_txq_desc_put(txq); |
| 1516 | } |
| 1517 | |
| 1518 | return -ENOMEM; |
| 1519 | } |
| 1520 | |
| 1521 | /* Main tx processing */ |
| 1522 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) |
| 1523 | { |
| 1524 | struct mvneta_port *pp = netdev_priv(dev); |
Willy Tarreau | ee40a11 | 2013-04-11 23:00:37 +0200 | [diff] [blame] | 1525 | u16 txq_id = skb_get_queue_mapping(skb); |
| 1526 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1527 | struct mvneta_tx_desc *tx_desc; |
| 1528 | struct netdev_queue *nq; |
| 1529 | int frags = 0; |
| 1530 | u32 tx_cmd; |
| 1531 | |
| 1532 | if (!netif_running(dev)) |
| 1533 | goto out; |
| 1534 | |
| 1535 | frags = skb_shinfo(skb)->nr_frags + 1; |
Willy Tarreau | ee40a11 | 2013-04-11 23:00:37 +0200 | [diff] [blame] | 1536 | nq = netdev_get_tx_queue(dev, txq_id); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1537 | |
| 1538 | /* Get a descriptor for the first part of the packet */ |
| 1539 | tx_desc = mvneta_txq_next_desc_get(txq); |
| 1540 | |
| 1541 | tx_cmd = mvneta_skb_tx_csum(pp, skb); |
| 1542 | |
| 1543 | tx_desc->data_size = skb_headlen(skb); |
| 1544 | |
| 1545 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, |
| 1546 | tx_desc->data_size, |
| 1547 | DMA_TO_DEVICE); |
| 1548 | if (unlikely(dma_mapping_error(dev->dev.parent, |
| 1549 | tx_desc->buf_phys_addr))) { |
| 1550 | mvneta_txq_desc_put(txq); |
| 1551 | frags = 0; |
| 1552 | goto out; |
| 1553 | } |
| 1554 | |
| 1555 | if (frags == 1) { |
| 1556 | /* First and Last descriptor */ |
| 1557 | tx_cmd |= MVNETA_TXD_FLZ_DESC; |
| 1558 | tx_desc->command = tx_cmd; |
| 1559 | txq->tx_skb[txq->txq_put_index] = skb; |
| 1560 | mvneta_txq_inc_put(txq); |
| 1561 | } else { |
| 1562 | /* First but not Last */ |
| 1563 | tx_cmd |= MVNETA_TXD_F_DESC; |
| 1564 | txq->tx_skb[txq->txq_put_index] = NULL; |
| 1565 | mvneta_txq_inc_put(txq); |
| 1566 | tx_desc->command = tx_cmd; |
| 1567 | /* Continue with other skb fragments */ |
| 1568 | if (mvneta_tx_frag_process(pp, skb, txq)) { |
| 1569 | dma_unmap_single(dev->dev.parent, |
| 1570 | tx_desc->buf_phys_addr, |
| 1571 | tx_desc->data_size, |
| 1572 | DMA_TO_DEVICE); |
| 1573 | mvneta_txq_desc_put(txq); |
| 1574 | frags = 0; |
| 1575 | goto out; |
| 1576 | } |
| 1577 | } |
| 1578 | |
| 1579 | txq->count += frags; |
| 1580 | mvneta_txq_pend_desc_add(pp, txq, frags); |
| 1581 | |
| 1582 | if (txq->size - txq->count < MAX_SKB_FRAGS + 1) |
| 1583 | netif_tx_stop_queue(nq); |
| 1584 | |
| 1585 | out: |
| 1586 | if (frags > 0) { |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1587 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1588 | |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1589 | u64_stats_update_begin(&stats->syncp); |
| 1590 | stats->tx_packets++; |
| 1591 | stats->tx_bytes += skb->len; |
| 1592 | u64_stats_update_end(&stats->syncp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1593 | } else { |
| 1594 | dev->stats.tx_dropped++; |
| 1595 | dev_kfree_skb_any(skb); |
| 1596 | } |
| 1597 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1598 | return NETDEV_TX_OK; |
| 1599 | } |
| 1600 | |
| 1601 | |
| 1602 | /* Free tx resources, when resetting a port */ |
| 1603 | static void mvneta_txq_done_force(struct mvneta_port *pp, |
| 1604 | struct mvneta_tx_queue *txq) |
| 1605 | |
| 1606 | { |
| 1607 | int tx_done = txq->count; |
| 1608 | |
| 1609 | mvneta_txq_bufs_free(pp, txq, tx_done); |
| 1610 | |
| 1611 | /* reset txq */ |
| 1612 | txq->count = 0; |
| 1613 | txq->txq_put_index = 0; |
| 1614 | txq->txq_get_index = 0; |
| 1615 | } |
| 1616 | |
| 1617 | /* handle tx done - called from tx done timer callback */ |
| 1618 | static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done, |
| 1619 | int *tx_todo) |
| 1620 | { |
| 1621 | struct mvneta_tx_queue *txq; |
| 1622 | u32 tx_done = 0; |
| 1623 | struct netdev_queue *nq; |
| 1624 | |
| 1625 | *tx_todo = 0; |
| 1626 | while (cause_tx_done != 0) { |
| 1627 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
| 1628 | if (!txq) |
| 1629 | break; |
| 1630 | |
| 1631 | nq = netdev_get_tx_queue(pp->dev, txq->id); |
| 1632 | __netif_tx_lock(nq, smp_processor_id()); |
| 1633 | |
| 1634 | if (txq->count) { |
| 1635 | tx_done += mvneta_txq_done(pp, txq); |
| 1636 | *tx_todo += txq->count; |
| 1637 | } |
| 1638 | |
| 1639 | __netif_tx_unlock(nq); |
| 1640 | cause_tx_done &= ~((1 << txq->id)); |
| 1641 | } |
| 1642 | |
| 1643 | return tx_done; |
| 1644 | } |
| 1645 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1646 | /* Compute crc8 of the specified address, using a unique algorithm , |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1647 | * according to hw spec, different than generic crc8 algorithm |
| 1648 | */ |
| 1649 | static int mvneta_addr_crc(unsigned char *addr) |
| 1650 | { |
| 1651 | int crc = 0; |
| 1652 | int i; |
| 1653 | |
| 1654 | for (i = 0; i < ETH_ALEN; i++) { |
| 1655 | int j; |
| 1656 | |
| 1657 | crc = (crc ^ addr[i]) << 8; |
| 1658 | for (j = 7; j >= 0; j--) { |
| 1659 | if (crc & (0x100 << j)) |
| 1660 | crc ^= 0x107 << j; |
| 1661 | } |
| 1662 | } |
| 1663 | |
| 1664 | return crc; |
| 1665 | } |
| 1666 | |
| 1667 | /* This method controls the net device special MAC multicast support. |
| 1668 | * The Special Multicast Table for MAC addresses supports MAC of the form |
| 1669 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). |
| 1670 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast |
| 1671 | * Table entries in the DA-Filter table. This method set the Special |
| 1672 | * Multicast Table appropriate entry. |
| 1673 | */ |
| 1674 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, |
| 1675 | unsigned char last_byte, |
| 1676 | int queue) |
| 1677 | { |
| 1678 | unsigned int smc_table_reg; |
| 1679 | unsigned int tbl_offset; |
| 1680 | unsigned int reg_offset; |
| 1681 | |
| 1682 | /* Register offset from SMC table base */ |
| 1683 | tbl_offset = (last_byte / 4); |
| 1684 | /* Entry offset within the above reg */ |
| 1685 | reg_offset = last_byte % 4; |
| 1686 | |
| 1687 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST |
| 1688 | + tbl_offset * 4)); |
| 1689 | |
| 1690 | if (queue == -1) |
| 1691 | smc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1692 | else { |
| 1693 | smc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1694 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); |
| 1695 | } |
| 1696 | |
| 1697 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, |
| 1698 | smc_table_reg); |
| 1699 | } |
| 1700 | |
| 1701 | /* This method controls the network device Other MAC multicast support. |
| 1702 | * The Other Multicast Table is used for multicast of another type. |
| 1703 | * A CRC-8 is used as an index to the Other Multicast Table entries |
| 1704 | * in the DA-Filter table. |
| 1705 | * The method gets the CRC-8 value from the calling routine and |
| 1706 | * sets the Other Multicast Table appropriate entry according to the |
| 1707 | * specified CRC-8 . |
| 1708 | */ |
| 1709 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, |
| 1710 | unsigned char crc8, |
| 1711 | int queue) |
| 1712 | { |
| 1713 | unsigned int omc_table_reg; |
| 1714 | unsigned int tbl_offset; |
| 1715 | unsigned int reg_offset; |
| 1716 | |
| 1717 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ |
| 1718 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ |
| 1719 | |
| 1720 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); |
| 1721 | |
| 1722 | if (queue == -1) { |
| 1723 | /* Clear accepts frame bit at specified Other DA table entry */ |
| 1724 | omc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1725 | } else { |
| 1726 | omc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1727 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); |
| 1728 | } |
| 1729 | |
| 1730 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); |
| 1731 | } |
| 1732 | |
| 1733 | /* The network device supports multicast using two tables: |
| 1734 | * 1) Special Multicast Table for MAC addresses of the form |
| 1735 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). |
| 1736 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast |
| 1737 | * Table entries in the DA-Filter table. |
| 1738 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value |
| 1739 | * is used as an index to the Other Multicast Table entries in the |
| 1740 | * DA-Filter table. |
| 1741 | */ |
| 1742 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, |
| 1743 | int queue) |
| 1744 | { |
| 1745 | unsigned char crc_result = 0; |
| 1746 | |
| 1747 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { |
| 1748 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); |
| 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | crc_result = mvneta_addr_crc(p_addr); |
| 1753 | if (queue == -1) { |
| 1754 | if (pp->mcast_count[crc_result] == 0) { |
| 1755 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", |
| 1756 | crc_result); |
| 1757 | return -EINVAL; |
| 1758 | } |
| 1759 | |
| 1760 | pp->mcast_count[crc_result]--; |
| 1761 | if (pp->mcast_count[crc_result] != 0) { |
| 1762 | netdev_info(pp->dev, |
| 1763 | "After delete there are %d valid Mcast for crc8=0x%02x\n", |
| 1764 | pp->mcast_count[crc_result], crc_result); |
| 1765 | return -EINVAL; |
| 1766 | } |
| 1767 | } else |
| 1768 | pp->mcast_count[crc_result]++; |
| 1769 | |
| 1770 | mvneta_set_other_mcast_addr(pp, crc_result, queue); |
| 1771 | |
| 1772 | return 0; |
| 1773 | } |
| 1774 | |
| 1775 | /* Configure Fitering mode of Ethernet port */ |
| 1776 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, |
| 1777 | int is_promisc) |
| 1778 | { |
| 1779 | u32 port_cfg_reg, val; |
| 1780 | |
| 1781 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); |
| 1782 | |
| 1783 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); |
| 1784 | |
| 1785 | /* Set / Clear UPM bit in port configuration register */ |
| 1786 | if (is_promisc) { |
| 1787 | /* Accept all Unicast addresses */ |
| 1788 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; |
| 1789 | val |= MVNETA_FORCE_UNI; |
| 1790 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); |
| 1791 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); |
| 1792 | } else { |
| 1793 | /* Reject all Unicast addresses */ |
| 1794 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; |
| 1795 | val &= ~MVNETA_FORCE_UNI; |
| 1796 | } |
| 1797 | |
| 1798 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); |
| 1799 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); |
| 1800 | } |
| 1801 | |
| 1802 | /* register unicast and multicast addresses */ |
| 1803 | static void mvneta_set_rx_mode(struct net_device *dev) |
| 1804 | { |
| 1805 | struct mvneta_port *pp = netdev_priv(dev); |
| 1806 | struct netdev_hw_addr *ha; |
| 1807 | |
| 1808 | if (dev->flags & IFF_PROMISC) { |
| 1809 | /* Accept all: Multicast + Unicast */ |
| 1810 | mvneta_rx_unicast_promisc_set(pp, 1); |
| 1811 | mvneta_set_ucast_table(pp, rxq_def); |
| 1812 | mvneta_set_special_mcast_table(pp, rxq_def); |
| 1813 | mvneta_set_other_mcast_table(pp, rxq_def); |
| 1814 | } else { |
| 1815 | /* Accept single Unicast */ |
| 1816 | mvneta_rx_unicast_promisc_set(pp, 0); |
| 1817 | mvneta_set_ucast_table(pp, -1); |
| 1818 | mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); |
| 1819 | |
| 1820 | if (dev->flags & IFF_ALLMULTI) { |
| 1821 | /* Accept all multicast */ |
| 1822 | mvneta_set_special_mcast_table(pp, rxq_def); |
| 1823 | mvneta_set_other_mcast_table(pp, rxq_def); |
| 1824 | } else { |
| 1825 | /* Accept only initialized multicast */ |
| 1826 | mvneta_set_special_mcast_table(pp, -1); |
| 1827 | mvneta_set_other_mcast_table(pp, -1); |
| 1828 | |
| 1829 | if (!netdev_mc_empty(dev)) { |
| 1830 | netdev_for_each_mc_addr(ha, dev) { |
| 1831 | mvneta_mcast_addr_set(pp, ha->addr, |
| 1832 | rxq_def); |
| 1833 | } |
| 1834 | } |
| 1835 | } |
| 1836 | } |
| 1837 | } |
| 1838 | |
| 1839 | /* Interrupt handling - the callback for request_irq() */ |
| 1840 | static irqreturn_t mvneta_isr(int irq, void *dev_id) |
| 1841 | { |
| 1842 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; |
| 1843 | |
| 1844 | /* Mask all interrupts */ |
| 1845 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 1846 | |
| 1847 | napi_schedule(&pp->napi); |
| 1848 | |
| 1849 | return IRQ_HANDLED; |
| 1850 | } |
| 1851 | |
| 1852 | /* NAPI handler |
| 1853 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted |
| 1854 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). |
| 1855 | * Bits 8 -15 of the cause Rx Tx register indicate that are received |
| 1856 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). |
| 1857 | * Each CPU has its own causeRxTx register |
| 1858 | */ |
| 1859 | static int mvneta_poll(struct napi_struct *napi, int budget) |
| 1860 | { |
| 1861 | int rx_done = 0; |
| 1862 | u32 cause_rx_tx; |
| 1863 | unsigned long flags; |
| 1864 | struct mvneta_port *pp = netdev_priv(napi->dev); |
| 1865 | |
| 1866 | if (!netif_running(pp->dev)) { |
| 1867 | napi_complete(napi); |
| 1868 | return rx_done; |
| 1869 | } |
| 1870 | |
| 1871 | /* Read cause register */ |
| 1872 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) & |
willy tarreau | a733b53 | 2014-01-16 08:20:11 +0100 | [diff] [blame] | 1873 | (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); |
| 1874 | |
| 1875 | /* Release Tx descriptors */ |
| 1876 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { |
| 1877 | int tx_todo = 0; |
| 1878 | |
| 1879 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL), &tx_todo); |
| 1880 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
| 1881 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1882 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1883 | /* For the case where the last mvneta_poll did not process all |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1884 | * RX packets |
| 1885 | */ |
| 1886 | cause_rx_tx |= pp->cause_rx_tx; |
| 1887 | if (rxq_number > 1) { |
willy tarreau | a733b53 | 2014-01-16 08:20:11 +0100 | [diff] [blame] | 1888 | while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1889 | int count; |
| 1890 | struct mvneta_rx_queue *rxq; |
| 1891 | /* get rx queue number from cause_rx_tx */ |
| 1892 | rxq = mvneta_rx_policy(pp, cause_rx_tx); |
| 1893 | if (!rxq) |
| 1894 | break; |
| 1895 | |
| 1896 | /* process the packet in that rx queue */ |
| 1897 | count = mvneta_rx(pp, budget, rxq); |
| 1898 | rx_done += count; |
| 1899 | budget -= count; |
| 1900 | if (budget > 0) { |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1901 | /* set off the rx bit of the |
| 1902 | * corresponding bit in the cause rx |
| 1903 | * tx register, so that next iteration |
| 1904 | * will find the next rx queue where |
| 1905 | * packets are received on |
| 1906 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1907 | cause_rx_tx &= ~((1 << rxq->id) << 8); |
| 1908 | } |
| 1909 | } |
| 1910 | } else { |
| 1911 | rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); |
| 1912 | budget -= rx_done; |
| 1913 | } |
| 1914 | |
| 1915 | if (budget > 0) { |
| 1916 | cause_rx_tx = 0; |
| 1917 | napi_complete(napi); |
| 1918 | local_irq_save(flags); |
| 1919 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, |
willy tarreau | a733b53 | 2014-01-16 08:20:11 +0100 | [diff] [blame] | 1920 | MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1921 | local_irq_restore(flags); |
| 1922 | } |
| 1923 | |
| 1924 | pp->cause_rx_tx = cause_rx_tx; |
| 1925 | return rx_done; |
| 1926 | } |
| 1927 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1928 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
| 1929 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, |
| 1930 | int num) |
| 1931 | { |
| 1932 | struct net_device *dev = pp->dev; |
| 1933 | int i; |
| 1934 | |
| 1935 | for (i = 0; i < num; i++) { |
| 1936 | struct sk_buff *skb; |
| 1937 | struct mvneta_rx_desc *rx_desc; |
| 1938 | unsigned long phys_addr; |
| 1939 | |
| 1940 | skb = dev_alloc_skb(pp->pkt_size); |
| 1941 | if (!skb) { |
| 1942 | netdev_err(dev, "%s:rxq %d, %d of %d buffs filled\n", |
| 1943 | __func__, rxq->id, i, num); |
| 1944 | break; |
| 1945 | } |
| 1946 | |
| 1947 | rx_desc = rxq->descs + i; |
| 1948 | memset(rx_desc, 0, sizeof(struct mvneta_rx_desc)); |
| 1949 | phys_addr = dma_map_single(dev->dev.parent, skb->head, |
| 1950 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
| 1951 | DMA_FROM_DEVICE); |
| 1952 | if (unlikely(dma_mapping_error(dev->dev.parent, phys_addr))) { |
| 1953 | dev_kfree_skb(skb); |
| 1954 | break; |
| 1955 | } |
| 1956 | |
| 1957 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb); |
| 1958 | } |
| 1959 | |
| 1960 | /* Add this number of RX descriptors as non occupied (ready to |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1961 | * get packets) |
| 1962 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1963 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
| 1964 | |
| 1965 | return i; |
| 1966 | } |
| 1967 | |
| 1968 | /* Free all packets pending transmit from all TXQs and reset TX port */ |
| 1969 | static void mvneta_tx_reset(struct mvneta_port *pp) |
| 1970 | { |
| 1971 | int queue; |
| 1972 | |
| 1973 | /* free the skb's in the hal tx ring */ |
| 1974 | for (queue = 0; queue < txq_number; queue++) |
| 1975 | mvneta_txq_done_force(pp, &pp->txqs[queue]); |
| 1976 | |
| 1977 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); |
| 1978 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); |
| 1979 | } |
| 1980 | |
| 1981 | static void mvneta_rx_reset(struct mvneta_port *pp) |
| 1982 | { |
| 1983 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); |
| 1984 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); |
| 1985 | } |
| 1986 | |
| 1987 | /* Rx/Tx queue initialization/cleanup methods */ |
| 1988 | |
| 1989 | /* Create a specified RX queue */ |
| 1990 | static int mvneta_rxq_init(struct mvneta_port *pp, |
| 1991 | struct mvneta_rx_queue *rxq) |
| 1992 | |
| 1993 | { |
| 1994 | rxq->size = pp->rx_ring_size; |
| 1995 | |
| 1996 | /* Allocate memory for RX descriptors */ |
| 1997 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, |
| 1998 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 1999 | &rxq->descs_phys, GFP_KERNEL); |
Joe Perches | d0320f7 | 2013-03-14 13:07:21 +0000 | [diff] [blame] | 2000 | if (rxq->descs == NULL) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2001 | return -ENOMEM; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2002 | |
| 2003 | BUG_ON(rxq->descs != |
| 2004 | PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); |
| 2005 | |
| 2006 | rxq->last_desc = rxq->size - 1; |
| 2007 | |
| 2008 | /* Set Rx descriptors queue starting address */ |
| 2009 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); |
| 2010 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); |
| 2011 | |
| 2012 | /* Set Offset */ |
| 2013 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); |
| 2014 | |
| 2015 | /* Set coalescing pkts and time */ |
| 2016 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); |
| 2017 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); |
| 2018 | |
| 2019 | /* Fill RXQ with buffers from RX pool */ |
| 2020 | mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); |
| 2021 | mvneta_rxq_bm_disable(pp, rxq); |
| 2022 | mvneta_rxq_fill(pp, rxq, rxq->size); |
| 2023 | |
| 2024 | return 0; |
| 2025 | } |
| 2026 | |
| 2027 | /* Cleanup Rx queue */ |
| 2028 | static void mvneta_rxq_deinit(struct mvneta_port *pp, |
| 2029 | struct mvneta_rx_queue *rxq) |
| 2030 | { |
| 2031 | mvneta_rxq_drop_pkts(pp, rxq); |
| 2032 | |
| 2033 | if (rxq->descs) |
| 2034 | dma_free_coherent(pp->dev->dev.parent, |
| 2035 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2036 | rxq->descs, |
| 2037 | rxq->descs_phys); |
| 2038 | |
| 2039 | rxq->descs = NULL; |
| 2040 | rxq->last_desc = 0; |
| 2041 | rxq->next_desc_to_proc = 0; |
| 2042 | rxq->descs_phys = 0; |
| 2043 | } |
| 2044 | |
| 2045 | /* Create and initialize a tx queue */ |
| 2046 | static int mvneta_txq_init(struct mvneta_port *pp, |
| 2047 | struct mvneta_tx_queue *txq) |
| 2048 | { |
| 2049 | txq->size = pp->tx_ring_size; |
| 2050 | |
| 2051 | /* Allocate memory for TX descriptors */ |
| 2052 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, |
| 2053 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2054 | &txq->descs_phys, GFP_KERNEL); |
Joe Perches | d0320f7 | 2013-03-14 13:07:21 +0000 | [diff] [blame] | 2055 | if (txq->descs == NULL) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2056 | return -ENOMEM; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2057 | |
| 2058 | /* Make sure descriptor address is cache line size aligned */ |
| 2059 | BUG_ON(txq->descs != |
| 2060 | PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); |
| 2061 | |
| 2062 | txq->last_desc = txq->size - 1; |
| 2063 | |
| 2064 | /* Set maximum bandwidth for enabled TXQs */ |
| 2065 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); |
| 2066 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); |
| 2067 | |
| 2068 | /* Set Tx descriptors queue starting address */ |
| 2069 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); |
| 2070 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); |
| 2071 | |
| 2072 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); |
| 2073 | if (txq->tx_skb == NULL) { |
| 2074 | dma_free_coherent(pp->dev->dev.parent, |
| 2075 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2076 | txq->descs, txq->descs_phys); |
| 2077 | return -ENOMEM; |
| 2078 | } |
| 2079 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
| 2080 | |
| 2081 | return 0; |
| 2082 | } |
| 2083 | |
| 2084 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ |
| 2085 | static void mvneta_txq_deinit(struct mvneta_port *pp, |
| 2086 | struct mvneta_tx_queue *txq) |
| 2087 | { |
| 2088 | kfree(txq->tx_skb); |
| 2089 | |
| 2090 | if (txq->descs) |
| 2091 | dma_free_coherent(pp->dev->dev.parent, |
| 2092 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2093 | txq->descs, txq->descs_phys); |
| 2094 | |
| 2095 | txq->descs = NULL; |
| 2096 | txq->last_desc = 0; |
| 2097 | txq->next_desc_to_proc = 0; |
| 2098 | txq->descs_phys = 0; |
| 2099 | |
| 2100 | /* Set minimum bandwidth for disabled TXQs */ |
| 2101 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); |
| 2102 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); |
| 2103 | |
| 2104 | /* Set Tx descriptors queue starting address and size */ |
| 2105 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); |
| 2106 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); |
| 2107 | } |
| 2108 | |
| 2109 | /* Cleanup all Tx queues */ |
| 2110 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) |
| 2111 | { |
| 2112 | int queue; |
| 2113 | |
| 2114 | for (queue = 0; queue < txq_number; queue++) |
| 2115 | mvneta_txq_deinit(pp, &pp->txqs[queue]); |
| 2116 | } |
| 2117 | |
| 2118 | /* Cleanup all Rx queues */ |
| 2119 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) |
| 2120 | { |
| 2121 | int queue; |
| 2122 | |
| 2123 | for (queue = 0; queue < rxq_number; queue++) |
| 2124 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); |
| 2125 | } |
| 2126 | |
| 2127 | |
| 2128 | /* Init all Rx queues */ |
| 2129 | static int mvneta_setup_rxqs(struct mvneta_port *pp) |
| 2130 | { |
| 2131 | int queue; |
| 2132 | |
| 2133 | for (queue = 0; queue < rxq_number; queue++) { |
| 2134 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); |
| 2135 | if (err) { |
| 2136 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", |
| 2137 | __func__, queue); |
| 2138 | mvneta_cleanup_rxqs(pp); |
| 2139 | return err; |
| 2140 | } |
| 2141 | } |
| 2142 | |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
| 2146 | /* Init all tx queues */ |
| 2147 | static int mvneta_setup_txqs(struct mvneta_port *pp) |
| 2148 | { |
| 2149 | int queue; |
| 2150 | |
| 2151 | for (queue = 0; queue < txq_number; queue++) { |
| 2152 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); |
| 2153 | if (err) { |
| 2154 | netdev_err(pp->dev, "%s: can't create txq=%d\n", |
| 2155 | __func__, queue); |
| 2156 | mvneta_cleanup_txqs(pp); |
| 2157 | return err; |
| 2158 | } |
| 2159 | } |
| 2160 | |
| 2161 | return 0; |
| 2162 | } |
| 2163 | |
| 2164 | static void mvneta_start_dev(struct mvneta_port *pp) |
| 2165 | { |
| 2166 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
| 2167 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); |
| 2168 | |
| 2169 | /* start the Rx/Tx activity */ |
| 2170 | mvneta_port_enable(pp); |
| 2171 | |
| 2172 | /* Enable polling on the port */ |
| 2173 | napi_enable(&pp->napi); |
| 2174 | |
| 2175 | /* Unmask interrupts */ |
| 2176 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, |
willy tarreau | a733b53 | 2014-01-16 08:20:11 +0100 | [diff] [blame] | 2177 | MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2178 | |
| 2179 | phy_start(pp->phy_dev); |
| 2180 | netif_tx_start_all_queues(pp->dev); |
| 2181 | } |
| 2182 | |
| 2183 | static void mvneta_stop_dev(struct mvneta_port *pp) |
| 2184 | { |
| 2185 | phy_stop(pp->phy_dev); |
| 2186 | |
| 2187 | napi_disable(&pp->napi); |
| 2188 | |
| 2189 | netif_carrier_off(pp->dev); |
| 2190 | |
| 2191 | mvneta_port_down(pp); |
| 2192 | netif_tx_stop_all_queues(pp->dev); |
| 2193 | |
| 2194 | /* Stop the port activity */ |
| 2195 | mvneta_port_disable(pp); |
| 2196 | |
| 2197 | /* Clear all ethernet port interrupts */ |
| 2198 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); |
| 2199 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); |
| 2200 | |
| 2201 | /* Mask all ethernet port interrupts */ |
| 2202 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 2203 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); |
| 2204 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); |
| 2205 | |
| 2206 | mvneta_tx_reset(pp); |
| 2207 | mvneta_rx_reset(pp); |
| 2208 | } |
| 2209 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2210 | /* Return positive if MTU is valid */ |
| 2211 | static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) |
| 2212 | { |
| 2213 | if (mtu < 68) { |
| 2214 | netdev_err(dev, "cannot change mtu to less than 68\n"); |
| 2215 | return -EINVAL; |
| 2216 | } |
| 2217 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2218 | /* 9676 == 9700 - 20 and rounding to 8 */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2219 | if (mtu > 9676) { |
| 2220 | netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); |
| 2221 | mtu = 9676; |
| 2222 | } |
| 2223 | |
| 2224 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
| 2225 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", |
| 2226 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); |
| 2227 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); |
| 2228 | } |
| 2229 | |
| 2230 | return mtu; |
| 2231 | } |
| 2232 | |
| 2233 | /* Change the device mtu */ |
| 2234 | static int mvneta_change_mtu(struct net_device *dev, int mtu) |
| 2235 | { |
| 2236 | struct mvneta_port *pp = netdev_priv(dev); |
| 2237 | int ret; |
| 2238 | |
| 2239 | mtu = mvneta_check_mtu_valid(dev, mtu); |
| 2240 | if (mtu < 0) |
| 2241 | return -EINVAL; |
| 2242 | |
| 2243 | dev->mtu = mtu; |
| 2244 | |
| 2245 | if (!netif_running(dev)) |
| 2246 | return 0; |
| 2247 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2248 | /* The interface is running, so we have to force a |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2249 | * reallocation of the RXQs |
| 2250 | */ |
| 2251 | mvneta_stop_dev(pp); |
| 2252 | |
| 2253 | mvneta_cleanup_txqs(pp); |
| 2254 | mvneta_cleanup_rxqs(pp); |
| 2255 | |
| 2256 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
| 2257 | |
| 2258 | ret = mvneta_setup_rxqs(pp); |
| 2259 | if (ret) { |
| 2260 | netdev_err(pp->dev, "unable to setup rxqs after MTU change\n"); |
| 2261 | return ret; |
| 2262 | } |
| 2263 | |
| 2264 | mvneta_setup_txqs(pp); |
| 2265 | |
| 2266 | mvneta_start_dev(pp); |
| 2267 | mvneta_port_up(pp); |
| 2268 | |
| 2269 | return 0; |
| 2270 | } |
| 2271 | |
| 2272 | /* Handle setting mac address */ |
| 2273 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) |
| 2274 | { |
| 2275 | struct mvneta_port *pp = netdev_priv(dev); |
| 2276 | u8 *mac = addr + 2; |
| 2277 | int i; |
| 2278 | |
| 2279 | if (netif_running(dev)) |
| 2280 | return -EBUSY; |
| 2281 | |
| 2282 | /* Remove previous address table entry */ |
| 2283 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); |
| 2284 | |
| 2285 | /* Set new addr in hw */ |
| 2286 | mvneta_mac_addr_set(pp, mac, rxq_def); |
| 2287 | |
| 2288 | /* Set addr in the device */ |
| 2289 | for (i = 0; i < ETH_ALEN; i++) |
| 2290 | dev->dev_addr[i] = mac[i]; |
| 2291 | |
| 2292 | return 0; |
| 2293 | } |
| 2294 | |
| 2295 | static void mvneta_adjust_link(struct net_device *ndev) |
| 2296 | { |
| 2297 | struct mvneta_port *pp = netdev_priv(ndev); |
| 2298 | struct phy_device *phydev = pp->phy_dev; |
| 2299 | int status_change = 0; |
| 2300 | |
| 2301 | if (phydev->link) { |
| 2302 | if ((pp->speed != phydev->speed) || |
| 2303 | (pp->duplex != phydev->duplex)) { |
| 2304 | u32 val; |
| 2305 | |
| 2306 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
| 2307 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | |
| 2308 | MVNETA_GMAC_CONFIG_GMII_SPEED | |
Thomas Petazzoni | 4c54b9d | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 2309 | MVNETA_GMAC_CONFIG_FULL_DUPLEX | |
| 2310 | MVNETA_GMAC_AN_SPEED_EN | |
| 2311 | MVNETA_GMAC_AN_DUPLEX_EN); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2312 | |
| 2313 | if (phydev->duplex) |
| 2314 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; |
| 2315 | |
| 2316 | if (phydev->speed == SPEED_1000) |
| 2317 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; |
Thomas Petazzoni | 8a8d269 | 2014-07-08 10:49:43 +0200 | [diff] [blame] | 2318 | else if (phydev->speed == SPEED_100) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2319 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
| 2320 | |
| 2321 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); |
| 2322 | |
| 2323 | pp->duplex = phydev->duplex; |
| 2324 | pp->speed = phydev->speed; |
| 2325 | } |
| 2326 | } |
| 2327 | |
| 2328 | if (phydev->link != pp->link) { |
| 2329 | if (!phydev->link) { |
| 2330 | pp->duplex = -1; |
| 2331 | pp->speed = 0; |
| 2332 | } |
| 2333 | |
| 2334 | pp->link = phydev->link; |
| 2335 | status_change = 1; |
| 2336 | } |
| 2337 | |
| 2338 | if (status_change) { |
| 2339 | if (phydev->link) { |
| 2340 | u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
| 2341 | val |= (MVNETA_GMAC_FORCE_LINK_PASS | |
| 2342 | MVNETA_GMAC_FORCE_LINK_DOWN); |
| 2343 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); |
| 2344 | mvneta_port_up(pp); |
| 2345 | netdev_info(pp->dev, "link up\n"); |
| 2346 | } else { |
| 2347 | mvneta_port_down(pp); |
| 2348 | netdev_info(pp->dev, "link down\n"); |
| 2349 | } |
| 2350 | } |
| 2351 | } |
| 2352 | |
| 2353 | static int mvneta_mdio_probe(struct mvneta_port *pp) |
| 2354 | { |
| 2355 | struct phy_device *phy_dev; |
| 2356 | |
| 2357 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, |
| 2358 | pp->phy_interface); |
| 2359 | if (!phy_dev) { |
| 2360 | netdev_err(pp->dev, "could not find the PHY\n"); |
| 2361 | return -ENODEV; |
| 2362 | } |
| 2363 | |
| 2364 | phy_dev->supported &= PHY_GBIT_FEATURES; |
| 2365 | phy_dev->advertising = phy_dev->supported; |
| 2366 | |
| 2367 | pp->phy_dev = phy_dev; |
| 2368 | pp->link = 0; |
| 2369 | pp->duplex = 0; |
| 2370 | pp->speed = 0; |
| 2371 | |
| 2372 | return 0; |
| 2373 | } |
| 2374 | |
| 2375 | static void mvneta_mdio_remove(struct mvneta_port *pp) |
| 2376 | { |
| 2377 | phy_disconnect(pp->phy_dev); |
| 2378 | pp->phy_dev = NULL; |
| 2379 | } |
| 2380 | |
| 2381 | static int mvneta_open(struct net_device *dev) |
| 2382 | { |
| 2383 | struct mvneta_port *pp = netdev_priv(dev); |
| 2384 | int ret; |
| 2385 | |
| 2386 | mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); |
| 2387 | |
| 2388 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
| 2389 | |
| 2390 | ret = mvneta_setup_rxqs(pp); |
| 2391 | if (ret) |
| 2392 | return ret; |
| 2393 | |
| 2394 | ret = mvneta_setup_txqs(pp); |
| 2395 | if (ret) |
| 2396 | goto err_cleanup_rxqs; |
| 2397 | |
| 2398 | /* Connect to port interrupt line */ |
| 2399 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, |
| 2400 | MVNETA_DRIVER_NAME, pp); |
| 2401 | if (ret) { |
| 2402 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); |
| 2403 | goto err_cleanup_txqs; |
| 2404 | } |
| 2405 | |
| 2406 | /* In default link is down */ |
| 2407 | netif_carrier_off(pp->dev); |
| 2408 | |
| 2409 | ret = mvneta_mdio_probe(pp); |
| 2410 | if (ret < 0) { |
| 2411 | netdev_err(dev, "cannot probe MDIO bus\n"); |
| 2412 | goto err_free_irq; |
| 2413 | } |
| 2414 | |
| 2415 | mvneta_start_dev(pp); |
| 2416 | |
| 2417 | return 0; |
| 2418 | |
| 2419 | err_free_irq: |
| 2420 | free_irq(pp->dev->irq, pp); |
| 2421 | err_cleanup_txqs: |
| 2422 | mvneta_cleanup_txqs(pp); |
| 2423 | err_cleanup_rxqs: |
| 2424 | mvneta_cleanup_rxqs(pp); |
| 2425 | return ret; |
| 2426 | } |
| 2427 | |
| 2428 | /* Stop the port, free port interrupt line */ |
| 2429 | static int mvneta_stop(struct net_device *dev) |
| 2430 | { |
| 2431 | struct mvneta_port *pp = netdev_priv(dev); |
| 2432 | |
| 2433 | mvneta_stop_dev(pp); |
| 2434 | mvneta_mdio_remove(pp); |
| 2435 | free_irq(dev->irq, pp); |
| 2436 | mvneta_cleanup_rxqs(pp); |
| 2437 | mvneta_cleanup_txqs(pp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2438 | |
| 2439 | return 0; |
| 2440 | } |
| 2441 | |
| 2442 | /* Ethtool methods */ |
| 2443 | |
| 2444 | /* Get settings (phy address, speed) for ethtools */ |
| 2445 | int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 2446 | { |
| 2447 | struct mvneta_port *pp = netdev_priv(dev); |
| 2448 | |
| 2449 | if (!pp->phy_dev) |
| 2450 | return -ENODEV; |
| 2451 | |
| 2452 | return phy_ethtool_gset(pp->phy_dev, cmd); |
| 2453 | } |
| 2454 | |
| 2455 | /* Set settings (phy address, speed) for ethtools */ |
| 2456 | int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 2457 | { |
| 2458 | struct mvneta_port *pp = netdev_priv(dev); |
| 2459 | |
| 2460 | if (!pp->phy_dev) |
| 2461 | return -ENODEV; |
| 2462 | |
| 2463 | return phy_ethtool_sset(pp->phy_dev, cmd); |
| 2464 | } |
| 2465 | |
| 2466 | /* Set interrupt coalescing for ethtools */ |
| 2467 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, |
| 2468 | struct ethtool_coalesce *c) |
| 2469 | { |
| 2470 | struct mvneta_port *pp = netdev_priv(dev); |
| 2471 | int queue; |
| 2472 | |
| 2473 | for (queue = 0; queue < rxq_number; queue++) { |
| 2474 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; |
| 2475 | rxq->time_coal = c->rx_coalesce_usecs; |
| 2476 | rxq->pkts_coal = c->rx_max_coalesced_frames; |
| 2477 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); |
| 2478 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); |
| 2479 | } |
| 2480 | |
| 2481 | for (queue = 0; queue < txq_number; queue++) { |
| 2482 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; |
| 2483 | txq->done_pkts_coal = c->tx_max_coalesced_frames; |
| 2484 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
| 2485 | } |
| 2486 | |
| 2487 | return 0; |
| 2488 | } |
| 2489 | |
| 2490 | /* get coalescing for ethtools */ |
| 2491 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, |
| 2492 | struct ethtool_coalesce *c) |
| 2493 | { |
| 2494 | struct mvneta_port *pp = netdev_priv(dev); |
| 2495 | |
| 2496 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; |
| 2497 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; |
| 2498 | |
| 2499 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; |
| 2500 | return 0; |
| 2501 | } |
| 2502 | |
| 2503 | |
| 2504 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, |
| 2505 | struct ethtool_drvinfo *drvinfo) |
| 2506 | { |
| 2507 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, |
| 2508 | sizeof(drvinfo->driver)); |
| 2509 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, |
| 2510 | sizeof(drvinfo->version)); |
| 2511 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), |
| 2512 | sizeof(drvinfo->bus_info)); |
| 2513 | } |
| 2514 | |
| 2515 | |
| 2516 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, |
| 2517 | struct ethtool_ringparam *ring) |
| 2518 | { |
| 2519 | struct mvneta_port *pp = netdev_priv(netdev); |
| 2520 | |
| 2521 | ring->rx_max_pending = MVNETA_MAX_RXD; |
| 2522 | ring->tx_max_pending = MVNETA_MAX_TXD; |
| 2523 | ring->rx_pending = pp->rx_ring_size; |
| 2524 | ring->tx_pending = pp->tx_ring_size; |
| 2525 | } |
| 2526 | |
| 2527 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, |
| 2528 | struct ethtool_ringparam *ring) |
| 2529 | { |
| 2530 | struct mvneta_port *pp = netdev_priv(dev); |
| 2531 | |
| 2532 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) |
| 2533 | return -EINVAL; |
| 2534 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? |
| 2535 | ring->rx_pending : MVNETA_MAX_RXD; |
| 2536 | pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ? |
| 2537 | ring->tx_pending : MVNETA_MAX_TXD; |
| 2538 | |
| 2539 | if (netif_running(dev)) { |
| 2540 | mvneta_stop(dev); |
| 2541 | if (mvneta_open(dev)) { |
| 2542 | netdev_err(dev, |
| 2543 | "error on opening device after ring param change\n"); |
| 2544 | return -ENOMEM; |
| 2545 | } |
| 2546 | } |
| 2547 | |
| 2548 | return 0; |
| 2549 | } |
| 2550 | |
| 2551 | static const struct net_device_ops mvneta_netdev_ops = { |
| 2552 | .ndo_open = mvneta_open, |
| 2553 | .ndo_stop = mvneta_stop, |
| 2554 | .ndo_start_xmit = mvneta_tx, |
| 2555 | .ndo_set_rx_mode = mvneta_set_rx_mode, |
| 2556 | .ndo_set_mac_address = mvneta_set_mac_addr, |
| 2557 | .ndo_change_mtu = mvneta_change_mtu, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2558 | .ndo_get_stats64 = mvneta_get_stats64, |
| 2559 | }; |
| 2560 | |
| 2561 | const struct ethtool_ops mvneta_eth_tool_ops = { |
| 2562 | .get_link = ethtool_op_get_link, |
| 2563 | .get_settings = mvneta_ethtool_get_settings, |
| 2564 | .set_settings = mvneta_ethtool_set_settings, |
| 2565 | .set_coalesce = mvneta_ethtool_set_coalesce, |
| 2566 | .get_coalesce = mvneta_ethtool_get_coalesce, |
| 2567 | .get_drvinfo = mvneta_ethtool_get_drvinfo, |
| 2568 | .get_ringparam = mvneta_ethtool_get_ringparam, |
| 2569 | .set_ringparam = mvneta_ethtool_set_ringparam, |
| 2570 | }; |
| 2571 | |
| 2572 | /* Initialize hw */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 2573 | static int mvneta_init(struct mvneta_port *pp, int phy_addr) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2574 | { |
| 2575 | int queue; |
| 2576 | |
| 2577 | /* Disable port */ |
| 2578 | mvneta_port_disable(pp); |
| 2579 | |
| 2580 | /* Set port default values */ |
| 2581 | mvneta_defaults_set(pp); |
| 2582 | |
| 2583 | pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), |
| 2584 | GFP_KERNEL); |
| 2585 | if (!pp->txqs) |
| 2586 | return -ENOMEM; |
| 2587 | |
| 2588 | /* Initialize TX descriptor rings */ |
| 2589 | for (queue = 0; queue < txq_number; queue++) { |
| 2590 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; |
| 2591 | txq->id = queue; |
| 2592 | txq->size = pp->tx_ring_size; |
| 2593 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; |
| 2594 | } |
| 2595 | |
| 2596 | pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), |
| 2597 | GFP_KERNEL); |
| 2598 | if (!pp->rxqs) { |
| 2599 | kfree(pp->txqs); |
| 2600 | return -ENOMEM; |
| 2601 | } |
| 2602 | |
| 2603 | /* Create Rx descriptor rings */ |
| 2604 | for (queue = 0; queue < rxq_number; queue++) { |
| 2605 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; |
| 2606 | rxq->id = queue; |
| 2607 | rxq->size = pp->rx_ring_size; |
| 2608 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; |
| 2609 | rxq->time_coal = MVNETA_RX_COAL_USEC; |
| 2610 | } |
| 2611 | |
| 2612 | return 0; |
| 2613 | } |
| 2614 | |
Thomas Petazzoni | 70eeaf9 | 2012-11-19 14:40:02 +0100 | [diff] [blame] | 2615 | static void mvneta_deinit(struct mvneta_port *pp) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2616 | { |
| 2617 | kfree(pp->txqs); |
| 2618 | kfree(pp->rxqs); |
| 2619 | } |
| 2620 | |
| 2621 | /* platform glue : initialize decoding windows */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 2622 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
| 2623 | const struct mbus_dram_target_info *dram) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2624 | { |
| 2625 | u32 win_enable; |
| 2626 | u32 win_protect; |
| 2627 | int i; |
| 2628 | |
| 2629 | for (i = 0; i < 6; i++) { |
| 2630 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); |
| 2631 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); |
| 2632 | |
| 2633 | if (i < 4) |
| 2634 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); |
| 2635 | } |
| 2636 | |
| 2637 | win_enable = 0x3f; |
| 2638 | win_protect = 0; |
| 2639 | |
| 2640 | for (i = 0; i < dram->num_cs; i++) { |
| 2641 | const struct mbus_dram_window *cs = dram->cs + i; |
| 2642 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | |
| 2643 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); |
| 2644 | |
| 2645 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
| 2646 | (cs->size - 1) & 0xffff0000); |
| 2647 | |
| 2648 | win_enable &= ~(1 << i); |
| 2649 | win_protect |= 3 << (2 * i); |
| 2650 | } |
| 2651 | |
| 2652 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); |
| 2653 | } |
| 2654 | |
| 2655 | /* Power up the port */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 2656 | static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2657 | { |
| 2658 | u32 val; |
| 2659 | |
| 2660 | /* MAC Cause register should be cleared */ |
| 2661 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); |
| 2662 | |
| 2663 | if (phy_mode == PHY_INTERFACE_MODE_SGMII) |
| 2664 | mvneta_port_sgmii_config(pp); |
| 2665 | |
| 2666 | mvneta_gmac_rgmii_set(pp, 1); |
| 2667 | |
| 2668 | /* Cancel Port Reset */ |
| 2669 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
| 2670 | val &= ~MVNETA_GMAC2_PORT_RESET; |
| 2671 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); |
| 2672 | |
| 2673 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & |
| 2674 | MVNETA_GMAC2_PORT_RESET) != 0) |
| 2675 | continue; |
| 2676 | } |
| 2677 | |
| 2678 | /* Device initialization routine */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 2679 | static int mvneta_probe(struct platform_device *pdev) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2680 | { |
| 2681 | const struct mbus_dram_target_info *dram_target_info; |
| 2682 | struct device_node *dn = pdev->dev.of_node; |
| 2683 | struct device_node *phy_node; |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 2684 | u32 phy_addr; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2685 | struct mvneta_port *pp; |
| 2686 | struct net_device *dev; |
| 2687 | const char *mac_addr; |
| 2688 | int phy_mode; |
| 2689 | int err; |
| 2690 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2691 | /* Our multiqueue support is not complete, so for now, only |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2692 | * allow the usage of the first RX queue |
| 2693 | */ |
| 2694 | if (rxq_def != 0) { |
| 2695 | dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def); |
| 2696 | return -EINVAL; |
| 2697 | } |
| 2698 | |
Willy Tarreau | ee40a11 | 2013-04-11 23:00:37 +0200 | [diff] [blame] | 2699 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2700 | if (!dev) |
| 2701 | return -ENOMEM; |
| 2702 | |
| 2703 | dev->irq = irq_of_parse_and_map(dn, 0); |
| 2704 | if (dev->irq == 0) { |
| 2705 | err = -EINVAL; |
| 2706 | goto err_free_netdev; |
| 2707 | } |
| 2708 | |
| 2709 | phy_node = of_parse_phandle(dn, "phy", 0); |
| 2710 | if (!phy_node) { |
| 2711 | dev_err(&pdev->dev, "no associated PHY\n"); |
| 2712 | err = -ENODEV; |
| 2713 | goto err_free_irq; |
| 2714 | } |
| 2715 | |
| 2716 | phy_mode = of_get_phy_mode(dn); |
| 2717 | if (phy_mode < 0) { |
| 2718 | dev_err(&pdev->dev, "incorrect phy-mode\n"); |
| 2719 | err = -EINVAL; |
| 2720 | goto err_free_irq; |
| 2721 | } |
| 2722 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2723 | mac_addr = of_get_mac_address(dn); |
| 2724 | |
| 2725 | if (!mac_addr || !is_valid_ether_addr(mac_addr)) |
| 2726 | eth_hw_addr_random(dev); |
| 2727 | else |
| 2728 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
| 2729 | |
| 2730 | dev->tx_queue_len = MVNETA_MAX_TXD; |
| 2731 | dev->watchdog_timeo = 5 * HZ; |
| 2732 | dev->netdev_ops = &mvneta_netdev_ops; |
| 2733 | |
| 2734 | SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops); |
| 2735 | |
| 2736 | pp = netdev_priv(dev); |
| 2737 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2738 | pp->weight = MVNETA_RX_POLL_WEIGHT; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2739 | pp->phy_node = phy_node; |
| 2740 | pp->phy_interface = phy_mode; |
| 2741 | |
| 2742 | pp->base = of_iomap(dn, 0); |
| 2743 | if (pp->base == NULL) { |
| 2744 | err = -ENOMEM; |
| 2745 | goto err_free_irq; |
| 2746 | } |
| 2747 | |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 2748 | pp->clk = devm_clk_get(&pdev->dev, NULL); |
| 2749 | if (IS_ERR(pp->clk)) { |
| 2750 | err = PTR_ERR(pp->clk); |
| 2751 | goto err_unmap; |
| 2752 | } |
| 2753 | |
| 2754 | clk_prepare_enable(pp->clk); |
| 2755 | |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 2756 | /* Alloc per-cpu stats */ |
| 2757 | pp->stats = alloc_percpu(struct mvneta_pcpu_stats); |
| 2758 | if (!pp->stats) { |
| 2759 | err = -ENOMEM; |
| 2760 | goto err_clk; |
| 2761 | } |
| 2762 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2763 | pp->tx_ring_size = MVNETA_MAX_TXD; |
| 2764 | pp->rx_ring_size = MVNETA_MAX_RXD; |
| 2765 | |
| 2766 | pp->dev = dev; |
| 2767 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 2768 | |
| 2769 | err = mvneta_init(pp, phy_addr); |
| 2770 | if (err < 0) { |
| 2771 | dev_err(&pdev->dev, "can't init eth hal\n"); |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 2772 | goto err_free_stats; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2773 | } |
| 2774 | mvneta_port_power_up(pp, phy_mode); |
| 2775 | |
| 2776 | dram_target_info = mv_mbus_dram_info(); |
| 2777 | if (dram_target_info) |
| 2778 | mvneta_conf_mbus_windows(pp, dram_target_info); |
| 2779 | |
| 2780 | netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight); |
| 2781 | |
willy tarreau | b50b72d | 2013-04-06 08:47:01 +0000 | [diff] [blame] | 2782 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
| 2783 | dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM; |
| 2784 | dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM; |
| 2785 | dev->priv_flags |= IFF_UNICAST_FLT; |
| 2786 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2787 | err = register_netdev(dev); |
| 2788 | if (err < 0) { |
| 2789 | dev_err(&pdev->dev, "failed to register\n"); |
| 2790 | goto err_deinit; |
| 2791 | } |
| 2792 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2793 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
| 2794 | |
| 2795 | platform_set_drvdata(pdev, pp->dev); |
| 2796 | |
| 2797 | return 0; |
| 2798 | |
| 2799 | err_deinit: |
| 2800 | mvneta_deinit(pp); |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 2801 | err_free_stats: |
| 2802 | free_percpu(pp->stats); |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 2803 | err_clk: |
| 2804 | clk_disable_unprepare(pp->clk); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2805 | err_unmap: |
| 2806 | iounmap(pp->base); |
| 2807 | err_free_irq: |
| 2808 | irq_dispose_mapping(dev->irq); |
| 2809 | err_free_netdev: |
| 2810 | free_netdev(dev); |
| 2811 | return err; |
| 2812 | } |
| 2813 | |
| 2814 | /* Device removal routine */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 2815 | static int mvneta_remove(struct platform_device *pdev) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2816 | { |
| 2817 | struct net_device *dev = platform_get_drvdata(pdev); |
| 2818 | struct mvneta_port *pp = netdev_priv(dev); |
| 2819 | |
| 2820 | unregister_netdev(dev); |
| 2821 | mvneta_deinit(pp); |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 2822 | clk_disable_unprepare(pp->clk); |
willy tarreau | 936e9bc | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 2823 | free_percpu(pp->stats); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2824 | iounmap(pp->base); |
| 2825 | irq_dispose_mapping(dev->irq); |
| 2826 | free_netdev(dev); |
| 2827 | |
| 2828 | platform_set_drvdata(pdev, NULL); |
| 2829 | |
| 2830 | return 0; |
| 2831 | } |
| 2832 | |
| 2833 | static const struct of_device_id mvneta_match[] = { |
| 2834 | { .compatible = "marvell,armada-370-neta" }, |
| 2835 | { } |
| 2836 | }; |
| 2837 | MODULE_DEVICE_TABLE(of, mvneta_match); |
| 2838 | |
| 2839 | static struct platform_driver mvneta_driver = { |
| 2840 | .probe = mvneta_probe, |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 2841 | .remove = mvneta_remove, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2842 | .driver = { |
| 2843 | .name = MVNETA_DRIVER_NAME, |
| 2844 | .of_match_table = mvneta_match, |
| 2845 | }, |
| 2846 | }; |
| 2847 | |
| 2848 | module_platform_driver(mvneta_driver); |
| 2849 | |
| 2850 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); |
| 2851 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); |
| 2852 | MODULE_LICENSE("GPL"); |
| 2853 | |
| 2854 | module_param(rxq_number, int, S_IRUGO); |
| 2855 | module_param(txq_number, int, S_IRUGO); |
| 2856 | |
| 2857 | module_param(rxq_def, int, S_IRUGO); |