Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/common/gic.c |
| 3 | * |
| 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Interrupt architecture for the GIC: |
| 11 | * |
| 12 | * o There is one Interrupt Distributor, which receives interrupts |
| 13 | * from system devices and sends them to the Interrupt Controllers. |
| 14 | * |
| 15 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 16 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 17 | * associated CPU. The base address of the CPU interface is usually |
| 18 | * aliased so that the same address points to different chips depending |
| 19 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 20 | * |
| 21 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 22 | * As such, the enable set/clear, pending set/clear and active bit |
| 23 | * registers are banked per-cpu for these sources. |
| 24 | */ |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/smp.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 29 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 30 | #include <linux/io.h> |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame^] | 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/percpu.h> |
| 33 | #include <linux/slab.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 34 | |
| 35 | #include <asm/irq.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 36 | #include <asm/mach/irq.h> |
| 37 | #include <asm/hardware/gic.h> |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame^] | 38 | #include <asm/localtimer.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 39 | |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 40 | static DEFINE_SPINLOCK(irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 41 | |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 42 | /* Address of GIC 0 CPU interface */ |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 43 | void __iomem *gic_cpu_base_addr __read_mostly; |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 44 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 45 | /* |
| 46 | * Supported arch specific GIC irq extension. |
| 47 | * Default make them NULL. |
| 48 | */ |
| 49 | struct irq_chip gic_arch_extn = { |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 50 | .irq_eoi = NULL, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 51 | .irq_mask = NULL, |
| 52 | .irq_unmask = NULL, |
| 53 | .irq_retrigger = NULL, |
| 54 | .irq_set_type = NULL, |
| 55 | .irq_set_wake = NULL, |
| 56 | }; |
| 57 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 58 | #ifndef MAX_GIC_NR |
| 59 | #define MAX_GIC_NR 1 |
| 60 | #endif |
| 61 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 62 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 63 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 64 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 65 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 66 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 67 | return gic_data->dist_base; |
| 68 | } |
| 69 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 70 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 71 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 72 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 73 | return gic_data->cpu_base; |
| 74 | } |
| 75 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 76 | static inline unsigned int gic_irq(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 77 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 78 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
| 79 | return d->irq - gic_data->irq_offset; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 80 | } |
| 81 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 82 | /* |
| 83 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 84 | */ |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 85 | static void gic_mask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 86 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 87 | u32 mask = 1 << (d->irq % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 88 | |
| 89 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 90 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 91 | if (gic_arch_extn.irq_mask) |
| 92 | gic_arch_extn.irq_mask(d); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 93 | spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 94 | } |
| 95 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 96 | static void gic_unmask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 97 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 98 | u32 mask = 1 << (d->irq % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 99 | |
| 100 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 101 | if (gic_arch_extn.irq_unmask) |
| 102 | gic_arch_extn.irq_unmask(d); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 103 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 104 | spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 105 | } |
| 106 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 107 | static void gic_eoi_irq(struct irq_data *d) |
| 108 | { |
| 109 | if (gic_arch_extn.irq_eoi) { |
| 110 | spin_lock(&irq_controller_lock); |
| 111 | gic_arch_extn.irq_eoi(d); |
| 112 | spin_unlock(&irq_controller_lock); |
| 113 | } |
| 114 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 115 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 118 | static int gic_set_type(struct irq_data *d, unsigned int type) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 119 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 120 | void __iomem *base = gic_dist_base(d); |
| 121 | unsigned int gicirq = gic_irq(d); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 122 | u32 enablemask = 1 << (gicirq % 32); |
| 123 | u32 enableoff = (gicirq / 32) * 4; |
| 124 | u32 confmask = 0x2 << ((gicirq % 16) * 2); |
| 125 | u32 confoff = (gicirq / 16) * 4; |
| 126 | bool enabled = false; |
| 127 | u32 val; |
| 128 | |
| 129 | /* Interrupt configuration for SGIs can't be changed */ |
| 130 | if (gicirq < 16) |
| 131 | return -EINVAL; |
| 132 | |
| 133 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) |
| 134 | return -EINVAL; |
| 135 | |
| 136 | spin_lock(&irq_controller_lock); |
| 137 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 138 | if (gic_arch_extn.irq_set_type) |
| 139 | gic_arch_extn.irq_set_type(d, type); |
| 140 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 141 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 142 | if (type == IRQ_TYPE_LEVEL_HIGH) |
| 143 | val &= ~confmask; |
| 144 | else if (type == IRQ_TYPE_EDGE_RISING) |
| 145 | val |= confmask; |
| 146 | |
| 147 | /* |
| 148 | * As recommended by the spec, disable the interrupt before changing |
| 149 | * the configuration |
| 150 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 151 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
| 152 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 153 | enabled = true; |
| 154 | } |
| 155 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 156 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 157 | |
| 158 | if (enabled) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 159 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 160 | |
| 161 | spin_unlock(&irq_controller_lock); |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 166 | static int gic_retrigger(struct irq_data *d) |
| 167 | { |
| 168 | if (gic_arch_extn.irq_retrigger) |
| 169 | return gic_arch_extn.irq_retrigger(d); |
| 170 | |
| 171 | return -ENXIO; |
| 172 | } |
| 173 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 174 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 175 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 176 | bool force) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 177 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 178 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
| 179 | unsigned int shift = (d->irq % 4) * 8; |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 180 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 181 | u32 val, mask, bit; |
| 182 | |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 183 | if (cpu >= 8 || cpu >= nr_cpu_ids) |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 184 | return -EINVAL; |
| 185 | |
| 186 | mask = 0xff << shift; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 187 | bit = 1 << (cpu_logical_map(cpu) + shift); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 188 | |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 189 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 190 | val = readl_relaxed(reg) & ~mask; |
| 191 | writel_relaxed(val | bit, reg); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 192 | spin_unlock(&irq_controller_lock); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 193 | |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 194 | return IRQ_SET_MASK_OK; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 195 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 196 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 197 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 198 | #ifdef CONFIG_PM |
| 199 | static int gic_set_wake(struct irq_data *d, unsigned int on) |
| 200 | { |
| 201 | int ret = -ENXIO; |
| 202 | |
| 203 | if (gic_arch_extn.irq_set_wake) |
| 204 | ret = gic_arch_extn.irq_set_wake(d, on); |
| 205 | |
| 206 | return ret; |
| 207 | } |
| 208 | |
| 209 | #else |
| 210 | #define gic_set_wake NULL |
| 211 | #endif |
| 212 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 213 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 214 | { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 215 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
| 216 | struct irq_chip *chip = irq_get_chip(irq); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 217 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 218 | unsigned long status; |
| 219 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 220 | chained_irq_enter(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 221 | |
| 222 | spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 223 | status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 224 | spin_unlock(&irq_controller_lock); |
| 225 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 226 | gic_irq = (status & 0x3ff); |
| 227 | if (gic_irq == 1023) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 228 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 229 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 230 | cascade_irq = gic_irq + chip_data->irq_offset; |
| 231 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) |
| 232 | do_bad_IRQ(cascade_irq, desc); |
| 233 | else |
| 234 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 235 | |
| 236 | out: |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 237 | chained_irq_exit(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 238 | } |
| 239 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 240 | static struct irq_chip gic_chip = { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 241 | .name = "GIC", |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 242 | .irq_mask = gic_mask_irq, |
| 243 | .irq_unmask = gic_unmask_irq, |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 244 | .irq_eoi = gic_eoi_irq, |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 245 | .irq_set_type = gic_set_type, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 246 | .irq_retrigger = gic_retrigger, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 247 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 248 | .irq_set_affinity = gic_set_affinity, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 249 | #endif |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 250 | .irq_set_wake = gic_set_wake, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 251 | }; |
| 252 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 253 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 254 | { |
| 255 | if (gic_nr >= MAX_GIC_NR) |
| 256 | BUG(); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 257 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 258 | BUG(); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 259 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 260 | } |
| 261 | |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame^] | 262 | #ifdef CONFIG_LOCAL_TIMERS |
| 263 | #define gic_ppi_handler percpu_timer_handler |
| 264 | #else |
| 265 | static irqreturn_t gic_ppi_handler(int irq, void *dev_id) |
| 266 | { |
| 267 | return IRQ_NONE; |
| 268 | } |
| 269 | #endif |
| 270 | |
| 271 | #define PPI_IRQACT(nr) \ |
| 272 | { \ |
| 273 | .handler = gic_ppi_handler, \ |
| 274 | .flags = IRQF_PERCPU | IRQF_TIMER, \ |
| 275 | .irq = nr, \ |
| 276 | .name = "PPI-" # nr, \ |
| 277 | } |
| 278 | |
| 279 | static struct irqaction ppi_irqaction_template[16] __initdata = { |
| 280 | PPI_IRQACT(0), PPI_IRQACT(1), PPI_IRQACT(2), PPI_IRQACT(3), |
| 281 | PPI_IRQACT(4), PPI_IRQACT(5), PPI_IRQACT(6), PPI_IRQACT(7), |
| 282 | PPI_IRQACT(8), PPI_IRQACT(9), PPI_IRQACT(10), PPI_IRQACT(11), |
| 283 | PPI_IRQACT(12), PPI_IRQACT(13), PPI_IRQACT(14), PPI_IRQACT(15), |
| 284 | }; |
| 285 | |
| 286 | static struct irqaction *ppi_irqaction; |
| 287 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 288 | static void __init gic_dist_init(struct gic_chip_data *gic, |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 289 | unsigned int irq_start) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 290 | { |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 291 | unsigned int gic_irqs, irq_limit, i; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 292 | u32 cpumask; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 293 | void __iomem *base = gic->dist_base; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 294 | u32 cpu = 0; |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame^] | 295 | u32 nrppis = 0, ppi_base = 0; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 296 | |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 297 | #ifdef CONFIG_SMP |
| 298 | cpu = cpu_logical_map(smp_processor_id()); |
| 299 | #endif |
| 300 | |
| 301 | cpumask = 1 << cpu; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 302 | cpumask |= cpumask << 8; |
| 303 | cpumask |= cpumask << 16; |
| 304 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 305 | writel_relaxed(0, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 306 | |
| 307 | /* |
| 308 | * Find out how many interrupts are supported. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 309 | * The GIC only supports up to 1020 interrupt sources. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 310 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 311 | gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 312 | gic_irqs = (gic_irqs + 1) * 32; |
| 313 | if (gic_irqs > 1020) |
| 314 | gic_irqs = 1020; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 315 | |
| 316 | /* |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame^] | 317 | * Nobody would be insane enough to use PPIs on a secondary |
| 318 | * GIC, right? |
| 319 | */ |
| 320 | if (gic == &gic_data[0]) { |
| 321 | nrppis = (32 - irq_start) & 31; |
| 322 | |
| 323 | /* The GIC only supports up to 16 PPIs. */ |
| 324 | if (nrppis > 16) |
| 325 | BUG(); |
| 326 | |
| 327 | ppi_base = gic->irq_offset + 32 - nrppis; |
| 328 | |
| 329 | ppi_irqaction = kmemdup(&ppi_irqaction_template[16 - nrppis], |
| 330 | sizeof(*ppi_irqaction) * nrppis, |
| 331 | GFP_KERNEL); |
| 332 | |
| 333 | if (nrppis && !ppi_irqaction) { |
| 334 | pr_err("GIC: Can't allocate PPI memory"); |
| 335 | nrppis = 0; |
| 336 | ppi_base = 0; |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | pr_info("Configuring GIC with %d sources (%d PPIs)\n", |
| 341 | gic_irqs, (gic == &gic_data[0]) ? nrppis : 0); |
| 342 | |
| 343 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 344 | * Set all global interrupts to be level triggered, active low. |
| 345 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 346 | for (i = 32; i < gic_irqs; i += 16) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 347 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 348 | |
| 349 | /* |
| 350 | * Set all global interrupts to this CPU only. |
| 351 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 352 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 353 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 354 | |
| 355 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 356 | * Set priority on all global interrupts. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 357 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 358 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 359 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 360 | |
| 361 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 362 | * Disable all interrupts. Leave the PPI and SGIs alone |
| 363 | * as these enables are banked registers. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 364 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 365 | for (i = 32; i < gic_irqs; i += 32) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 366 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 367 | |
| 368 | /* |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 369 | * Limit number of interrupts registered to the platform maximum |
| 370 | */ |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 371 | irq_limit = gic->irq_offset + gic_irqs; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 372 | if (WARN_ON(irq_limit > NR_IRQS)) |
| 373 | irq_limit = NR_IRQS; |
| 374 | |
| 375 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 376 | * Setup the Linux IRQ subsystem. |
| 377 | */ |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame^] | 378 | for (i = 0; i < nrppis; i++) { |
| 379 | int ppi = i + ppi_base; |
| 380 | int err; |
| 381 | |
| 382 | irq_set_percpu_devid(ppi); |
| 383 | irq_set_chip_and_handler(ppi, &gic_chip, |
| 384 | handle_percpu_devid_irq); |
| 385 | irq_set_chip_data(ppi, gic); |
| 386 | set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN); |
| 387 | |
| 388 | err = setup_percpu_irq(ppi, &ppi_irqaction[i]); |
| 389 | if (err) |
| 390 | pr_err("GIC: can't setup PPI%d (%d)\n", ppi, err); |
| 391 | } |
| 392 | |
| 393 | for (i = irq_start + nrppis; i < irq_limit; i++) { |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 394 | irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); |
Thomas Gleixner | 9323f261 | 2011-03-24 13:29:39 +0100 | [diff] [blame] | 395 | irq_set_chip_data(i, gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 396 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 397 | } |
| 398 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 399 | writel_relaxed(1, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 400 | } |
| 401 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 402 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 403 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 404 | void __iomem *dist_base = gic->dist_base; |
| 405 | void __iomem *base = gic->cpu_base; |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 406 | int i; |
| 407 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 408 | /* |
| 409 | * Deal with the banked PPI and SGI interrupts - disable all |
| 410 | * PPI interrupts, ensure all SGI interrupts are enabled. |
| 411 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 412 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
| 413 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 414 | |
| 415 | /* |
| 416 | * Set priority on PPI and SGI interrupts |
| 417 | */ |
| 418 | for (i = 0; i < 32; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 419 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 420 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 421 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
| 422 | writel_relaxed(1, base + GIC_CPU_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 423 | } |
| 424 | |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 425 | void __init gic_init(unsigned int gic_nr, unsigned int irq_start, |
| 426 | void __iomem *dist_base, void __iomem *cpu_base) |
| 427 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 428 | struct gic_chip_data *gic; |
| 429 | |
| 430 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 431 | |
| 432 | gic = &gic_data[gic_nr]; |
| 433 | gic->dist_base = dist_base; |
| 434 | gic->cpu_base = cpu_base; |
| 435 | gic->irq_offset = (irq_start - 1) & ~31; |
| 436 | |
Russell King | ff2e27a | 2010-12-04 16:13:29 +0000 | [diff] [blame] | 437 | if (gic_nr == 0) |
| 438 | gic_cpu_base_addr = cpu_base; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 439 | |
| 440 | gic_dist_init(gic, irq_start); |
| 441 | gic_cpu_init(gic); |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 442 | } |
| 443 | |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 444 | void __cpuinit gic_secondary_init(unsigned int gic_nr) |
| 445 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 446 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 447 | |
| 448 | gic_cpu_init(&gic_data[gic_nr]); |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 449 | } |
| 450 | |
Russell King | ac61d14 | 2010-12-06 10:38:14 +0000 | [diff] [blame] | 451 | void __cpuinit gic_enable_ppi(unsigned int irq) |
| 452 | { |
| 453 | unsigned long flags; |
| 454 | |
| 455 | local_irq_save(flags); |
Thomas Gleixner | fdea77b | 2011-03-24 12:48:54 +0100 | [diff] [blame] | 456 | irq_set_status_flags(irq, IRQ_NOPROBE); |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 457 | gic_unmask_irq(irq_get_irq_data(irq)); |
Russell King | ac61d14 | 2010-12-06 10:38:14 +0000 | [diff] [blame] | 458 | local_irq_restore(flags); |
| 459 | } |
| 460 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 461 | #ifdef CONFIG_SMP |
Russell King | 8266810 | 2009-05-17 16:20:18 +0100 | [diff] [blame] | 462 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 463 | { |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 464 | int cpu; |
| 465 | unsigned long map = 0; |
| 466 | |
| 467 | /* Convert our logical CPU mask into a physical one. */ |
| 468 | for_each_cpu(cpu, mask) |
| 469 | map |= 1 << cpu_logical_map(cpu); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 470 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 471 | /* |
| 472 | * Ensure that stores to Normal memory are visible to the |
| 473 | * other CPUs before issuing the IPI. |
| 474 | */ |
| 475 | dsb(); |
| 476 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 477 | /* this always happens on GIC0 */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 478 | writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 479 | } |
| 480 | #endif |