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review.linaro.org / kernel / linux-linaro-stable.git / 1e2c53f19cefa0689798e4a37ecb73f2c8a7d7c7 / . / arch / powerpc / include / uapi / asm / elf.h
blob: 59dad113897b0b65f6c616df175a596d901dab77 [file] [log] [blame]
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]1/*
2 * ELF register definitions..
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef _UAPI_ASM_POWERPC_ELF_H
10#define _UAPI_ASM_POWERPC_ELF_H
11
12
13#include <linux/types.h>
14
15#include <asm/ptrace.h>
16#include <asm/cputable.h>
17#include <asm/auxvec.h>
18
19/* PowerPC relocations defined by the ABIs */
20#define R_PPC_NONE 0
21#define R_PPC_ADDR32 1 /* 32bit absolute address */
22#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
23#define R_PPC_ADDR16 3 /* 16bit absolute address */
24#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
25#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
26#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
27#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
28#define R_PPC_ADDR14_BRTAKEN 8
29#define R_PPC_ADDR14_BRNTAKEN 9
30#define R_PPC_REL24 10 /* PC relative 26 bit */
31#define R_PPC_REL14 11 /* PC relative 16 bit */
32#define R_PPC_REL14_BRTAKEN 12
33#define R_PPC_REL14_BRNTAKEN 13
34#define R_PPC_GOT16 14
35#define R_PPC_GOT16_LO 15
36#define R_PPC_GOT16_HI 16
37#define R_PPC_GOT16_HA 17
38#define R_PPC_PLTREL24 18
39#define R_PPC_COPY 19
40#define R_PPC_GLOB_DAT 20
41#define R_PPC_JMP_SLOT 21
42#define R_PPC_RELATIVE 22
43#define R_PPC_LOCAL24PC 23
44#define R_PPC_UADDR32 24
45#define R_PPC_UADDR16 25
46#define R_PPC_REL32 26
47#define R_PPC_PLT32 27
48#define R_PPC_PLTREL32 28
49#define R_PPC_PLT16_LO 29
50#define R_PPC_PLT16_HI 30
51#define R_PPC_PLT16_HA 31
52#define R_PPC_SDAREL16 32
53#define R_PPC_SECTOFF 33
54#define R_PPC_SECTOFF_LO 34
55#define R_PPC_SECTOFF_HI 35
56#define R_PPC_SECTOFF_HA 36
57
58/* PowerPC relocations defined for the TLS access ABI. */
59#define R_PPC_TLS 67 /* none (sym+add)@tls */
60#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
61#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
62#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
63#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
64#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
65#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
66#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
67#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
68#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
69#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
70#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
71#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
72#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
73#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
74#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
75#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
76#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
77#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
78#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
79#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
80#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
81#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
82#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
83#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
84#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
85#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
86#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
87
88/* keep this the last entry. */
89#define R_PPC_NUM 95
90
91
92#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
93#define ELF_NFPREG 33 /* includes fpscr */
94
95typedef unsigned long elf_greg_t64;
96typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
97
98typedef unsigned int elf_greg_t32;
99typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
100typedef elf_gregset_t32 compat_elf_gregset_t;
101
102/*
103 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
104 */
105#ifdef __powerpc64__
106# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
107# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
108# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
109# define ELF_GREG_TYPE elf_greg_t64
Anton Blanchard01b0e072013-08-07 02:01:22 +1000[diff] [blame]110# define ELF_ARCH EM_PPC64
111# define ELF_CLASS ELFCLASS64
Anton Blanchard01b0e072013-08-07 02:01:22 +1000[diff] [blame]112typedef elf_greg_t64 elf_greg_t;
113typedef elf_gregset_t64 elf_gregset_t;
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]114#else
115# define ELF_NEVRREG 34 /* includes acc (as 2) */
116# define ELF_NVRREG 33 /* includes vscr */
117# define ELF_GREG_TYPE elf_greg_t32
118# define ELF_ARCH EM_PPC
119# define ELF_CLASS ELFCLASS32
Anton Blanchard01b0e072013-08-07 02:01:22 +1000[diff] [blame]120typedef elf_greg_t32 elf_greg_t;
121typedef elf_gregset_t32 elf_gregset_t;
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]122#endif /* __powerpc64__ */
123
Anton Blanchard8bd0b112013-08-07 02:01:50 +1000[diff] [blame]124#ifdef __BIG_ENDIAN__
125#define ELF_DATA ELFDATA2MSB
126#else
127#define ELF_DATA ELFDATA2LSB
128#endif
129
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]130/* Floating point registers */
131typedef double elf_fpreg_t;
132typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
133
134/* Altivec registers */
135/*
136 * The entries with indexes 0-31 contain the corresponding vector registers.
137 * The entry with index 32 contains the vscr as the last word (offset 12)
138 * within the quadword. This allows the vscr to be stored as either a
139 * quadword (since it must be copied via a vector register to/from storage)
140 * or as a word.
141 *
142 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
143 * word (offset 0) within the quadword.
144 *
145 * This definition of the VMX state is compatible with the current PPC32
146 * ptrace interface. This allows signal handling and ptrace to use the same
147 * structures. This also simplifies the implementation of a bi-arch
148 * (combined (32- and 64-bit) gdb.
149 *
150 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
151 * vrsave along with vscr and so only uses 33 vectors for the register set
152 */
153typedef __vector128 elf_vrreg_t;
154typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
155#ifdef __powerpc64__
156typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
157typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
158#endif
159
160
161/*
162 * The requirements here are:
163 * - keep the final alignment of sp (sp & 0xf)
164 * - make sure the 32-bit value at the first 16 byte aligned position of
165 * AUXV is greater than 16 for glibc compatibility.
166 * AT_IGNOREPPC is used for that.
167 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
168 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
169 * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
170 */
171#define ARCH_DLINFO \
172do { \
173 /* Handle glibc compatibility. */ \
174 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
175 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
176 /* Cache size items */ \
177 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
178 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
179 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
180 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base); \
181} while (0)
182
183/* PowerPC64 relocations defined by the ABIs */
184#define R_PPC64_NONE R_PPC_NONE
185#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
186#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
187#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
188#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
189#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
190#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
191#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
192#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
193#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
194#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
195#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
196#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
197#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
198#define R_PPC64_GOT16 R_PPC_GOT16
199#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
200#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
201#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
202
203#define R_PPC64_COPY R_PPC_COPY
204#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
205#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
206#define R_PPC64_RELATIVE R_PPC_RELATIVE
207
208#define R_PPC64_UADDR32 R_PPC_UADDR32
209#define R_PPC64_UADDR16 R_PPC_UADDR16
210#define R_PPC64_REL32 R_PPC_REL32
211#define R_PPC64_PLT32 R_PPC_PLT32
212#define R_PPC64_PLTREL32 R_PPC_PLTREL32
213#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
214#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
215#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
216
217#define R_PPC64_SECTOFF R_PPC_SECTOFF
218#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
219#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
220#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
221#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
222#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
223#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
224#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
225#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
226#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
227#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
228#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
229#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
230#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
231#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
232#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
233#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
234#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
235#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
236#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
237#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
238#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
239#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
240
241#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
242#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
243#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
244#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
245#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
246#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
247#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
248#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
249#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
250#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
251#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
252
253/* PowerPC64 relocations defined for the TLS access ABI. */
254#define R_PPC64_TLS 67 /* none (sym+add)@tls */
255#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
256#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
257#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
258#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
259#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
260#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
261#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
262#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
263#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
264#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
265#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
266#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
267#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
268#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
269#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
270#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
271#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
272#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
273#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
274#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
275#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
276#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
277#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
278#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
279#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
280#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
281#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
282#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
283#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
284#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
285#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
286#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
287#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
288#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
289#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
290#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
291#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
292#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
293#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
Rusty Russelld247da02014-03-18 17:36:28 +1030[diff] [blame]294#define R_PPC64_TLSGD 107
295#define R_PPC64_TLSLD 108
296#define R_PPC64_TOCSAVE 109
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]297
Rusty Russell09065842014-03-18 19:59:27 +1030[diff] [blame]298#define R_PPC64_REL16 249
299#define R_PPC64_REL16_LO 250
300#define R_PPC64_REL16_HI 251
301#define R_PPC64_REL16_HA 252
302
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]303/* Keep this the last entry. */
Rusty Russell09065842014-03-18 19:59:27 +1030[diff] [blame]304#define R_PPC64_NUM 253
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]305
306/* There's actually a third entry here, but it's unused */
307struct ppc64_opd_entry
308{
309 unsigned long funcaddr;
310 unsigned long r2;
311};
312
313
314#endif /* _UAPI_ASM_POWERPC_ELF_H */