blob: 9d6f3bbf0e53db364d63edd45ab2c7ef46efa5c1 [file] [log] [blame]
Dan Williamsbf40a682009-09-08 17:42:55 -07001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
24 *
25 * BSD LICENSE
26 *
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
31 *
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
37 * distribution.
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
53 */
54
55/*
56 * Support routines for v3+ hardware
57 */
58
59#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090060#include <linux/gfp.h>
Dan Williamsbf40a682009-09-08 17:42:55 -070061#include <linux/dmaengine.h>
62#include <linux/dma-mapping.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040063#include <linux/prefetch.h>
Vinod Koul949ff5b2012-03-13 11:58:12 +053064#include "../dmaengine.h"
Dan Williamsbf40a682009-09-08 17:42:55 -070065#include "registers.h"
66#include "hw.h"
67#include "dma.h"
68#include "dma_v2.h"
69
Dan Williamsb094ad32009-09-08 17:42:57 -070070/* ioat hardware assumes at least two sources for raid operations */
71#define src_cnt_to_sw(x) ((x) + 2)
72#define src_cnt_to_hw(x) ((x) - 2)
73
74/* provide a lookup table for setting the source address in the base or
Dan Williamsd69d235b2009-09-08 17:42:59 -070075 * extended descriptor of an xor or pq descriptor
Dan Williamsb094ad32009-09-08 17:42:57 -070076 */
Dan Williamsd0b0c8c2011-07-22 14:20:46 -070077static const u8 xor_idx_to_desc = 0xe0;
Andi Kleen9b487ce2011-06-07 15:26:33 -070078static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 };
79static const u8 pq_idx_to_desc = 0xf8;
80static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 };
Dan Williamsb094ad32009-09-08 17:42:57 -070081
82static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
83{
84 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
85
86 return raw->field[xor_idx_to_field[idx]];
87}
88
89static void xor_set_src(struct ioat_raw_descriptor *descs[2],
90 dma_addr_t addr, u32 offset, int idx)
91{
92 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
93
94 raw->field[xor_idx_to_field[idx]] = addr + offset;
95}
96
Dan Williamsd69d235b2009-09-08 17:42:59 -070097static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
98{
99 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
100
101 return raw->field[pq_idx_to_field[idx]];
102}
103
104static void pq_set_src(struct ioat_raw_descriptor *descs[2],
105 dma_addr_t addr, u32 offset, u8 coef, int idx)
106{
107 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
108 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
109
110 raw->field[pq_idx_to_field[idx]] = addr + offset;
111 pq->coef[idx] = coef;
112}
113
Dan Williamsbf40a682009-09-08 17:42:55 -0700114static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
Dan Williamsb094ad32009-09-08 17:42:57 -0700115 struct ioat_ring_ent *desc, int idx)
Dan Williamsbf40a682009-09-08 17:42:55 -0700116{
117 struct ioat_chan_common *chan = &ioat->base;
118 struct pci_dev *pdev = chan->device->pdev;
119 size_t len = desc->len;
120 size_t offset = len - desc->hw->size;
121 struct dma_async_tx_descriptor *tx = &desc->txd;
122 enum dma_ctrl_flags flags = tx->flags;
123
124 switch (desc->hw->ctl_f.op) {
125 case IOAT_OP_COPY:
Dan Williams58c86492009-09-08 17:43:00 -0700126 if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */
127 ioat_dma_unmap(chan, flags, len, desc->hw);
Dan Williamsbf40a682009-09-08 17:42:55 -0700128 break;
129 case IOAT_OP_FILL: {
130 struct ioat_fill_descriptor *hw = desc->fill;
131
132 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
133 ioat_unmap(pdev, hw->dst_addr - offset, len,
134 PCI_DMA_FROMDEVICE, flags, 1);
135 break;
136 }
Dan Williamsb094ad32009-09-08 17:42:57 -0700137 case IOAT_OP_XOR_VAL:
138 case IOAT_OP_XOR: {
139 struct ioat_xor_descriptor *xor = desc->xor;
140 struct ioat_ring_ent *ext;
141 struct ioat_xor_ext_descriptor *xor_ex = NULL;
142 int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt);
143 struct ioat_raw_descriptor *descs[2];
144 int i;
145
146 if (src_cnt > 5) {
147 ext = ioat2_get_ring_ent(ioat, idx + 1);
148 xor_ex = ext->xor_ex;
149 }
150
151 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
152 descs[0] = (struct ioat_raw_descriptor *) xor;
153 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
154 for (i = 0; i < src_cnt; i++) {
155 dma_addr_t src = xor_get_src(descs, i);
156
157 ioat_unmap(pdev, src - offset, len,
158 PCI_DMA_TODEVICE, flags, 0);
159 }
160
161 /* dest is a source in xor validate operations */
162 if (xor->ctl_f.op == IOAT_OP_XOR_VAL) {
163 ioat_unmap(pdev, xor->dst_addr - offset, len,
164 PCI_DMA_TODEVICE, flags, 1);
165 break;
166 }
167 }
168
169 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
170 ioat_unmap(pdev, xor->dst_addr - offset, len,
171 PCI_DMA_FROMDEVICE, flags, 1);
172 break;
173 }
Dan Williamsd69d235b2009-09-08 17:42:59 -0700174 case IOAT_OP_PQ_VAL:
175 case IOAT_OP_PQ: {
176 struct ioat_pq_descriptor *pq = desc->pq;
177 struct ioat_ring_ent *ext;
178 struct ioat_pq_ext_descriptor *pq_ex = NULL;
179 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
180 struct ioat_raw_descriptor *descs[2];
181 int i;
182
183 if (src_cnt > 3) {
184 ext = ioat2_get_ring_ent(ioat, idx + 1);
185 pq_ex = ext->pq_ex;
186 }
187
188 /* in the 'continue' case don't unmap the dests as sources */
189 if (dmaf_p_disabled_continue(flags))
190 src_cnt--;
191 else if (dmaf_continue(flags))
192 src_cnt -= 3;
193
194 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
195 descs[0] = (struct ioat_raw_descriptor *) pq;
196 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
197 for (i = 0; i < src_cnt; i++) {
198 dma_addr_t src = pq_get_src(descs, i);
199
200 ioat_unmap(pdev, src - offset, len,
201 PCI_DMA_TODEVICE, flags, 0);
202 }
203
204 /* the dests are sources in pq validate operations */
205 if (pq->ctl_f.op == IOAT_OP_XOR_VAL) {
206 if (!(flags & DMA_PREP_PQ_DISABLE_P))
207 ioat_unmap(pdev, pq->p_addr - offset,
208 len, PCI_DMA_TODEVICE, flags, 0);
209 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
210 ioat_unmap(pdev, pq->q_addr - offset,
211 len, PCI_DMA_TODEVICE, flags, 0);
212 break;
213 }
214 }
215
216 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
217 if (!(flags & DMA_PREP_PQ_DISABLE_P))
218 ioat_unmap(pdev, pq->p_addr - offset, len,
219 PCI_DMA_BIDIRECTIONAL, flags, 1);
220 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
221 ioat_unmap(pdev, pq->q_addr - offset, len,
222 PCI_DMA_BIDIRECTIONAL, flags, 1);
223 }
224 break;
225 }
Dan Williamsbf40a682009-09-08 17:42:55 -0700226 default:
227 dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
228 __func__, desc->hw->ctl_f.op);
229 }
230}
231
Dan Williamsb094ad32009-09-08 17:42:57 -0700232static bool desc_has_ext(struct ioat_ring_ent *desc)
233{
234 struct ioat_dma_descriptor *hw = desc->hw;
Dan Williamsbf40a682009-09-08 17:42:55 -0700235
Dan Williamsb094ad32009-09-08 17:42:57 -0700236 if (hw->ctl_f.op == IOAT_OP_XOR ||
237 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
238 struct ioat_xor_descriptor *xor = desc->xor;
239
240 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
241 return true;
Dan Williamsd69d235b2009-09-08 17:42:59 -0700242 } else if (hw->ctl_f.op == IOAT_OP_PQ ||
243 hw->ctl_f.op == IOAT_OP_PQ_VAL) {
244 struct ioat_pq_descriptor *pq = desc->pq;
245
246 if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
247 return true;
Dan Williamsb094ad32009-09-08 17:42:57 -0700248 }
249
250 return false;
251}
252
253/**
254 * __cleanup - reclaim used descriptors
255 * @ioat: channel (ring) to clean
256 *
257 * The difference from the dma_v2.c __cleanup() is that this routine
258 * handles extended descriptors and dma-unmapping raid operations.
259 */
Dan Williams27502932012-03-23 13:36:42 -0700260static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
Dan Williamsbf40a682009-09-08 17:42:55 -0700261{
262 struct ioat_chan_common *chan = &ioat->base;
263 struct ioat_ring_ent *desc;
264 bool seen_current = false;
Dan Williams074cc472010-05-01 15:22:55 -0700265 int idx = ioat->tail, i;
Dan Williamsbf40a682009-09-08 17:42:55 -0700266 u16 active;
Dan Williamsbf40a682009-09-08 17:42:55 -0700267
268 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
269 __func__, ioat->head, ioat->tail, ioat->issued);
270
271 active = ioat2_ring_active(ioat);
272 for (i = 0; i < active && !seen_current; i++) {
273 struct dma_async_tx_descriptor *tx;
274
Dan Williams074cc472010-05-01 15:22:55 -0700275 smp_read_barrier_depends();
276 prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
277 desc = ioat2_get_ring_ent(ioat, idx + i);
Dan Williamsbf40a682009-09-08 17:42:55 -0700278 dump_desc_dbg(ioat, desc);
279 tx = &desc->txd;
280 if (tx->cookie) {
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +0000281 dma_cookie_complete(tx);
Dan Williams074cc472010-05-01 15:22:55 -0700282 ioat3_dma_unmap(ioat, desc, idx + i);
Dan Williamsbf40a682009-09-08 17:42:55 -0700283 if (tx->callback) {
284 tx->callback(tx->callback_param);
285 tx->callback = NULL;
286 }
287 }
288
289 if (tx->phys == phys_complete)
290 seen_current = true;
Dan Williamsb094ad32009-09-08 17:42:57 -0700291
292 /* skip extended descriptors */
293 if (desc_has_ext(desc)) {
294 BUG_ON(i + 1 >= active);
295 i++;
296 }
Dan Williamsbf40a682009-09-08 17:42:55 -0700297 }
Dan Williams074cc472010-05-01 15:22:55 -0700298 smp_mb(); /* finish all descriptor reads before incrementing tail */
299 ioat->tail = idx + i;
Dan Williamsaa75db02010-03-03 21:21:10 -0700300 BUG_ON(active && !seen_current); /* no active descs have written a completion? */
Dan Williamsbf40a682009-09-08 17:42:55 -0700301 chan->last_completion = phys_complete;
Dan Williamsb9cc9862010-03-03 21:21:13 -0700302
Dan Williams074cc472010-05-01 15:22:55 -0700303 if (active - i == 0) {
Dan Williamsbf40a682009-09-08 17:42:55 -0700304 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
305 __func__);
306 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
307 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
308 }
Dan Williamsb9cc9862010-03-03 21:21:13 -0700309 /* 5 microsecond delay per pending descriptor */
Dan Williams074cc472010-05-01 15:22:55 -0700310 writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK),
Dan Williamsb9cc9862010-03-03 21:21:13 -0700311 chan->device->reg_base + IOAT_INTRDELAY_OFFSET);
Dan Williamsbf40a682009-09-08 17:42:55 -0700312}
313
Dan Williams074cc472010-05-01 15:22:55 -0700314static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
Dan Williamsbf40a682009-09-08 17:42:55 -0700315{
316 struct ioat_chan_common *chan = &ioat->base;
Dan Williams27502932012-03-23 13:36:42 -0700317 dma_addr_t phys_complete;
Dan Williamsbf40a682009-09-08 17:42:55 -0700318
Dan Williamsb9cc9862010-03-03 21:21:13 -0700319 spin_lock_bh(&chan->cleanup_lock);
Dan Williams074cc472010-05-01 15:22:55 -0700320 if (ioat_cleanup_preamble(chan, &phys_complete))
321 __cleanup(ioat, phys_complete);
Dan Williamsb9cc9862010-03-03 21:21:13 -0700322 spin_unlock_bh(&chan->cleanup_lock);
323}
324
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700325static void ioat3_cleanup_event(unsigned long data)
Dan Williamsbf40a682009-09-08 17:42:55 -0700326{
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700327 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
Dan Williamsbf40a682009-09-08 17:42:55 -0700328
Dan Williams074cc472010-05-01 15:22:55 -0700329 ioat3_cleanup(ioat);
Dan Williams773d9e22010-03-03 11:47:42 -0700330 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
Dan Williamsbf40a682009-09-08 17:42:55 -0700331}
332
333static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
334{
335 struct ioat_chan_common *chan = &ioat->base;
Dan Williams27502932012-03-23 13:36:42 -0700336 dma_addr_t phys_complete;
Dan Williamsbf40a682009-09-08 17:42:55 -0700337
Dan Williamsb372ec22010-03-03 11:47:42 -0700338 ioat2_quiesce(chan, 0);
Dan Williamsbf40a682009-09-08 17:42:55 -0700339 if (ioat_cleanup_preamble(chan, &phys_complete))
340 __cleanup(ioat, phys_complete);
341
342 __ioat2_restart_chan(ioat);
343}
344
345static void ioat3_timer_event(unsigned long data)
346{
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700347 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
Dan Williamsbf40a682009-09-08 17:42:55 -0700348 struct ioat_chan_common *chan = &ioat->base;
349
Dan Williamsbf40a682009-09-08 17:42:55 -0700350 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
Dan Williams27502932012-03-23 13:36:42 -0700351 dma_addr_t phys_complete;
Dan Williamsbf40a682009-09-08 17:42:55 -0700352 u64 status;
353
Dan Williamsbf40a682009-09-08 17:42:55 -0700354 status = ioat_chansts(chan);
355
356 /* when halted due to errors check for channel
357 * programming errors before advancing the completion state
358 */
359 if (is_ioat_halted(status)) {
360 u32 chanerr;
361
362 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
Dan Williamsb57014d2009-11-19 17:10:07 -0700363 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
364 __func__, chanerr);
Dan Williams556ab452010-07-23 15:47:56 -0700365 if (test_bit(IOAT_RUN, &chan->state))
366 BUG_ON(is_ioat_bug(chanerr));
367 else /* we never got off the ground */
368 return;
Dan Williamsbf40a682009-09-08 17:42:55 -0700369 }
370
371 /* if we haven't made progress and we have already
372 * acknowledged a pending completion once, then be more
373 * forceful with a restart
374 */
Dan Williams074cc472010-05-01 15:22:55 -0700375 spin_lock_bh(&chan->cleanup_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700376 if (ioat_cleanup_preamble(chan, &phys_complete))
377 __cleanup(ioat, phys_complete);
Dan Williams074cc472010-05-01 15:22:55 -0700378 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
379 spin_lock_bh(&ioat->prep_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700380 ioat3_restart_channel(ioat);
Dan Williams074cc472010-05-01 15:22:55 -0700381 spin_unlock_bh(&ioat->prep_lock);
382 } else {
Dan Williamsbf40a682009-09-08 17:42:55 -0700383 set_bit(IOAT_COMPLETION_ACK, &chan->state);
384 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
385 }
Dan Williams074cc472010-05-01 15:22:55 -0700386 spin_unlock_bh(&chan->cleanup_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700387 } else {
388 u16 active;
389
390 /* if the ring is idle, empty, and oversized try to step
391 * down the size
392 */
Dan Williams074cc472010-05-01 15:22:55 -0700393 spin_lock_bh(&chan->cleanup_lock);
394 spin_lock_bh(&ioat->prep_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700395 active = ioat2_ring_active(ioat);
396 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
397 reshape_ring(ioat, ioat->alloc_order-1);
Dan Williams074cc472010-05-01 15:22:55 -0700398 spin_unlock_bh(&ioat->prep_lock);
399 spin_unlock_bh(&chan->cleanup_lock);
Dan Williamsbf40a682009-09-08 17:42:55 -0700400
401 /* keep shrinking until we get back to our minimum
402 * default size
403 */
404 if (ioat->alloc_order > ioat_get_alloc_order())
405 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
406 }
Dan Williamsbf40a682009-09-08 17:42:55 -0700407}
408
409static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -0700410ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
411 struct dma_tx_state *txstate)
Dan Williamsbf40a682009-09-08 17:42:55 -0700412{
413 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000414 enum dma_status ret;
Dan Williamsbf40a682009-09-08 17:42:55 -0700415
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000416 ret = dma_cookie_status(c, cookie, txstate);
417 if (ret == DMA_SUCCESS)
418 return ret;
Dan Williamsbf40a682009-09-08 17:42:55 -0700419
Dan Williams074cc472010-05-01 15:22:55 -0700420 ioat3_cleanup(ioat);
Dan Williamsbf40a682009-09-08 17:42:55 -0700421
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000422 return dma_cookie_status(c, cookie, txstate);
Dan Williamsbf40a682009-09-08 17:42:55 -0700423}
424
425static struct dma_async_tx_descriptor *
426ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
427 size_t len, unsigned long flags)
428{
429 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
430 struct ioat_ring_ent *desc;
431 size_t total_len = len;
432 struct ioat_fill_descriptor *fill;
Dan Williamsbf40a682009-09-08 17:42:55 -0700433 u64 src_data = (0x0101010101010101ULL) * (value & 0xff);
Dan Williams074cc472010-05-01 15:22:55 -0700434 int num_descs, idx, i;
Dan Williamsbf40a682009-09-08 17:42:55 -0700435
436 num_descs = ioat2_xferlen_to_descs(ioat, len);
Dan Williams074cc472010-05-01 15:22:55 -0700437 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0)
438 idx = ioat->head;
Dan Williamsbf40a682009-09-08 17:42:55 -0700439 else
440 return NULL;
Dan Williamscdef57d2009-09-21 09:22:29 -0700441 i = 0;
442 do {
Dan Williamsbf40a682009-09-08 17:42:55 -0700443 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
444
445 desc = ioat2_get_ring_ent(ioat, idx + i);
446 fill = desc->fill;
447
448 fill->size = xfer_size;
449 fill->src_data = src_data;
450 fill->dst_addr = dest;
451 fill->ctl = 0;
452 fill->ctl_f.op = IOAT_OP_FILL;
453
454 len -= xfer_size;
455 dest += xfer_size;
456 dump_desc_dbg(ioat, desc);
Dan Williamscdef57d2009-09-21 09:22:29 -0700457 } while (++i < num_descs);
Dan Williamsbf40a682009-09-08 17:42:55 -0700458
459 desc->txd.flags = flags;
460 desc->len = total_len;
461 fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
462 fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
463 fill->ctl_f.compl_write = 1;
464 dump_desc_dbg(ioat, desc);
465
466 /* we leave the channel locked to ensure in order submission */
467 return &desc->txd;
468}
469
Dan Williamsb094ad32009-09-08 17:42:57 -0700470static struct dma_async_tx_descriptor *
471__ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
472 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
473 size_t len, unsigned long flags)
474{
475 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
476 struct ioat_ring_ent *compl_desc;
477 struct ioat_ring_ent *desc;
478 struct ioat_ring_ent *ext;
479 size_t total_len = len;
480 struct ioat_xor_descriptor *xor;
481 struct ioat_xor_ext_descriptor *xor_ex = NULL;
482 struct ioat_dma_descriptor *hw;
Dan Williams074cc472010-05-01 15:22:55 -0700483 int num_descs, with_ext, idx, i;
Dan Williamsb094ad32009-09-08 17:42:57 -0700484 u32 offset = 0;
Dan Williamsb094ad32009-09-08 17:42:57 -0700485 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
486
487 BUG_ON(src_cnt < 2);
488
489 num_descs = ioat2_xferlen_to_descs(ioat, len);
490 /* we need 2x the number of descriptors to cover greater than 5
491 * sources
492 */
493 if (src_cnt > 5) {
494 with_ext = 1;
495 num_descs *= 2;
496 } else
497 with_ext = 0;
498
499 /* completion writes from the raid engine may pass completion
500 * writes from the legacy engine, so we need one extra null
501 * (legacy) descriptor to ensure all completion writes arrive in
502 * order.
503 */
Dan Williams074cc472010-05-01 15:22:55 -0700504 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs+1) == 0)
505 idx = ioat->head;
Dan Williamsb094ad32009-09-08 17:42:57 -0700506 else
507 return NULL;
Dan Williamscdef57d2009-09-21 09:22:29 -0700508 i = 0;
509 do {
Dan Williamsb094ad32009-09-08 17:42:57 -0700510 struct ioat_raw_descriptor *descs[2];
511 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
512 int s;
513
514 desc = ioat2_get_ring_ent(ioat, idx + i);
515 xor = desc->xor;
516
517 /* save a branch by unconditionally retrieving the
518 * extended descriptor xor_set_src() knows to not write
519 * to it in the single descriptor case
520 */
521 ext = ioat2_get_ring_ent(ioat, idx + i + 1);
522 xor_ex = ext->xor_ex;
523
524 descs[0] = (struct ioat_raw_descriptor *) xor;
525 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
526 for (s = 0; s < src_cnt; s++)
527 xor_set_src(descs, src[s], offset, s);
528 xor->size = xfer_size;
529 xor->dst_addr = dest + offset;
530 xor->ctl = 0;
531 xor->ctl_f.op = op;
532 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
533
534 len -= xfer_size;
535 offset += xfer_size;
536 dump_desc_dbg(ioat, desc);
Dan Williamscdef57d2009-09-21 09:22:29 -0700537 } while ((i += 1 + with_ext) < num_descs);
Dan Williamsb094ad32009-09-08 17:42:57 -0700538
539 /* last xor descriptor carries the unmap parameters and fence bit */
540 desc->txd.flags = flags;
541 desc->len = total_len;
542 if (result)
543 desc->result = result;
544 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
545
546 /* completion descriptor carries interrupt bit */
547 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
548 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
549 hw = compl_desc->hw;
550 hw->ctl = 0;
551 hw->ctl_f.null = 1;
552 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
553 hw->ctl_f.compl_write = 1;
554 hw->size = NULL_DESC_BUFFER_SIZE;
555 dump_desc_dbg(ioat, compl_desc);
556
557 /* we leave the channel locked to ensure in order submission */
Dan Williams49954c12009-11-19 17:11:03 -0700558 return &compl_desc->txd;
Dan Williamsb094ad32009-09-08 17:42:57 -0700559}
560
561static struct dma_async_tx_descriptor *
562ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
563 unsigned int src_cnt, size_t len, unsigned long flags)
564{
565 return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
566}
567
568struct dma_async_tx_descriptor *
569ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
570 unsigned int src_cnt, size_t len,
571 enum sum_check_flags *result, unsigned long flags)
572{
573 /* the cleanup routine only sets bits on validate failure, it
574 * does not clear bits on validate success... so clear it here
575 */
576 *result = 0;
577
578 return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
579 src_cnt - 1, len, flags);
580}
581
Dan Williamsd69d235b2009-09-08 17:42:59 -0700582static void
583dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext)
584{
585 struct device *dev = to_dev(&ioat->base);
586 struct ioat_pq_descriptor *pq = desc->pq;
587 struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
588 struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
589 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
590 int i;
591
592 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
593 " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n",
594 desc_id(desc), (unsigned long long) desc->txd.phys,
595 (unsigned long long) (pq_ex ? pq_ex->next : pq->next),
596 desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en,
597 pq->ctl_f.compl_write,
598 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
599 pq->ctl_f.src_cnt);
600 for (i = 0; i < src_cnt; i++)
601 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
602 (unsigned long long) pq_get_src(descs, i), pq->coef[i]);
603 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
604 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
605}
606
607static struct dma_async_tx_descriptor *
608__ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
609 const dma_addr_t *dst, const dma_addr_t *src,
610 unsigned int src_cnt, const unsigned char *scf,
611 size_t len, unsigned long flags)
612{
613 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
614 struct ioat_chan_common *chan = &ioat->base;
615 struct ioat_ring_ent *compl_desc;
616 struct ioat_ring_ent *desc;
617 struct ioat_ring_ent *ext;
618 size_t total_len = len;
619 struct ioat_pq_descriptor *pq;
620 struct ioat_pq_ext_descriptor *pq_ex = NULL;
621 struct ioat_dma_descriptor *hw;
622 u32 offset = 0;
Dan Williamsd69d235b2009-09-08 17:42:59 -0700623 u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
Dan Williams074cc472010-05-01 15:22:55 -0700624 int i, s, idx, with_ext, num_descs;
Dan Williamsd69d235b2009-09-08 17:42:59 -0700625
626 dev_dbg(to_dev(chan), "%s\n", __func__);
627 /* the engine requires at least two sources (we provide
628 * at least 1 implied source in the DMA_PREP_CONTINUE case)
629 */
630 BUG_ON(src_cnt + dmaf_continue(flags) < 2);
631
632 num_descs = ioat2_xferlen_to_descs(ioat, len);
633 /* we need 2x the number of descriptors to cover greater than 3
Dan Williamscd788092009-12-17 13:52:39 -0700634 * sources (we need 1 extra source in the q-only continuation
635 * case and 3 extra sources in the p+q continuation case.
Dan Williamsd69d235b2009-09-08 17:42:59 -0700636 */
Dan Williamscd788092009-12-17 13:52:39 -0700637 if (src_cnt + dmaf_p_disabled_continue(flags) > 3 ||
638 (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) {
Dan Williamsd69d235b2009-09-08 17:42:59 -0700639 with_ext = 1;
640 num_descs *= 2;
641 } else
642 with_ext = 0;
643
644 /* completion writes from the raid engine may pass completion
645 * writes from the legacy engine, so we need one extra null
646 * (legacy) descriptor to ensure all completion writes arrive in
647 * order.
648 */
649 if (likely(num_descs) &&
Dan Williams074cc472010-05-01 15:22:55 -0700650 ioat2_check_space_lock(ioat, num_descs+1) == 0)
651 idx = ioat->head;
Dan Williamsd69d235b2009-09-08 17:42:59 -0700652 else
653 return NULL;
Dan Williamscdef57d2009-09-21 09:22:29 -0700654 i = 0;
655 do {
Dan Williamsd69d235b2009-09-08 17:42:59 -0700656 struct ioat_raw_descriptor *descs[2];
657 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
658
659 desc = ioat2_get_ring_ent(ioat, idx + i);
660 pq = desc->pq;
661
662 /* save a branch by unconditionally retrieving the
663 * extended descriptor pq_set_src() knows to not write
664 * to it in the single descriptor case
665 */
666 ext = ioat2_get_ring_ent(ioat, idx + i + with_ext);
667 pq_ex = ext->pq_ex;
668
669 descs[0] = (struct ioat_raw_descriptor *) pq;
670 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
671
672 for (s = 0; s < src_cnt; s++)
673 pq_set_src(descs, src[s], offset, scf[s], s);
674
675 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
676 if (dmaf_p_disabled_continue(flags))
677 pq_set_src(descs, dst[1], offset, 1, s++);
678 else if (dmaf_continue(flags)) {
679 pq_set_src(descs, dst[0], offset, 0, s++);
680 pq_set_src(descs, dst[1], offset, 1, s++);
681 pq_set_src(descs, dst[1], offset, 0, s++);
682 }
683 pq->size = xfer_size;
684 pq->p_addr = dst[0] + offset;
685 pq->q_addr = dst[1] + offset;
686 pq->ctl = 0;
687 pq->ctl_f.op = op;
688 pq->ctl_f.src_cnt = src_cnt_to_hw(s);
689 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
690 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
691
692 len -= xfer_size;
693 offset += xfer_size;
Dan Williamscdef57d2009-09-21 09:22:29 -0700694 } while ((i += 1 + with_ext) < num_descs);
Dan Williamsd69d235b2009-09-08 17:42:59 -0700695
696 /* last pq descriptor carries the unmap parameters and fence bit */
697 desc->txd.flags = flags;
698 desc->len = total_len;
699 if (result)
700 desc->result = result;
701 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
702 dump_pq_desc_dbg(ioat, desc, ext);
703
704 /* completion descriptor carries interrupt bit */
705 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
706 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
707 hw = compl_desc->hw;
708 hw->ctl = 0;
709 hw->ctl_f.null = 1;
710 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
711 hw->ctl_f.compl_write = 1;
712 hw->size = NULL_DESC_BUFFER_SIZE;
713 dump_desc_dbg(ioat, compl_desc);
714
715 /* we leave the channel locked to ensure in order submission */
Dan Williams49954c12009-11-19 17:11:03 -0700716 return &compl_desc->txd;
Dan Williamsd69d235b2009-09-08 17:42:59 -0700717}
718
719static struct dma_async_tx_descriptor *
720ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
721 unsigned int src_cnt, const unsigned char *scf, size_t len,
722 unsigned long flags)
723{
Dan Williamsde581b62009-11-19 17:08:45 -0700724 /* specify valid address for disabled result */
725 if (flags & DMA_PREP_PQ_DISABLE_P)
726 dst[0] = dst[1];
727 if (flags & DMA_PREP_PQ_DISABLE_Q)
728 dst[1] = dst[0];
729
Dan Williamsd69d235b2009-09-08 17:42:59 -0700730 /* handle the single source multiply case from the raid6
731 * recovery path
732 */
Dan Williamsde581b62009-11-19 17:08:45 -0700733 if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) {
Dan Williamsd69d235b2009-09-08 17:42:59 -0700734 dma_addr_t single_source[2];
735 unsigned char single_source_coef[2];
736
737 BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
738 single_source[0] = src[0];
739 single_source[1] = src[0];
740 single_source_coef[0] = scf[0];
741 single_source_coef[1] = 0;
742
743 return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2,
744 single_source_coef, len, flags);
745 } else
746 return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf,
747 len, flags);
748}
749
750struct dma_async_tx_descriptor *
751ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
752 unsigned int src_cnt, const unsigned char *scf, size_t len,
753 enum sum_check_flags *pqres, unsigned long flags)
754{
Dan Williamsde581b62009-11-19 17:08:45 -0700755 /* specify valid address for disabled result */
756 if (flags & DMA_PREP_PQ_DISABLE_P)
757 pq[0] = pq[1];
758 if (flags & DMA_PREP_PQ_DISABLE_Q)
759 pq[1] = pq[0];
760
Dan Williamsd69d235b2009-09-08 17:42:59 -0700761 /* the cleanup routine only sets bits on validate failure, it
762 * does not clear bits on validate success... so clear it here
763 */
764 *pqres = 0;
765
766 return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
767 flags);
768}
769
Dan Williamsae786622009-09-08 17:43:00 -0700770static struct dma_async_tx_descriptor *
771ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
772 unsigned int src_cnt, size_t len, unsigned long flags)
773{
774 unsigned char scf[src_cnt];
775 dma_addr_t pq[2];
776
777 memset(scf, 0, src_cnt);
Dan Williamsae786622009-09-08 17:43:00 -0700778 pq[0] = dst;
Dan Williamsde581b62009-11-19 17:08:45 -0700779 flags |= DMA_PREP_PQ_DISABLE_Q;
780 pq[1] = dst; /* specify valid address for disabled result */
Dan Williamsae786622009-09-08 17:43:00 -0700781
782 return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len,
783 flags);
784}
785
786struct dma_async_tx_descriptor *
787ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
788 unsigned int src_cnt, size_t len,
789 enum sum_check_flags *result, unsigned long flags)
790{
791 unsigned char scf[src_cnt];
792 dma_addr_t pq[2];
793
794 /* the cleanup routine only sets bits on validate failure, it
795 * does not clear bits on validate success... so clear it here
796 */
797 *result = 0;
798
799 memset(scf, 0, src_cnt);
Dan Williamsae786622009-09-08 17:43:00 -0700800 pq[0] = src[0];
Dan Williamsde581b62009-11-19 17:08:45 -0700801 flags |= DMA_PREP_PQ_DISABLE_Q;
802 pq[1] = pq[0]; /* specify valid address for disabled result */
Dan Williamsae786622009-09-08 17:43:00 -0700803
804 return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf,
805 len, flags);
806}
807
Dan Williams58c86492009-09-08 17:43:00 -0700808static struct dma_async_tx_descriptor *
809ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
810{
811 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
812 struct ioat_ring_ent *desc;
813 struct ioat_dma_descriptor *hw;
Dan Williams58c86492009-09-08 17:43:00 -0700814
Dan Williams074cc472010-05-01 15:22:55 -0700815 if (ioat2_check_space_lock(ioat, 1) == 0)
816 desc = ioat2_get_ring_ent(ioat, ioat->head);
Dan Williams58c86492009-09-08 17:43:00 -0700817 else
818 return NULL;
819
820 hw = desc->hw;
821 hw->ctl = 0;
822 hw->ctl_f.null = 1;
823 hw->ctl_f.int_en = 1;
824 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
825 hw->ctl_f.compl_write = 1;
826 hw->size = NULL_DESC_BUFFER_SIZE;
827 hw->src_addr = 0;
828 hw->dst_addr = 0;
829
830 desc->txd.flags = flags;
831 desc->len = 1;
832
833 dump_desc_dbg(ioat, desc);
834
835 /* we leave the channel locked to ensure in order submission */
836 return &desc->txd;
837}
838
Dan Williams9de6fc72009-09-08 17:42:58 -0700839static void __devinit ioat3_dma_test_callback(void *dma_async_param)
840{
841 struct completion *cmp = dma_async_param;
842
843 complete(cmp);
844}
845
846#define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
847static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device)
848{
849 int i, src_idx;
850 struct page *dest;
851 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
852 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
853 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
854 dma_addr_t dma_addr, dest_dma;
855 struct dma_async_tx_descriptor *tx;
856 struct dma_chan *dma_chan;
857 dma_cookie_t cookie;
858 u8 cmp_byte = 0;
859 u32 cmp_word;
860 u32 xor_val_result;
861 int err = 0;
862 struct completion cmp;
863 unsigned long tmo;
864 struct device *dev = &device->pdev->dev;
865 struct dma_device *dma = &device->common;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000866 u8 op = 0;
Dan Williams9de6fc72009-09-08 17:42:58 -0700867
868 dev_dbg(dev, "%s\n", __func__);
869
870 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
871 return 0;
872
873 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
874 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
875 if (!xor_srcs[src_idx]) {
876 while (src_idx--)
877 __free_page(xor_srcs[src_idx]);
878 return -ENOMEM;
879 }
880 }
881
882 dest = alloc_page(GFP_KERNEL);
883 if (!dest) {
884 while (src_idx--)
885 __free_page(xor_srcs[src_idx]);
886 return -ENOMEM;
887 }
888
889 /* Fill in src buffers */
890 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
891 u8 *ptr = page_address(xor_srcs[src_idx]);
892 for (i = 0; i < PAGE_SIZE; i++)
893 ptr[i] = (1 << src_idx);
894 }
895
896 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
897 cmp_byte ^= (u8) (1 << src_idx);
898
899 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
900 (cmp_byte << 8) | cmp_byte;
901
902 memset(page_address(dest), 0, PAGE_SIZE);
903
904 dma_chan = container_of(dma->channels.next, struct dma_chan,
905 device_node);
906 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
907 err = -ENODEV;
908 goto out;
909 }
910
911 /* test xor */
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000912 op = IOAT_OP_XOR;
913
Dan Williams9de6fc72009-09-08 17:42:58 -0700914 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
915 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
916 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
917 DMA_TO_DEVICE);
918 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
919 IOAT_NUM_SRC_TEST, PAGE_SIZE,
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000920 DMA_PREP_INTERRUPT |
921 DMA_COMPL_SKIP_SRC_UNMAP |
922 DMA_COMPL_SKIP_DEST_UNMAP);
Dan Williams9de6fc72009-09-08 17:42:58 -0700923
924 if (!tx) {
925 dev_err(dev, "Self-test xor prep failed\n");
926 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000927 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -0700928 }
929
930 async_tx_ack(tx);
931 init_completion(&cmp);
932 tx->callback = ioat3_dma_test_callback;
933 tx->callback_param = &cmp;
934 cookie = tx->tx_submit(tx);
935 if (cookie < 0) {
936 dev_err(dev, "Self-test xor setup failed\n");
937 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000938 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -0700939 }
940 dma->device_issue_pending(dma_chan);
941
942 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
943
Linus Walleij07934482010-03-26 16:50:49 -0700944 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
Dan Williams9de6fc72009-09-08 17:42:58 -0700945 dev_err(dev, "Self-test xor timed out\n");
946 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000947 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -0700948 }
949
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000950 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
951 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
952 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
953
Dan Williams9de6fc72009-09-08 17:42:58 -0700954 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
955 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
956 u32 *ptr = page_address(dest);
957 if (ptr[i] != cmp_word) {
958 dev_err(dev, "Self-test xor failed compare\n");
959 err = -ENODEV;
960 goto free_resources;
961 }
962 }
963 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE);
964
965 /* skip validate if the capability is not present */
966 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
967 goto free_resources;
968
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000969 op = IOAT_OP_XOR_VAL;
970
Dan Williams9de6fc72009-09-08 17:42:58 -0700971 /* validate the sources with the destintation page */
972 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
973 xor_val_srcs[i] = xor_srcs[i];
974 xor_val_srcs[i] = dest;
975
976 xor_val_result = 1;
977
978 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
979 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
980 DMA_TO_DEVICE);
981 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
982 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000983 &xor_val_result, DMA_PREP_INTERRUPT |
984 DMA_COMPL_SKIP_SRC_UNMAP |
985 DMA_COMPL_SKIP_DEST_UNMAP);
Dan Williams9de6fc72009-09-08 17:42:58 -0700986 if (!tx) {
987 dev_err(dev, "Self-test zero prep failed\n");
988 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +0000989 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -0700990 }
991
992 async_tx_ack(tx);
993 init_completion(&cmp);
994 tx->callback = ioat3_dma_test_callback;
995 tx->callback_param = &cmp;
996 cookie = tx->tx_submit(tx);
997 if (cookie < 0) {
998 dev_err(dev, "Self-test zero setup failed\n");
999 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001000 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001001 }
1002 dma->device_issue_pending(dma_chan);
1003
1004 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1005
Linus Walleij07934482010-03-26 16:50:49 -07001006 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
Dan Williams9de6fc72009-09-08 17:42:58 -07001007 dev_err(dev, "Self-test validate timed out\n");
1008 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001009 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001010 }
1011
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001012 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1013 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1014
Dan Williams9de6fc72009-09-08 17:42:58 -07001015 if (xor_val_result != 0) {
1016 dev_err(dev, "Self-test validate failed compare\n");
1017 err = -ENODEV;
1018 goto free_resources;
1019 }
1020
1021 /* skip memset if the capability is not present */
1022 if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask))
1023 goto free_resources;
1024
1025 /* test memset */
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001026 op = IOAT_OP_FILL;
1027
Dan Williams9de6fc72009-09-08 17:42:58 -07001028 dma_addr = dma_map_page(dev, dest, 0,
1029 PAGE_SIZE, DMA_FROM_DEVICE);
1030 tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001031 DMA_PREP_INTERRUPT |
1032 DMA_COMPL_SKIP_SRC_UNMAP |
1033 DMA_COMPL_SKIP_DEST_UNMAP);
Dan Williams9de6fc72009-09-08 17:42:58 -07001034 if (!tx) {
1035 dev_err(dev, "Self-test memset prep failed\n");
1036 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001037 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001038 }
1039
1040 async_tx_ack(tx);
1041 init_completion(&cmp);
1042 tx->callback = ioat3_dma_test_callback;
1043 tx->callback_param = &cmp;
1044 cookie = tx->tx_submit(tx);
1045 if (cookie < 0) {
1046 dev_err(dev, "Self-test memset setup failed\n");
1047 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001048 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001049 }
1050 dma->device_issue_pending(dma_chan);
1051
1052 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1053
Linus Walleij07934482010-03-26 16:50:49 -07001054 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
Dan Williams9de6fc72009-09-08 17:42:58 -07001055 dev_err(dev, "Self-test memset timed out\n");
1056 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001057 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001058 }
1059
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001060 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
1061
Dan Williams9de6fc72009-09-08 17:42:58 -07001062 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1063 u32 *ptr = page_address(dest);
1064 if (ptr[i]) {
1065 dev_err(dev, "Self-test memset failed compare\n");
1066 err = -ENODEV;
1067 goto free_resources;
1068 }
1069 }
1070
1071 /* test for non-zero parity sum */
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001072 op = IOAT_OP_XOR_VAL;
1073
Dan Williams9de6fc72009-09-08 17:42:58 -07001074 xor_val_result = 0;
1075 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1076 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1077 DMA_TO_DEVICE);
1078 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1079 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001080 &xor_val_result, DMA_PREP_INTERRUPT |
1081 DMA_COMPL_SKIP_SRC_UNMAP |
1082 DMA_COMPL_SKIP_DEST_UNMAP);
Dan Williams9de6fc72009-09-08 17:42:58 -07001083 if (!tx) {
1084 dev_err(dev, "Self-test 2nd zero prep failed\n");
1085 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001086 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001087 }
1088
1089 async_tx_ack(tx);
1090 init_completion(&cmp);
1091 tx->callback = ioat3_dma_test_callback;
1092 tx->callback_param = &cmp;
1093 cookie = tx->tx_submit(tx);
1094 if (cookie < 0) {
1095 dev_err(dev, "Self-test 2nd zero setup failed\n");
1096 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001097 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001098 }
1099 dma->device_issue_pending(dma_chan);
1100
1101 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1102
Linus Walleij07934482010-03-26 16:50:49 -07001103 if (dma->device_tx_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
Dan Williams9de6fc72009-09-08 17:42:58 -07001104 dev_err(dev, "Self-test 2nd validate timed out\n");
1105 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001106 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001107 }
1108
1109 if (xor_val_result != SUM_CHECK_P_RESULT) {
1110 dev_err(dev, "Self-test validate failed compare\n");
1111 err = -ENODEV;
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001112 goto dma_unmap;
Dan Williams9de6fc72009-09-08 17:42:58 -07001113 }
1114
Bartlomiej Zolnierkiewicz7369f562012-11-05 10:00:19 +00001115 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1116 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1117
1118 goto free_resources;
1119dma_unmap:
1120 if (op == IOAT_OP_XOR) {
1121 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1122 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1123 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1124 DMA_TO_DEVICE);
1125 } else if (op == IOAT_OP_XOR_VAL) {
1126 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1127 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1128 DMA_TO_DEVICE);
1129 } else if (op == IOAT_OP_FILL)
1130 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
Dan Williams9de6fc72009-09-08 17:42:58 -07001131free_resources:
1132 dma->device_free_chan_resources(dma_chan);
1133out:
1134 src_idx = IOAT_NUM_SRC_TEST;
1135 while (src_idx--)
1136 __free_page(xor_srcs[src_idx]);
1137 __free_page(dest);
1138 return err;
1139}
1140
1141static int __devinit ioat3_dma_self_test(struct ioatdma_device *device)
1142{
1143 int rc = ioat_dma_self_test(device);
1144
1145 if (rc)
1146 return rc;
1147
1148 rc = ioat_xor_val_self_test(device);
1149 if (rc)
1150 return rc;
1151
1152 return 0;
1153}
1154
Dan Williamsa6d52d72009-12-19 15:36:02 -07001155static int ioat3_reset_hw(struct ioat_chan_common *chan)
1156{
1157 /* throw away whatever the channel was doing and get it
1158 * initialized, with ioat3 specific workarounds
1159 */
1160 struct ioatdma_device *device = chan->device;
1161 struct pci_dev *pdev = device->pdev;
1162 u32 chanerr;
1163 u16 dev_id;
1164 int err;
1165
1166 ioat2_quiesce(chan, msecs_to_jiffies(100));
1167
1168 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
1169 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
1170
1171 /* -= IOAT ver.3 workarounds =- */
1172 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
1173 * that can cause stability issues for IOAT ver.3, and clear any
1174 * pending errors
1175 */
1176 pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
1177 err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
1178 if (err) {
1179 dev_err(&pdev->dev, "channel error register unreachable\n");
1180 return err;
1181 }
1182 pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
1183
1184 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1185 * (workaround for spurious config parity error after restart)
1186 */
1187 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
1188 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
1189 pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
1190
1191 return ioat2_reset_sync(chan, msecs_to_jiffies(200));
1192}
1193
Dave Jiangf26df1a2012-04-04 16:10:41 -07001194static bool is_jf_ioat(struct pci_dev *pdev)
1195{
1196 switch (pdev->device) {
1197 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
1198 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
1199 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
1200 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
1201 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
1202 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
1203 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
1204 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
1205 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
1206 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
1207 return true;
1208 default:
1209 return false;
1210 }
1211}
1212
1213static bool is_snb_ioat(struct pci_dev *pdev)
1214{
1215 switch (pdev->device) {
1216 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
1217 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
1218 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
1219 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
1220 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
1221 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
1222 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
1223 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
1224 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
1225 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
1226 return true;
1227 default:
1228 return false;
1229 }
1230}
1231
Dave Jiang1a363062012-12-03 16:08:37 -07001232static bool is_ivb_ioat(struct pci_dev *pdev)
1233{
1234 switch (pdev->device) {
1235 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
1236 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
1237 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
1238 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
1239 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
1240 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
1241 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
1242 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
1243 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
1244 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
1245 return true;
1246 default:
1247 return false;
1248 }
1249
1250}
1251
Dan Williamsbf40a682009-09-08 17:42:55 -07001252int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
1253{
1254 struct pci_dev *pdev = device->pdev;
Dan Williams228c4f52009-11-19 17:07:10 -07001255 int dca_en = system_has_dca_enabled(pdev);
Dan Williamsbf40a682009-09-08 17:42:55 -07001256 struct dma_device *dma;
1257 struct dma_chan *c;
1258 struct ioat_chan_common *chan;
Dan Williamse3232712009-09-08 17:43:02 -07001259 bool is_raid_device = false;
Dan Williamsbf40a682009-09-08 17:42:55 -07001260 int err;
Dan Williamsbf40a682009-09-08 17:42:55 -07001261 u32 cap;
1262
1263 device->enumerate_channels = ioat2_enumerate_channels;
Dan Williamsa6d52d72009-12-19 15:36:02 -07001264 device->reset_hw = ioat3_reset_hw;
Dan Williams9de6fc72009-09-08 17:42:58 -07001265 device->self_test = ioat3_dma_self_test;
Dan Williamsbf40a682009-09-08 17:42:55 -07001266 dma = &device->common;
1267 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
1268 dma->device_issue_pending = ioat2_issue_pending;
1269 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
1270 dma->device_free_chan_resources = ioat2_free_chan_resources;
Dan Williams58c86492009-09-08 17:43:00 -07001271
Dave Jiang1a363062012-12-03 16:08:37 -07001272 if (is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev))
Dave Jiangf26df1a2012-04-04 16:10:41 -07001273 dma->copy_align = 6;
1274
Dan Williams58c86492009-09-08 17:43:00 -07001275 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1276 dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
1277
Dan Williamsbf40a682009-09-08 17:42:55 -07001278 cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
Dan Williams228c4f52009-11-19 17:07:10 -07001279
1280 /* dca is incompatible with raid operations */
1281 if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1282 cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1283
Dan Williamsb094ad32009-09-08 17:42:57 -07001284 if (cap & IOAT_CAP_XOR) {
Dan Williamse3232712009-09-08 17:43:02 -07001285 is_raid_device = true;
Dan Williamsb094ad32009-09-08 17:42:57 -07001286 dma->max_xor = 8;
Dan Williams2adfc552010-05-01 15:22:56 -07001287 dma->xor_align = 6;
Dan Williamsb094ad32009-09-08 17:42:57 -07001288
1289 dma_cap_set(DMA_XOR, dma->cap_mask);
1290 dma->device_prep_dma_xor = ioat3_prep_xor;
1291
1292 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1293 dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
1294 }
Dan Williamsd69d235b2009-09-08 17:42:59 -07001295 if (cap & IOAT_CAP_PQ) {
Dan Williamse3232712009-09-08 17:43:02 -07001296 is_raid_device = true;
Dan Williamsd69d235b2009-09-08 17:42:59 -07001297 dma_set_maxpq(dma, 8, 0);
Dan Williams2adfc552010-05-01 15:22:56 -07001298 dma->pq_align = 6;
Dan Williamsd69d235b2009-09-08 17:42:59 -07001299
1300 dma_cap_set(DMA_PQ, dma->cap_mask);
1301 dma->device_prep_dma_pq = ioat3_prep_pq;
1302
1303 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1304 dma->device_prep_dma_pq_val = ioat3_prep_pq_val;
Dan Williamsae786622009-09-08 17:43:00 -07001305
1306 if (!(cap & IOAT_CAP_XOR)) {
1307 dma->max_xor = 8;
Dan Williams2adfc552010-05-01 15:22:56 -07001308 dma->xor_align = 6;
Dan Williamsae786622009-09-08 17:43:00 -07001309
1310 dma_cap_set(DMA_XOR, dma->cap_mask);
1311 dma->device_prep_dma_xor = ioat3_prep_pqxor;
1312
1313 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1314 dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val;
1315 }
Dan Williamsd69d235b2009-09-08 17:42:59 -07001316 }
Dan Williamse3232712009-09-08 17:43:02 -07001317 if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) {
1318 dma_cap_set(DMA_MEMSET, dma->cap_mask);
1319 dma->device_prep_dma_memset = ioat3_prep_memset_lock;
1320 }
1321
1322
1323 if (is_raid_device) {
Linus Walleij07934482010-03-26 16:50:49 -07001324 dma->device_tx_status = ioat3_tx_status;
Dan Williamsaa4d72a2010-03-03 21:21:13 -07001325 device->cleanup_fn = ioat3_cleanup_event;
Dan Williamse3232712009-09-08 17:43:02 -07001326 device->timer_fn = ioat3_timer_event;
1327 } else {
Linus Walleij07934482010-03-26 16:50:49 -07001328 dma->device_tx_status = ioat_dma_tx_status;
Dan Williamsaa4d72a2010-03-03 21:21:13 -07001329 device->cleanup_fn = ioat2_cleanup_event;
Dan Williamse3232712009-09-08 17:43:02 -07001330 device->timer_fn = ioat2_timer_event;
1331 }
Dan Williamsbf40a682009-09-08 17:42:55 -07001332
Dan Williams7b3cc2b2009-11-19 17:10:37 -07001333 #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
1334 dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
1335 dma->device_prep_dma_pq_val = NULL;
1336 #endif
1337
1338 #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
1339 dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
1340 dma->device_prep_dma_xor_val = NULL;
1341 #endif
1342
Dan Williamsbf40a682009-09-08 17:42:55 -07001343 err = ioat_probe(device);
1344 if (err)
1345 return err;
1346 ioat_set_tcp_copy_break(262144);
1347
1348 list_for_each_entry(c, &dma->channels, device_node) {
1349 chan = to_chan_common(c);
1350 writel(IOAT_DMA_DCA_ANY_CPU,
1351 chan->reg_base + IOAT_DCACTRL_OFFSET);
1352 }
1353
1354 err = ioat_register(device);
1355 if (err)
1356 return err;
Dan Williams5669e312009-09-08 17:42:56 -07001357
1358 ioat_kobject_add(device, &ioat2_ktype);
1359
Dan Williamsbf40a682009-09-08 17:42:55 -07001360 if (dca)
1361 device->dca = ioat3_dca_init(pdev, device->reg_base);
1362
1363 return 0;
1364}