| Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Chip-specific header file for the SAMA5D3 family |
| 3 | * |
| 4 | * Copyright (C) 2013 Atmel, |
| 5 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> |
| 6 | * |
| 7 | * Common definitions. |
| 8 | * Based on SAMA5D3 datasheet. |
| 9 | * |
| 10 | * Licensed under GPLv2 or later. |
| 11 | */ |
| 12 | |
| 13 | #ifndef SAMA5D3_H |
| 14 | #define SAMA5D3_H |
| 15 | |
| 16 | /* |
| 17 | * Peripheral identifiers/interrupts. |
| 18 | */ |
| 19 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
| 20 | #define AT91_ID_SYS 1 /* System Peripherals */ |
| 21 | #define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ |
| 22 | #define AT91_ID_PIT 3 /* PIT */ |
| 23 | #define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ |
| 24 | #define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ |
| 25 | #define SAMA5D3_ID_PIOA 6 /* PIOA */ |
| 26 | #define SAMA5D3_ID_PIOB 7 /* PIOB */ |
| 27 | #define SAMA5D3_ID_PIOC 8 /* PIOC */ |
| 28 | #define SAMA5D3_ID_PIOD 9 /* PIOD */ |
| 29 | #define SAMA5D3_ID_PIOE 10 /* PIOE */ |
| 30 | #define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ |
| 31 | #define SAMA5D3_ID_USART0 12 /* USART0 */ |
| 32 | #define SAMA5D3_ID_USART1 13 /* USART1 */ |
| 33 | #define SAMA5D3_ID_USART2 14 /* USART2 */ |
| 34 | #define SAMA5D3_ID_USART3 15 /* USART3 */ |
| 35 | #define SAMA5D3_ID_UART0 16 /* UART 0 */ |
| 36 | #define SAMA5D3_ID_UART1 17 /* UART 1 */ |
| 37 | #define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ |
| 38 | #define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ |
| 39 | #define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ |
| 40 | #define SAMA5D3_ID_HSMCI0 21 /* MCI */ |
| 41 | #define SAMA5D3_ID_HSMCI1 22 /* MCI */ |
| 42 | #define SAMA5D3_ID_HSMCI2 23 /* MCI */ |
| 43 | #define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ |
| 44 | #define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ |
| 45 | #define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ |
| 46 | #define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ |
| 47 | #define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ |
| 48 | #define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ |
| 49 | #define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ |
| 50 | #define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ |
| 51 | #define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ |
| 52 | #define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ |
| 53 | #define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ |
| 54 | #define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ |
| 55 | #define SAMA5D3_ID_LCDC 36 /* LCD Controller */ |
| 56 | #define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ |
| 57 | #define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ |
| 58 | #define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ |
| 59 | #define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ |
| 60 | #define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ |
| 61 | #define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ |
| 62 | #define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ |
| 63 | #define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ |
| 64 | #define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ |
| 65 | #define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ |
| 66 | |
| 67 | /* |
| 68 | * Internal Memory |
| 69 | */ |
| 70 | #define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| 71 | #define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ |
| 72 | |
| 73 | #endif |