blob: 387d484c62f95bf96ed654058f1ad79071f506e6 [file] [log] [blame]
Sam Ravnborgf5e706a2008-07-17 21:55:51 -07001/*
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#ifndef _SPARC64_PGTABLE_H
9#define _SPARC64_PGTABLE_H
10
11/* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070015#include <linux/compiler.h>
16#include <linux/const.h>
17#include <asm/types.h>
18#include <asm/spitfire.h>
19#include <asm/asi.h>
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070020#include <asm/page.h>
21#include <asm/processor.h>
22
Aaro Koskinen2533e822012-04-01 08:54:38 +000023#include <asm-generic/pgtable-nopud.h>
24
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070025/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
26 * The page copy blockops can use 0x6000000 to 0x8000000.
27 * The TSB is mapped in the 0x8000000 to 0xa000000 range.
28 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
29 * The vmalloc area spans 0x100000000 to 0x200000000.
30 * Since modules need to be in the lowest 32-bits of the address space,
31 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
32 * There is a single static kernel PMD which maps from 0x0 to address
33 * 0x400000000.
34 */
35#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
36#define TSBMAP_BASE _AC(0x0000000008000000,UL)
37#define MODULES_VADDR _AC(0x0000000010000000,UL)
38#define MODULES_LEN _AC(0x00000000e0000000,UL)
39#define MODULES_END _AC(0x00000000f0000000,UL)
40#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
42#define VMALLOC_START _AC(0x0000000100000000,UL)
David S. Miller1b6b9d62009-09-28 14:39:58 -070043#define VMALLOC_END _AC(0x0000010000000000,UL)
44#define VMEMMAP_BASE _AC(0x0000010000000000,UL)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070045
46#define vmemmap ((struct page *)VMEMMAP_BASE)
47
48/* XXX All of this needs to be rethought so we can take advantage
49 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
50 * XXX in the middle like on spitfire. -DaveM
51 */
52/*
53 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
54 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
55 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
56 * table is a single page long). The next higher PMD_BITS determine pmd#
57 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
58 * since the pmd entries are 4 bytes, and each pmd page is a single page
59 * long). Finally, the higher few bits determine pgde#.
60 */
61
62/* PMD_SHIFT determines the size of the area a second-level page
63 * table can map
64 */
65#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
66#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
67#define PMD_MASK (~(PMD_SIZE-1))
68#define PMD_BITS (PAGE_SHIFT - 2)
69
70/* PGDIR_SHIFT determines what a third-level page table entry can map */
71#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
72#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
73#define PGDIR_MASK (~(PGDIR_SIZE-1))
74#define PGDIR_BITS (PAGE_SHIFT - 2)
75
76#ifndef __ASSEMBLY__
77
78#include <linux/sched.h>
79
80/* Entries per page directory level. */
81#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
82#define PTRS_PER_PMD (1UL << PMD_BITS)
83#define PTRS_PER_PGD (1UL << PGDIR_BITS)
84
85/* Kernel has a separate 44bit address space. */
86#define FIRST_USER_ADDRESS 0
87
88#define pte_ERROR(e) __builtin_trap()
89#define pmd_ERROR(e) __builtin_trap()
90#define pgd_ERROR(e) __builtin_trap()
91
92#endif /* !(__ASSEMBLY__) */
93
94/* PTE bits which are the same in SUN4U and SUN4V format. */
95#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
96#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
David S. Miller683d2fa2011-07-25 17:12:21 -070097#define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
98
99/* Advertise support for _PAGE_SPECIAL */
100#define __HAVE_ARCH_PTE_SPECIAL
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700101
102/* SUN4U pte bits... */
103#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
104#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
105#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
106#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
107#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
108#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
109#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
David S. Miller683d2fa2011-07-25 17:12:21 -0700110#define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700111#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
112#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
113#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
114#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
115#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
116#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
117#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
118#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
119#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
120#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
121#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
122#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
123#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
124#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
125#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
126#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
127#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
128#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
129#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
130#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
131#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
132
133/* SUN4V pte bits... */
134#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
135#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
136#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
137#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
138#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
139#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
David S. Miller683d2fa2011-07-25 17:12:21 -0700140#define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700141#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
142#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
143#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
144#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
145#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
146#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
147#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
148#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
149#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
150#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
151#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
152#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
153#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
154#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
155#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
156#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
157#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
158#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
159#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
160#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
161#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
162
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700163#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
164#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700165
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700166#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
167#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700168
169/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
170#define __P000 __pgprot(0)
171#define __P001 __pgprot(0)
172#define __P010 __pgprot(0)
173#define __P011 __pgprot(0)
174#define __P100 __pgprot(0)
175#define __P101 __pgprot(0)
176#define __P110 __pgprot(0)
177#define __P111 __pgprot(0)
178
179#define __S000 __pgprot(0)
180#define __S001 __pgprot(0)
181#define __S010 __pgprot(0)
182#define __S011 __pgprot(0)
183#define __S100 __pgprot(0)
184#define __S101 __pgprot(0)
185#define __S110 __pgprot(0)
186#define __S111 __pgprot(0)
187
188#ifndef __ASSEMBLY__
189
190extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
191
192extern unsigned long pte_sz_bits(unsigned long size);
193
194extern pgprot_t PAGE_KERNEL;
195extern pgprot_t PAGE_KERNEL_LOCKED;
196extern pgprot_t PAGE_COPY;
197extern pgprot_t PAGE_SHARED;
198
199/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
200extern unsigned long _PAGE_IE;
201extern unsigned long _PAGE_E;
202extern unsigned long _PAGE_CACHE;
203
204extern unsigned long pg_iobits;
205extern unsigned long _PAGE_ALL_SZ_BITS;
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700206
207extern struct page *mem_map_zero;
208#define ZERO_PAGE(vaddr) (mem_map_zero)
209
210/* PFNs are real physical page numbers. However, mem_map only begins to record
211 * per-page information starting at pfn_base. This is to handle systems where
212 * the first physical page in the machine is at some huge physical address,
213 * such as 4GB. This is common on a partitioned E10000, for example.
214 */
215static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
216{
217 unsigned long paddr = pfn << PAGE_SHIFT;
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700218
David Miller15b93502012-10-08 16:34:19 -0700219 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
220 return __pte(paddr | pgprot_val(prot));
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700221}
222#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
223
224/* This one can be done with two shifts. */
225static inline unsigned long pte_pfn(pte_t pte)
226{
227 unsigned long ret;
228
229 __asm__ __volatile__(
230 "\n661: sllx %1, %2, %0\n"
231 " srlx %0, %3, %0\n"
232 " .section .sun4v_2insn_patch, \"ax\"\n"
233 " .word 661b\n"
234 " sllx %1, %4, %0\n"
235 " srlx %0, %5, %0\n"
236 " .previous\n"
237 : "=r" (ret)
238 : "r" (pte_val(pte)),
239 "i" (21), "i" (21 + PAGE_SHIFT),
240 "i" (8), "i" (8 + PAGE_SHIFT));
241
242 return ret;
243}
244#define pte_page(x) pfn_to_page(pte_pfn(x))
245
246static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
247{
248 unsigned long mask, tmp;
249
250 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
251 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
252 *
253 * Even if we use negation tricks the result is still a 6
254 * instruction sequence, so don't try to play fancy and just
255 * do the most straightforward implementation.
256 *
257 * Note: We encode this into 3 sun4v 2-insn patch sequences.
258 */
259
David Miller15b93502012-10-08 16:34:19 -0700260 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700261 __asm__ __volatile__(
262 "\n661: sethi %%uhi(%2), %1\n"
263 " sethi %%hi(%2), %0\n"
264 "\n662: or %1, %%ulo(%2), %1\n"
265 " or %0, %%lo(%2), %0\n"
266 "\n663: sllx %1, 32, %1\n"
267 " or %0, %1, %0\n"
268 " .section .sun4v_2insn_patch, \"ax\"\n"
269 " .word 661b\n"
270 " sethi %%uhi(%3), %1\n"
271 " sethi %%hi(%3), %0\n"
272 " .word 662b\n"
273 " or %1, %%ulo(%3), %1\n"
274 " or %0, %%lo(%3), %0\n"
275 " .word 663b\n"
276 " sllx %1, 32, %1\n"
277 " or %0, %1, %0\n"
278 " .previous\n"
279 : "=r" (mask), "=r" (tmp)
280 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
281 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
David Miller15b93502012-10-08 16:34:19 -0700282 _PAGE_SPECIAL),
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700283 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
284 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
David Miller15b93502012-10-08 16:34:19 -0700285 _PAGE_SPECIAL));
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700286
287 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
288}
289
290static inline pte_t pgoff_to_pte(unsigned long off)
291{
292 off <<= PAGE_SHIFT;
293
294 __asm__ __volatile__(
295 "\n661: or %0, %2, %0\n"
296 " .section .sun4v_1insn_patch, \"ax\"\n"
297 " .word 661b\n"
298 " or %0, %3, %0\n"
299 " .previous\n"
300 : "=r" (off)
301 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
302
303 return __pte(off);
304}
305
306static inline pgprot_t pgprot_noncached(pgprot_t prot)
307{
308 unsigned long val = pgprot_val(prot);
309
310 __asm__ __volatile__(
311 "\n661: andn %0, %2, %0\n"
312 " or %0, %3, %0\n"
313 " .section .sun4v_2insn_patch, \"ax\"\n"
314 " .word 661b\n"
315 " andn %0, %4, %0\n"
316 " or %0, %5, %0\n"
317 " .previous\n"
318 : "=r" (val)
319 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
320 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
321
322 return __pgprot(val);
323}
324/* Various pieces of code check for platform support by ifdef testing
325 * on "pgprot_noncached". That's broken and should be fixed, but for
326 * now...
327 */
328#define pgprot_noncached pgprot_noncached
329
330#ifdef CONFIG_HUGETLB_PAGE
331static inline pte_t pte_mkhuge(pte_t pte)
332{
333 unsigned long mask;
334
335 __asm__ __volatile__(
336 "\n661: sethi %%uhi(%1), %0\n"
337 " sllx %0, 32, %0\n"
338 " .section .sun4v_2insn_patch, \"ax\"\n"
339 " .word 661b\n"
340 " mov %2, %0\n"
341 " nop\n"
342 " .previous\n"
343 : "=r" (mask)
344 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
345
346 return __pte(pte_val(pte) | mask);
347}
348#endif
349
350static inline pte_t pte_mkdirty(pte_t pte)
351{
352 unsigned long val = pte_val(pte), tmp;
353
354 __asm__ __volatile__(
355 "\n661: or %0, %3, %0\n"
356 " nop\n"
357 "\n662: nop\n"
358 " nop\n"
359 " .section .sun4v_2insn_patch, \"ax\"\n"
360 " .word 661b\n"
361 " sethi %%uhi(%4), %1\n"
362 " sllx %1, 32, %1\n"
363 " .word 662b\n"
364 " or %1, %%lo(%4), %1\n"
365 " or %0, %1, %0\n"
366 " .previous\n"
367 : "=r" (val), "=r" (tmp)
368 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
369 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
370
371 return __pte(val);
372}
373
374static inline pte_t pte_mkclean(pte_t pte)
375{
376 unsigned long val = pte_val(pte), tmp;
377
378 __asm__ __volatile__(
379 "\n661: andn %0, %3, %0\n"
380 " nop\n"
381 "\n662: nop\n"
382 " nop\n"
383 " .section .sun4v_2insn_patch, \"ax\"\n"
384 " .word 661b\n"
385 " sethi %%uhi(%4), %1\n"
386 " sllx %1, 32, %1\n"
387 " .word 662b\n"
388 " or %1, %%lo(%4), %1\n"
389 " andn %0, %1, %0\n"
390 " .previous\n"
391 : "=r" (val), "=r" (tmp)
392 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
393 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
394
395 return __pte(val);
396}
397
398static inline pte_t pte_mkwrite(pte_t pte)
399{
400 unsigned long val = pte_val(pte), mask;
401
402 __asm__ __volatile__(
403 "\n661: mov %1, %0\n"
404 " nop\n"
405 " .section .sun4v_2insn_patch, \"ax\"\n"
406 " .word 661b\n"
407 " sethi %%uhi(%2), %0\n"
408 " sllx %0, 32, %0\n"
409 " .previous\n"
410 : "=r" (mask)
411 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
412
413 return __pte(val | mask);
414}
415
416static inline pte_t pte_wrprotect(pte_t pte)
417{
418 unsigned long val = pte_val(pte), tmp;
419
420 __asm__ __volatile__(
421 "\n661: andn %0, %3, %0\n"
422 " nop\n"
423 "\n662: nop\n"
424 " nop\n"
425 " .section .sun4v_2insn_patch, \"ax\"\n"
426 " .word 661b\n"
427 " sethi %%uhi(%4), %1\n"
428 " sllx %1, 32, %1\n"
429 " .word 662b\n"
430 " or %1, %%lo(%4), %1\n"
431 " andn %0, %1, %0\n"
432 " .previous\n"
433 : "=r" (val), "=r" (tmp)
434 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
435 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
436
437 return __pte(val);
438}
439
440static inline pte_t pte_mkold(pte_t pte)
441{
442 unsigned long mask;
443
444 __asm__ __volatile__(
445 "\n661: mov %1, %0\n"
446 " nop\n"
447 " .section .sun4v_2insn_patch, \"ax\"\n"
448 " .word 661b\n"
449 " sethi %%uhi(%2), %0\n"
450 " sllx %0, 32, %0\n"
451 " .previous\n"
452 : "=r" (mask)
453 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
454
455 mask |= _PAGE_R;
456
457 return __pte(pte_val(pte) & ~mask);
458}
459
460static inline pte_t pte_mkyoung(pte_t pte)
461{
462 unsigned long mask;
463
464 __asm__ __volatile__(
465 "\n661: mov %1, %0\n"
466 " nop\n"
467 " .section .sun4v_2insn_patch, \"ax\"\n"
468 " .word 661b\n"
469 " sethi %%uhi(%2), %0\n"
470 " sllx %0, 32, %0\n"
471 " .previous\n"
472 : "=r" (mask)
473 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
474
475 mask |= _PAGE_R;
476
477 return __pte(pte_val(pte) | mask);
478}
479
480static inline pte_t pte_mkspecial(pte_t pte)
481{
David S. Miller683d2fa2011-07-25 17:12:21 -0700482 pte_val(pte) |= _PAGE_SPECIAL;
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700483 return pte;
484}
485
486static inline unsigned long pte_young(pte_t pte)
487{
488 unsigned long mask;
489
490 __asm__ __volatile__(
491 "\n661: mov %1, %0\n"
492 " nop\n"
493 " .section .sun4v_2insn_patch, \"ax\"\n"
494 " .word 661b\n"
495 " sethi %%uhi(%2), %0\n"
496 " sllx %0, 32, %0\n"
497 " .previous\n"
498 : "=r" (mask)
499 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
500
501 return (pte_val(pte) & mask);
502}
503
504static inline unsigned long pte_dirty(pte_t pte)
505{
506 unsigned long mask;
507
508 __asm__ __volatile__(
509 "\n661: mov %1, %0\n"
510 " nop\n"
511 " .section .sun4v_2insn_patch, \"ax\"\n"
512 " .word 661b\n"
513 " sethi %%uhi(%2), %0\n"
514 " sllx %0, 32, %0\n"
515 " .previous\n"
516 : "=r" (mask)
517 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
518
519 return (pte_val(pte) & mask);
520}
521
522static inline unsigned long pte_write(pte_t pte)
523{
524 unsigned long mask;
525
526 __asm__ __volatile__(
527 "\n661: mov %1, %0\n"
528 " nop\n"
529 " .section .sun4v_2insn_patch, \"ax\"\n"
530 " .word 661b\n"
531 " sethi %%uhi(%2), %0\n"
532 " sllx %0, 32, %0\n"
533 " .previous\n"
534 : "=r" (mask)
535 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
536
537 return (pte_val(pte) & mask);
538}
539
540static inline unsigned long pte_exec(pte_t pte)
541{
542 unsigned long mask;
543
544 __asm__ __volatile__(
545 "\n661: sethi %%hi(%1), %0\n"
546 " .section .sun4v_1insn_patch, \"ax\"\n"
547 " .word 661b\n"
548 " mov %2, %0\n"
549 " .previous\n"
550 : "=r" (mask)
551 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
552
553 return (pte_val(pte) & mask);
554}
555
556static inline unsigned long pte_file(pte_t pte)
557{
558 unsigned long val = pte_val(pte);
559
560 __asm__ __volatile__(
561 "\n661: and %0, %2, %0\n"
562 " .section .sun4v_1insn_patch, \"ax\"\n"
563 " .word 661b\n"
564 " and %0, %3, %0\n"
565 " .previous\n"
566 : "=r" (val)
567 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
568
569 return val;
570}
571
572static inline unsigned long pte_present(pte_t pte)
573{
574 unsigned long val = pte_val(pte);
575
576 __asm__ __volatile__(
577 "\n661: and %0, %2, %0\n"
578 " .section .sun4v_1insn_patch, \"ax\"\n"
579 " .word 661b\n"
580 " and %0, %3, %0\n"
581 " .previous\n"
582 : "=r" (val)
583 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
584
585 return val;
586}
587
David S. Miller683d2fa2011-07-25 17:12:21 -0700588static inline unsigned long pte_special(pte_t pte)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700589{
David S. Miller683d2fa2011-07-25 17:12:21 -0700590 return pte_val(pte) & _PAGE_SPECIAL;
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700591}
592
593#define pmd_set(pmdp, ptep) \
594 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
595#define pud_set(pudp, pmdp) \
596 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
597#define __pmd_page(pmd) \
598 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
599#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
600#define pud_page_vaddr(pud) \
601 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
602#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
603#define pmd_none(pmd) (!pmd_val(pmd))
604#define pmd_bad(pmd) (0)
605#define pmd_present(pmd) (pmd_val(pmd) != 0U)
606#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
607#define pud_none(pud) (!pud_val(pud))
608#define pud_bad(pud) (0)
609#define pud_present(pud) (pud_val(pud) != 0U)
610#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
611
612/* Same in both SUN4V and SUN4U. */
613#define pte_none(pte) (!pte_val(pte))
614
615/* to find an entry in a page-table-directory. */
616#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
617#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
618
619/* to find an entry in a kernel page-table-directory */
620#define pgd_offset_k(address) pgd_offset(&init_mm, address)
621
622/* Find an entry in the second-level page table.. */
623#define pmd_offset(pudp, address) \
624 ((pmd_t *) pud_page_vaddr(*(pudp)) + \
625 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
626
627/* Find an entry in the third-level page table.. */
628#define pte_index(dir, address) \
629 ((pte_t *) __pmd_page(*(dir)) + \
630 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
631#define pte_offset_kernel pte_index
632#define pte_offset_map pte_index
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700633#define pte_unmap(pte) do { } while (0)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700634
635/* Actual page table PTE updates. */
Peter Zijlstra90f08e32011-05-24 17:11:50 -0700636extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
637 pte_t *ptep, pte_t orig, int fullmm);
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700638
Peter Zijlstra90f08e32011-05-24 17:11:50 -0700639static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
640 pte_t *ptep, pte_t pte, int fullmm)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700641{
642 pte_t orig = *ptep;
643
644 *ptep = pte;
645
646 /* It is more efficient to let flush_tlb_kernel_range()
647 * handle init_mm tlb flushes.
648 *
649 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
650 * and SUN4V pte layout, so this inline test is fine.
651 */
652 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
Peter Zijlstra90f08e32011-05-24 17:11:50 -0700653 tlb_batch_add(mm, addr, ptep, orig, fullmm);
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700654}
655
Peter Zijlstra90f08e32011-05-24 17:11:50 -0700656#define set_pte_at(mm,addr,ptep,pte) \
657 __set_pte_at((mm), (addr), (ptep), (pte), 0)
658
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700659#define pte_clear(mm,addr,ptep) \
660 set_pte_at((mm), (addr), (ptep), __pte(0UL))
661
Peter Zijlstra90f08e32011-05-24 17:11:50 -0700662#define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
663#define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
664 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
665
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700666#ifdef DCACHE_ALIASING_POSSIBLE
667#define __HAVE_ARCH_MOVE_PTE
668#define move_pte(pte, prot, old_addr, new_addr) \
669({ \
670 pte_t newpte = (pte); \
671 if (tlb_type != hypervisor && pte_present(pte)) { \
672 unsigned long this_pfn = pte_pfn(pte); \
673 \
674 if (pfn_valid(this_pfn) && \
675 (((old_addr) ^ (new_addr)) & (1 << 13))) \
676 flush_dcache_page_all(current->mm, \
677 pfn_to_page(this_pfn)); \
678 } \
679 newpte; \
680})
681#endif
682
683extern pgd_t swapper_pg_dir[2048];
684extern pmd_t swapper_low_pmd_dir[2048];
685
686extern void paging_init(void);
687extern unsigned long find_ecache_flush_span(unsigned long size);
688
Sam Ravnborgcb1b8202011-04-21 15:45:45 -0700689struct seq_file;
690extern void mmu_info(struct seq_file *);
691
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700692struct vm_area_struct;
Russell King4b3073e2009-12-18 16:40:18 +0000693extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700694
695/* Encode and de-code a swap entry */
696#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
697#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
698#define __swp_entry(type, offset) \
699 ( (swp_entry_t) \
700 { \
701 (((long)(type) << PAGE_SHIFT) | \
702 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
703 } )
704#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
705#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
706
707/* File offset in PTE support. */
708extern unsigned long pte_file(pte_t);
709#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
710extern pte_t pgoff_to_pte(unsigned long);
711#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
712
David S. Millerd8ed1d42009-08-25 16:47:46 -0700713extern unsigned long sparc64_valid_addr_bitmap[];
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700714
715/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
David S. Millerd8ed1d42009-08-25 16:47:46 -0700716static inline bool kern_addr_valid(unsigned long addr)
717{
718 unsigned long paddr = __pa(addr);
719
720 if ((paddr >> 41UL) != 0UL)
721 return false;
722 return test_bit(paddr >> 22, sparc64_valid_addr_bitmap);
723}
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700724
725extern int page_in_phys_avail(unsigned long paddr);
726
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700727/*
728 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
729 * its high 4 bits. These macros/functions put it there or get it from there.
730 */
731#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
732#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
733#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
734
David S. Miller3e37fd32011-11-17 18:17:59 -0800735extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
736 unsigned long, pgprot_t);
737
738static inline int io_remap_pfn_range(struct vm_area_struct *vma,
739 unsigned long from, unsigned long pfn,
740 unsigned long size, pgprot_t prot)
741{
742 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
743 int space = GET_IOSPACE(pfn);
744 unsigned long phys_base;
745
746 phys_base = offset | (((unsigned long) space) << 32UL);
747
748 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
749}
750
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700751#include <asm-generic/pgtable.h>
752
753/* We provide our own get_unmapped_area to cope with VA holes and
754 * SHM area cache aliasing for userland.
755 */
756#define HAVE_ARCH_UNMAPPED_AREA
757#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
758
759/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
760 * the largest alignment possible such that larget PTEs can be used.
761 */
762extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
763 unsigned long, unsigned long,
764 unsigned long);
765#define HAVE_ARCH_FB_UNMAPPED_AREA
766
767extern void pgtable_cache_init(void);
768extern void sun4v_register_fault_status(void);
769extern void sun4v_ktsb_register(void);
770extern void __init cheetah_ecache_flush_init(void);
771extern void sun4v_patch_tlb_handlers(void);
772
773extern unsigned long cmdline_memory_size;
774
David S. Millerb539c462008-09-12 00:10:32 -0700775extern asmlinkage void do_sparc64_fault(struct pt_regs *regs);
776
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700777#endif /* !(__ASSEMBLY__) */
778
779#endif /* !(_SPARC64_PGTABLE_H) */