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Murali Karicheri0c4ffcf2014-09-02 17:26:19 -06001/*
2 * PCIe host controller driver for Texas Instruments Keystone SoCs
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 * Implementation based on pci-exynos.c and pcie-designware.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/irqchip/chained_irq.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/irqdomain.h>
19#include <linux/module.h>
20#include <linux/msi.h>
21#include <linux/of_irq.h>
22#include <linux/of.h>
23#include <linux/of_pci.h>
24#include <linux/platform_device.h>
25#include <linux/phy/phy.h>
26#include <linux/resource.h>
27#include <linux/signal.h>
28
29#include "pcie-designware.h"
30#include "pci-keystone.h"
31
32#define DRIVER_NAME "keystone-pcie"
33
34/* driver specific constants */
35#define MAX_MSI_HOST_IRQS 8
36#define MAX_LEGACY_HOST_IRQS 4
37
38/* RC mode settings masks */
39#define PCIE_RC_MODE BIT(2)
40#define PCIE_MODE_MASK (BIT(1) | BIT(2))
41
42/* DEV_STAT_CTRL */
43#define PCIE_CAP_BASE 0x70
44
45#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
46
47static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
48{
49 struct pcie_port *pp = &ks_pcie->pp;
50 int count = 200;
51
52 dw_pcie_setup_rc(pp);
53
54 if (dw_pcie_link_up(pp)) {
55 dev_err(pp->dev, "Link already up\n");
56 return 0;
57 }
58
59 ks_dw_pcie_initiate_link_train(ks_pcie);
60 /* check if the link is up or not */
61 while (!dw_pcie_link_up(pp)) {
62 usleep_range(100, 1000);
63 if (--count) {
64 ks_dw_pcie_initiate_link_train(ks_pcie);
65 continue;
66 }
67 dev_err(pp->dev, "phy link never came up\n");
68 return -EINVAL;
69 }
70
71 return 0;
72}
73
74static void ks_pcie_msi_irq_handler(unsigned int irq, struct irq_desc *desc)
75{
76 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
77 u32 offset = irq - ks_pcie->msi_host_irqs[0];
78 struct pcie_port *pp = &ks_pcie->pp;
79 struct irq_chip *chip = irq_desc_get_chip(desc);
80
81 dev_dbg(pp->dev, "ks_pci_msi_irq_handler, irq %d\n", irq);
82
83 /*
84 * The chained irq handler installation would have replaced normal
85 * interrupt driver handler so we need to take care of mask/unmask and
86 * ack operation.
87 */
88 chained_irq_enter(chip, desc);
89 ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
90 chained_irq_exit(chip, desc);
91}
92
93/**
94 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
95 * @irq: IRQ line for legacy interrupts
96 * @desc: Pointer to irq descriptor
97 *
98 * Traverse through pending legacy interrupts and invoke handler for each. Also
99 * takes care of interrupt controller level mask/ack operation.
100 */
101static void ks_pcie_legacy_irq_handler(unsigned int irq, struct irq_desc *desc)
102{
103 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
104 struct pcie_port *pp = &ks_pcie->pp;
105 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
106 struct irq_chip *chip = irq_desc_get_chip(desc);
107
108 dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
109
110 /*
111 * The chained irq handler installation would have replaced normal
112 * interrupt driver handler so we need to take care of mask/unmask and
113 * ack operation.
114 */
115 chained_irq_enter(chip, desc);
116 ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
117 chained_irq_exit(chip, desc);
118}
119
120static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
121 char *controller, int *num_irqs)
122{
123 int temp, max_host_irqs, legacy = 1, *host_irqs, ret = -EINVAL;
124 struct device *dev = ks_pcie->pp.dev;
125 struct device_node *np_pcie = dev->of_node, **np_temp;
126
127 if (!strcmp(controller, "msi-interrupt-controller"))
128 legacy = 0;
129
130 if (legacy) {
131 np_temp = &ks_pcie->legacy_intc_np;
132 max_host_irqs = MAX_LEGACY_HOST_IRQS;
133 host_irqs = &ks_pcie->legacy_host_irqs[0];
134 } else {
135 np_temp = &ks_pcie->msi_intc_np;
136 max_host_irqs = MAX_MSI_HOST_IRQS;
137 host_irqs = &ks_pcie->msi_host_irqs[0];
138 }
139
140 /* interrupt controller is in a child node */
141 *np_temp = of_find_node_by_name(np_pcie, controller);
142 if (!(*np_temp)) {
143 dev_err(dev, "Node for %s is absent\n", controller);
144 goto out;
145 }
146 temp = of_irq_count(*np_temp);
147 if (!temp)
148 goto out;
149 if (temp > max_host_irqs)
150 dev_warn(dev, "Too many %s interrupts defined %u\n",
151 (legacy ? "legacy" : "MSI"), temp);
152
153 /*
154 * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
155 * 7 (MSI)
156 */
157 for (temp = 0; temp < max_host_irqs; temp++) {
158 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
159 if (host_irqs[temp] < 0)
160 break;
161 }
162 if (temp) {
163 *num_irqs = temp;
164 ret = 0;
165 }
166out:
167 return ret;
168}
169
170static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
171{
172 int i;
173
174 /* Legacy IRQ */
175 for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
176 irq_set_handler_data(ks_pcie->legacy_host_irqs[i], ks_pcie);
177 irq_set_chained_handler(ks_pcie->legacy_host_irqs[i],
178 ks_pcie_legacy_irq_handler);
179 }
180 ks_dw_pcie_enable_legacy_irqs(ks_pcie);
181
182 /* MSI IRQ */
183 if (IS_ENABLED(CONFIG_PCI_MSI)) {
184 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
185 irq_set_chained_handler(ks_pcie->msi_host_irqs[i],
186 ks_pcie_msi_irq_handler);
187 irq_set_handler_data(ks_pcie->msi_host_irqs[i],
188 ks_pcie);
189 }
190 }
191}
192
193/*
194 * When a PCI device does not exist during config cycles, keystone host gets a
195 * bus error instead of returning 0xffffffff. This handler always returns 0
196 * for this kind of faults.
197 */
198static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
199 struct pt_regs *regs)
200{
201 unsigned long instr = *(unsigned long *) instruction_pointer(regs);
202
203 if ((instr & 0x0e100090) == 0x00100090) {
204 int reg = (instr >> 12) & 15;
205
206 regs->uregs[reg] = -1;
207 regs->ARM_pc += 4;
208 }
209
210 return 0;
211}
212
213static void __init ks_pcie_host_init(struct pcie_port *pp)
214{
215 u32 vendor_device_id, val;
216 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
217
218 ks_pcie_establish_link(ks_pcie);
219 ks_dw_pcie_setup_rc_app_regs(ks_pcie);
220 ks_pcie_setup_interrupts(ks_pcie);
221 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
222 pp->dbi_base + PCI_IO_BASE);
223
224 /* update the Vendor ID */
225 vendor_device_id = readl(ks_pcie->va_reg_pciid);
226 writew((vendor_device_id >> 16), pp->dbi_base + PCI_DEVICE_ID);
227
228 /* update the DEV_STAT_CTRL to publish right mrrs */
229 val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
230 val &= ~PCI_EXP_DEVCTL_READRQ;
231 /* set the mrrs to 256 bytes */
232 val |= BIT(12);
233 writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
234
235 /*
236 * PCIe access errors that result into OCP errors are caught by ARM as
237 * "External aborts"
238 */
239 hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
240 "Asynchronous external abort");
241}
242
243static struct pcie_host_ops keystone_pcie_host_ops = {
244 .rd_other_conf = ks_dw_pcie_rd_other_conf,
245 .wr_other_conf = ks_dw_pcie_wr_other_conf,
246 .link_up = ks_dw_pcie_link_up,
247 .host_init = ks_pcie_host_init,
248 .msi_set_irq = ks_dw_pcie_msi_set_irq,
249 .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
250 .get_msi_data = ks_dw_pcie_get_msi_data,
251 .msi_host_init = ks_dw_pcie_msi_host_init,
252 .scan_bus = ks_dw_pcie_v3_65_scan_bus,
253};
254
255static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
256 struct platform_device *pdev)
257{
258 struct pcie_port *pp = &ks_pcie->pp;
259 int ret;
260
261 ret = ks_pcie_get_irq_controller_info(ks_pcie,
262 "legacy-interrupt-controller",
263 &ks_pcie->num_legacy_host_irqs);
264 if (ret)
265 return ret;
266
267 if (IS_ENABLED(CONFIG_PCI_MSI)) {
268 ret = ks_pcie_get_irq_controller_info(ks_pcie,
269 "msi-interrupt-controller",
270 &ks_pcie->num_msi_host_irqs);
271 if (ret)
272 return ret;
273 }
274
275 pp->root_bus_nr = -1;
276 pp->ops = &keystone_pcie_host_ops;
277 ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
278 if (ret) {
279 dev_err(&pdev->dev, "failed to initialize host\n");
280 return ret;
281 }
282
283 return ret;
284}
285
286static const struct of_device_id ks_pcie_of_match[] = {
287 {
288 .type = "pci",
289 .compatible = "ti,keystone-pcie",
290 },
291 { },
292};
293MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
294
295static int __exit ks_pcie_remove(struct platform_device *pdev)
296{
297 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
298
299 clk_disable_unprepare(ks_pcie->clk);
300
301 return 0;
302}
303
304static int __init ks_pcie_probe(struct platform_device *pdev)
305{
306 struct device *dev = &pdev->dev;
307 struct keystone_pcie *ks_pcie;
308 struct pcie_port *pp;
309 struct resource *res;
310 void __iomem *reg_p;
311 struct phy *phy;
312 int ret = 0;
313 u32 val;
314
315 ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
316 GFP_KERNEL);
317 if (!ks_pcie) {
318 dev_err(dev, "no memory for keystone pcie\n");
319 return -ENOMEM;
320 }
321 pp = &ks_pcie->pp;
322
323 /* index 2 is the devcfg register for RC mode settings */
324 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
325 reg_p = devm_ioremap_resource(dev, res);
326 if (IS_ERR(reg_p))
327 return PTR_ERR(reg_p);
328
329 /* enable RC mode in devcfg */
330 val = readl(reg_p);
331 val &= ~PCIE_MODE_MASK;
332 val |= PCIE_RC_MODE;
333 writel(val, reg_p);
334
335 /* initialize SerDes Phy if present */
336 phy = devm_phy_get(dev, "pcie-phy");
337 if (!IS_ERR_OR_NULL(phy)) {
338 ret = phy_init(phy);
339 if (ret < 0)
340 return ret;
341 }
342
343 /* index 3 is to read PCI DEVICE_ID */
344 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
345 reg_p = devm_ioremap_resource(dev, res);
346 if (IS_ERR(reg_p))
347 return PTR_ERR(reg_p);
348 ks_pcie->va_reg_pciid = reg_p;
349
350 pp->dev = dev;
351 platform_set_drvdata(pdev, ks_pcie);
352 ks_pcie->clk = devm_clk_get(dev, "pcie");
353 if (IS_ERR(ks_pcie->clk)) {
354 dev_err(dev, "Failed to get pcie rc clock\n");
355 return PTR_ERR(ks_pcie->clk);
356 }
357 ret = clk_prepare_enable(ks_pcie->clk);
358 if (ret)
359 return ret;
360
361 ret = ks_add_pcie_port(ks_pcie, pdev);
362 if (ret < 0)
363 goto fail_clk;
364
365 return 0;
366fail_clk:
367 clk_disable_unprepare(ks_pcie->clk);
368
369 return ret;
370}
371
372static struct platform_driver ks_pcie_driver __refdata = {
373 .probe = ks_pcie_probe,
374 .remove = __exit_p(ks_pcie_remove),
375 .driver = {
376 .name = "keystone-pcie",
377 .owner = THIS_MODULE,
378 .of_match_table = of_match_ptr(ks_pcie_of_match),
379 },
380};
381
382module_platform_driver(ks_pcie_driver);
383
384MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
385MODULE_DESCRIPTION("Keystone PCIe host controller driver");
386MODULE_LICENSE("GPL v2");