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Lorenzo Pieralisie53b9232012-07-13 15:55:52 +01001/*
2 * CCI cache coherent interconnect driver
3 *
4 * Copyright (C) 2013 ARM Ltd.
5 * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/arm-cci.h>
18#include <linux/io.h>
19#include <linux/module.h>
Jon Medhurst0b9bd1c2013-05-10 14:47:27 +010020#include <linux/platform_device.h>
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +010021#include <linux/of_address.h>
22#include <linux/slab.h>
23
24#include <asm/cacheflush.h>
25#include <asm/smp_plat.h>
26
Jon Medhurst0b9bd1c2013-05-10 14:47:27 +010027#define DRIVER_NAME "CCI"
28
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +010029#define CCI_PORT_CTRL 0x0
30#define CCI_CTRL_STATUS 0xc
31
32#define CCI_ENABLE_SNOOP_REQ 0x1
33#define CCI_ENABLE_DVM_REQ 0x2
34#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
35
36struct cci_nb_ports {
37 unsigned int nb_ace;
38 unsigned int nb_ace_lite;
39};
40
41enum cci_ace_port_type {
42 ACE_INVALID_PORT = 0x0,
43 ACE_PORT,
44 ACE_LITE_PORT,
45};
46
47struct cci_ace_port {
48 void __iomem *base;
Nicolas Pitreab28e082013-05-21 23:34:41 -040049 unsigned long phys;
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +010050 enum cci_ace_port_type type;
51 struct device_node *dn;
52};
53
54static struct cci_ace_port *ports;
55static unsigned int nb_cci_ports;
56
57static void __iomem *cci_ctrl_base;
Nicolas Pitreab28e082013-05-21 23:34:41 -040058static unsigned long cci_ctrl_phys;
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +010059
Jon Medhurst0b9bd1c2013-05-10 14:47:27 +010060#ifdef CONFIG_HW_PERF_EVENTS
61
62static void __iomem *cci_pmu_base;
63
64static int cci_pmu_probe(struct platform_device *pdev)
65{
66 struct resource *res;
67
68 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
69 cci_pmu_base = devm_ioremap_resource(&pdev->dev, res);
70 if (IS_ERR(cci_pmu_base))
71 return PTR_ERR(cci_pmu_base);
72
73 return 0;
74}
75
76static const struct of_device_id arm_cci_pmu_matches[] = {
77 {.compatible = "arm,cci-400-pmu"},
78 {},
79};
80
81static struct platform_driver cci_pmu_platform_driver = {
82 .driver = {
83 .name = DRIVER_NAME,
84 .of_match_table = arm_cci_pmu_matches,
85 },
86 .probe = cci_pmu_probe,
87};
88
89static int __init cci_pmu_init(void)
90{
91 if (platform_driver_register(&cci_pmu_platform_driver))
92 WARN(1, "unable to register CCI platform driver\n");
93 return 0;
94}
95
96#else
97
98static int __init cci_pmu_init(void)
99{
100 return 0;
101}
102
103static void cci_pmu_destroy(void) { }
104
105#endif /* CONFIG_HW_PERF_EVENTS */
106
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100107struct cpu_port {
108 u64 mpidr;
109 u32 port;
110};
Nicolas Pitreab28e082013-05-21 23:34:41 -0400111
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100112/*
113 * Use the port MSB as valid flag, shift can be made dynamic
114 * by computing number of bits required for port indexes.
115 * Code disabling CCI cpu ports runs with D-cache invalidated
116 * and SCTLR bit clear so data accesses must be kept to a minimum
117 * to improve performance; for now shift is left static to
118 * avoid one more data access while disabling the CCI port.
119 */
120#define PORT_VALID_SHIFT 31
121#define PORT_VALID (0x1 << PORT_VALID_SHIFT)
122
123static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
124{
125 port->port = PORT_VALID | index;
126 port->mpidr = mpidr;
127}
128
129static inline bool cpu_port_is_valid(struct cpu_port *port)
130{
131 return !!(port->port & PORT_VALID);
132}
133
134static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
135{
136 return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
137}
138
139static struct cpu_port cpu_port[NR_CPUS];
140
141/**
142 * __cci_ace_get_port - Function to retrieve the port index connected to
143 * a cpu or device.
144 *
145 * @dn: device node of the device to look-up
146 * @type: port type
147 *
148 * Return value:
149 * - CCI port index if success
150 * - -ENODEV if failure
151 */
152static int __cci_ace_get_port(struct device_node *dn, int type)
153{
154 int i;
155 bool ace_match;
156 struct device_node *cci_portn;
157
158 cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
159 for (i = 0; i < nb_cci_ports; i++) {
160 ace_match = ports[i].type == type;
161 if (ace_match && cci_portn == ports[i].dn)
162 return i;
163 }
164 return -ENODEV;
165}
166
167int cci_ace_get_port(struct device_node *dn)
168{
169 return __cci_ace_get_port(dn, ACE_LITE_PORT);
170}
171EXPORT_SYMBOL_GPL(cci_ace_get_port);
172
173static void __init cci_ace_init_ports(void)
174{
175 int port, ac, cpu;
176 u64 hwid;
177 const u32 *cell;
178 struct device_node *cpun, *cpus;
179
180 cpus = of_find_node_by_path("/cpus");
181 if (WARN(!cpus, "Missing cpus node, bailing out\n"))
182 return;
183
184 if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
185 ac = of_n_addr_cells(cpus);
186
187 /*
188 * Port index look-up speeds up the function disabling ports by CPU,
189 * since the logical to port index mapping is done once and does
190 * not change after system boot.
191 * The stashed index array is initialized for all possible CPUs
192 * at probe time.
193 */
194 for_each_child_of_node(cpus, cpun) {
195 if (of_node_cmp(cpun->type, "cpu"))
196 continue;
197 cell = of_get_property(cpun, "reg", NULL);
198 if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
199 continue;
200
201 hwid = of_read_number(cell, ac);
202 cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
203
204 if (cpu < 0 || !cpu_possible(cpu))
205 continue;
206 port = __cci_ace_get_port(cpun, ACE_PORT);
207 if (port < 0)
208 continue;
209
210 init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
211 }
212
213 for_each_possible_cpu(cpu) {
214 WARN(!cpu_port_is_valid(&cpu_port[cpu]),
215 "CPU %u does not have an associated CCI port\n",
216 cpu);
217 }
218}
219/*
220 * Functions to enable/disable a CCI interconnect slave port
221 *
222 * They are called by low-level power management code to disable slave
223 * interfaces snoops and DVM broadcast.
224 * Since they may execute with cache data allocation disabled and
225 * after the caches have been cleaned and invalidated the functions provide
226 * no explicit locking since they may run with D-cache disabled, so normal
227 * cacheable kernel locks based on ldrex/strex may not work.
228 * Locking has to be provided by BSP implementations to ensure proper
229 * operations.
230 */
231
232/**
233 * cci_port_control() - function to control a CCI port
234 *
235 * @port: index of the port to setup
236 * @enable: if true enables the port, if false disables it
237 */
238static void notrace cci_port_control(unsigned int port, bool enable)
239{
240 void __iomem *base = ports[port].base;
241
242 writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
243 /*
244 * This function is called from power down procedures
245 * and must not execute any instruction that might
246 * cause the processor to be put in a quiescent state
247 * (eg wfi). Hence, cpu_relax() can not be added to this
248 * read loop to optimize power, since it might hide possibly
249 * disruptive operations.
250 */
251 while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
252 ;
253}
254
255/**
256 * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
257 * reference
258 *
259 * @mpidr: mpidr of the CPU whose CCI port should be disabled
260 *
261 * Disabling a CCI port for a CPU implies disabling the CCI port
262 * controlling that CPU cluster. Code disabling CPU CCI ports
263 * must make sure that the CPU running the code is the last active CPU
264 * in the cluster ie all other CPUs are quiescent in a low power state.
265 *
266 * Return:
267 * 0 on success
268 * -ENODEV on port look-up failure
269 */
270int notrace cci_disable_port_by_cpu(u64 mpidr)
271{
272 int cpu;
273 bool is_valid;
274 for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
275 is_valid = cpu_port_is_valid(&cpu_port[cpu]);
276 if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
277 cci_port_control(cpu_port[cpu].port, false);
278 return 0;
279 }
280 }
281 return -ENODEV;
282}
283EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
284
285/**
Nicolas Pitreab28e082013-05-21 23:34:41 -0400286 * cci_enable_port_for_self() - enable a CCI port for calling CPU
287 *
288 * Enabling a CCI port for the calling CPU implies enabling the CCI
289 * port controlling that CPU's cluster. Caller must make sure that the
290 * CPU running the code is the first active CPU in the cluster and all
291 * other CPUs are quiescent in a low power state or waiting for this CPU
292 * to complete the CCI initialization.
293 *
294 * Because this is called when the MMU is still off and with no stack,
295 * the code must be position independent and ideally rely on callee
296 * clobbered registers only. To achieve this we must code this function
297 * entirely in assembler.
298 *
299 * On success this returns with the proper CCI port enabled. In case of
300 * any failure this never returns as the inability to enable the CCI is
301 * fatal and there is no possible recovery at this stage.
302 */
303asmlinkage void __naked cci_enable_port_for_self(void)
304{
305 asm volatile ("\n"
306
307" mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n"
308" and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
309" adr r1, 5f \n"
310" ldr r2, [r1] \n"
311" add r1, r1, r2 @ &cpu_port \n"
312" add ip, r1, %[sizeof_cpu_port] \n"
313
314 /* Loop over the cpu_port array looking for a matching MPIDR */
315"1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
316" cmp r2, r0 @ compare MPIDR \n"
317" bne 2f \n"
318
319 /* Found a match, now test port validity */
320" ldr r3, [r1, %[offsetof_cpu_port_port]] \n"
321" tst r3, #"__stringify(PORT_VALID)" \n"
322" bne 3f \n"
323
324 /* no match, loop with the next cpu_port entry */
325"2: add r1, r1, %[sizeof_struct_cpu_port] \n"
326" cmp r1, ip @ done? \n"
327" blo 1b \n"
328
329 /* CCI port not found -- cheaply try to stall this CPU */
330"cci_port_not_found: \n"
331" wfi \n"
332" wfe \n"
333" b cci_port_not_found \n"
334
335 /* Use matched port index to look up the corresponding ports entry */
336"3: bic r3, r3, #"__stringify(PORT_VALID)" \n"
337" adr r0, 6f \n"
338" ldmia r0, {r1, r2} \n"
339" sub r1, r1, r0 @ virt - phys \n"
340" ldr r0, [r0, r2] @ *(&ports) \n"
341" mov r2, %[sizeof_struct_ace_port] \n"
342" mla r0, r2, r3, r0 @ &ports[index] \n"
343" sub r0, r0, r1 @ virt_to_phys() \n"
344
345 /* Enable the CCI port */
346" ldr r0, [r0, %[offsetof_port_phys]] \n"
347" mov r3, #"__stringify(CCI_ENABLE_REQ)" \n"
348" str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
349
350 /* poll the status reg for completion */
351" adr r1, 7f \n"
352" ldr r0, [r1] \n"
353" ldr r0, [r0, r1] @ cci_ctrl_base \n"
354"4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
355" tst r1, #1 \n"
356" bne 4b \n"
357
358" mov r0, #0 \n"
359" bx lr \n"
360
361" .align 2 \n"
362"5: .word cpu_port - . \n"
363"6: .word . \n"
364" .word ports - 6b \n"
365"7: .word cci_ctrl_phys - . \n"
366 : :
367 [sizeof_cpu_port] "i" (sizeof(cpu_port)),
368#ifndef __ARMEB__
369 [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
370#else
371 [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
372#endif
373 [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
374 [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
375 [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
376 [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
377
378 unreachable();
379}
380
381/**
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100382 * __cci_control_port_by_device() - function to control a CCI port by device
383 * reference
384 *
385 * @dn: device node pointer of the device whose CCI port should be
386 * controlled
387 * @enable: if true enables the port, if false disables it
388 *
389 * Return:
390 * 0 on success
391 * -ENODEV on port look-up failure
392 */
393int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
394{
395 int port;
396
397 if (!dn)
398 return -ENODEV;
399
400 port = __cci_ace_get_port(dn, ACE_LITE_PORT);
401 if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
402 dn->full_name))
403 return -ENODEV;
404 cci_port_control(port, enable);
405 return 0;
406}
407EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
408
409/**
410 * __cci_control_port_by_index() - function to control a CCI port by port index
411 *
412 * @port: port index previously retrieved with cci_ace_get_port()
413 * @enable: if true enables the port, if false disables it
414 *
415 * Return:
416 * 0 on success
417 * -ENODEV on port index out of range
418 * -EPERM if operation carried out on an ACE PORT
419 */
420int notrace __cci_control_port_by_index(u32 port, bool enable)
421{
422 if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
423 return -ENODEV;
424 /*
425 * CCI control for ports connected to CPUS is extremely fragile
426 * and must be made to go through a specific and controlled
427 * interface (ie cci_disable_port_by_cpu(); control by general purpose
428 * indexing is therefore disabled for ACE ports.
429 */
430 if (ports[port].type == ACE_PORT)
431 return -EPERM;
432
433 cci_port_control(port, enable);
434 return 0;
435}
436EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
437
438static const struct cci_nb_ports cci400_ports = {
439 .nb_ace = 2,
440 .nb_ace_lite = 3
441};
442
443static const struct of_device_id arm_cci_matches[] = {
444 {.compatible = "arm,cci-400", .data = &cci400_ports },
445 {},
446};
447
448static const struct of_device_id arm_cci_ctrl_if_matches[] = {
449 {.compatible = "arm,cci-400-ctrl-if", },
450 {},
451};
452
453static int __init cci_probe(void)
454{
455 struct cci_nb_ports const *cci_config;
456 int ret, i, nb_ace = 0, nb_ace_lite = 0;
457 struct device_node *np, *cp;
Nicolas Pitreab28e082013-05-21 23:34:41 -0400458 struct resource res;
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100459 const char *match_str;
460 bool is_ace;
461
462 np = of_find_matching_node(NULL, arm_cci_matches);
463 if (!np)
464 return -ENODEV;
465
466 cci_config = of_match_node(arm_cci_matches, np)->data;
467 if (!cci_config)
468 return -ENODEV;
469
470 nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
471
472 ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
473 if (!ports)
474 return -ENOMEM;
475
Nicolas Pitreab28e082013-05-21 23:34:41 -0400476 ret = of_address_to_resource(np, 0, &res);
477 if (!ret) {
478 cci_ctrl_base = ioremap(res.start, resource_size(&res));
479 cci_ctrl_phys = res.start;
480 }
481 if (ret || !cci_ctrl_base) {
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100482 WARN(1, "unable to ioremap CCI ctrl\n");
483 ret = -ENXIO;
484 goto memalloc_err;
485 }
486
487 for_each_child_of_node(np, cp) {
488 if (!of_match_node(arm_cci_ctrl_if_matches, cp))
489 continue;
490
491 i = nb_ace + nb_ace_lite;
492
493 if (i >= nb_cci_ports)
494 break;
495
496 if (of_property_read_string(cp, "interface-type",
497 &match_str)) {
498 WARN(1, "node %s missing interface-type property\n",
499 cp->full_name);
500 continue;
501 }
502 is_ace = strcmp(match_str, "ace") == 0;
503 if (!is_ace && strcmp(match_str, "ace-lite")) {
504 WARN(1, "node %s containing invalid interface-type property, skipping it\n",
505 cp->full_name);
506 continue;
507 }
508
Nicolas Pitreab28e082013-05-21 23:34:41 -0400509 ret = of_address_to_resource(cp, 0, &res);
510 if (!ret) {
511 ports[i].base = ioremap(res.start, resource_size(&res));
512 ports[i].phys = res.start;
513 }
514 if (ret || !ports[i].base) {
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100515 WARN(1, "unable to ioremap CCI port %d\n", i);
516 continue;
517 }
518
519 if (is_ace) {
520 if (WARN_ON(nb_ace >= cci_config->nb_ace))
521 continue;
522 ports[i].type = ACE_PORT;
523 ++nb_ace;
524 } else {
525 if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
526 continue;
527 ports[i].type = ACE_LITE_PORT;
528 ++nb_ace_lite;
529 }
530 ports[i].dn = cp;
531 }
532
533 /* initialize a stashed array of ACE ports to speed-up look-up */
534 cci_ace_init_ports();
535
536 /*
537 * Multi-cluster systems may need this data when non-coherent, during
538 * cluster power-up/power-down. Make sure it reaches main memory.
539 */
540 sync_cache_w(&cci_ctrl_base);
Nicolas Pitreab28e082013-05-21 23:34:41 -0400541 sync_cache_w(&cci_ctrl_phys);
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100542 sync_cache_w(&ports);
543 sync_cache_w(&cpu_port);
544 __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
545 pr_info("ARM CCI driver probed\n");
546 return 0;
547
548memalloc_err:
549
550 kfree(ports);
551 return ret;
552}
553
554static int cci_init_status = -EAGAIN;
555static DEFINE_MUTEX(cci_probing);
556
557static int __init cci_init(void)
558{
559 if (cci_init_status != -EAGAIN)
560 return cci_init_status;
561
562 mutex_lock(&cci_probing);
563 if (cci_init_status == -EAGAIN)
564 cci_init_status = cci_probe();
565 mutex_unlock(&cci_probing);
566 return cci_init_status;
567}
568
569/*
570 * To sort out early init calls ordering a helper function is provided to
571 * check if the CCI driver has beed initialized. Function check if the driver
572 * has been initialized, if not it calls the init function that probes
573 * the driver and updates the return value.
574 */
575bool __init cci_probed(void)
576{
577 return cci_init() == 0;
578}
579EXPORT_SYMBOL_GPL(cci_probed);
580
581early_initcall(cci_init);
Jon Medhurst0b9bd1c2013-05-10 14:47:27 +0100582core_initcall(cci_pmu_init);
Lorenzo Pieralisie53b9232012-07-13 15:55:52 +0100583MODULE_LICENSE("GPL");
584MODULE_DESCRIPTION("ARM CCI support");