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Florian Fainelli7f646e92014-05-23 17:40:53 -07001/*
2 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/init.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
Kevin Cernekee05f12752014-11-06 22:44:20 -080022#include <linux/spinlock.h>
Florian Fainelli7f646e92014-05-23 17:40:53 -070023#include <linux/of.h>
24#include <linux/of_irq.h>
25#include <linux/of_address.h>
26#include <linux/of_platform.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/io.h>
30#include <linux/irqdomain.h>
31#include <linux/irqchip.h>
32#include <linux/irqchip/chained_irq.h>
33
Florian Fainelli7f646e92014-05-23 17:40:53 -070034#include "irqchip.h"
35
36/* Register offsets in the L2 interrupt controller */
37#define CPU_STATUS 0x00
38#define CPU_SET 0x04
39#define CPU_CLEAR 0x08
40#define CPU_MASK_STATUS 0x0c
41#define CPU_MASK_SET 0x10
42#define CPU_MASK_CLEAR 0x14
43
44/* L2 intc private data structure */
45struct brcmstb_l2_intc_data {
46 int parent_irq;
47 void __iomem *base;
48 struct irq_domain *domain;
49 bool can_wake;
50 u32 saved_mask; /* for suspend/resume */
51};
52
53static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
54{
55 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
56 struct irq_chip *chip = irq_desc_get_chip(desc);
57 u32 status;
58
59 chained_irq_enter(chip, desc);
60
61 status = __raw_readl(b->base + CPU_STATUS) &
62 ~(__raw_readl(b->base + CPU_MASK_STATUS));
63
64 if (status == 0) {
Kevin Cernekee05f12752014-11-06 22:44:20 -080065 raw_spin_lock(&desc->lock);
66 handle_bad_irq(irq, desc);
67 raw_spin_unlock(&desc->lock);
Florian Fainelli7f646e92014-05-23 17:40:53 -070068 goto out;
69 }
70
71 do {
72 irq = ffs(status) - 1;
73 /* ack at our level */
74 __raw_writel(1 << irq, b->base + CPU_CLEAR);
75 status &= ~(1 << irq);
76 generic_handle_irq(irq_find_mapping(b->domain, irq));
77 } while (status);
78out:
79 chained_irq_exit(chip, desc);
80}
81
82static void brcmstb_l2_intc_suspend(struct irq_data *d)
83{
84 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
85 struct brcmstb_l2_intc_data *b = gc->private;
86
87 irq_gc_lock(gc);
88 /* Save the current mask */
89 b->saved_mask = __raw_readl(b->base + CPU_MASK_STATUS);
90
91 if (b->can_wake) {
92 /* Program the wakeup mask */
93 __raw_writel(~gc->wake_active, b->base + CPU_MASK_SET);
94 __raw_writel(gc->wake_active, b->base + CPU_MASK_CLEAR);
95 }
96 irq_gc_unlock(gc);
97}
98
99static void brcmstb_l2_intc_resume(struct irq_data *d)
100{
101 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
102 struct brcmstb_l2_intc_data *b = gc->private;
103
104 irq_gc_lock(gc);
105 /* Clear unmasked non-wakeup interrupts */
106 __raw_writel(~b->saved_mask & ~gc->wake_active, b->base + CPU_CLEAR);
107
108 /* Restore the saved mask */
109 __raw_writel(b->saved_mask, b->base + CPU_MASK_SET);
110 __raw_writel(~b->saved_mask, b->base + CPU_MASK_CLEAR);
111 irq_gc_unlock(gc);
112}
113
114int __init brcmstb_l2_intc_of_init(struct device_node *np,
115 struct device_node *parent)
116{
117 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
118 struct brcmstb_l2_intc_data *data;
119 struct irq_chip_generic *gc;
120 struct irq_chip_type *ct;
121 int ret;
122
123 data = kzalloc(sizeof(*data), GFP_KERNEL);
124 if (!data)
125 return -ENOMEM;
126
127 data->base = of_iomap(np, 0);
128 if (!data->base) {
129 pr_err("failed to remap intc L2 registers\n");
130 ret = -ENOMEM;
131 goto out_free;
132 }
133
134 /* Disable all interrupts by default */
135 __raw_writel(0xffffffff, data->base + CPU_MASK_SET);
136 __raw_writel(0xffffffff, data->base + CPU_CLEAR);
137
138 data->parent_irq = irq_of_parse_and_map(np, 0);
139 if (data->parent_irq < 0) {
140 pr_err("failed to find parent interrupt\n");
141 ret = data->parent_irq;
142 goto out_unmap;
143 }
144
145 data->domain = irq_domain_add_linear(np, 32,
146 &irq_generic_chip_ops, NULL);
147 if (!data->domain) {
148 ret = -ENOMEM;
149 goto out_unmap;
150 }
151
152 /* Allocate a single Generic IRQ chip for this node */
153 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
Florian Fainelli00ac2022014-06-09 11:05:02 -0700154 np->full_name, handle_edge_irq, clr, 0, 0);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700155 if (ret) {
156 pr_err("failed to allocate generic irq chip\n");
157 goto out_free_domain;
158 }
159
160 /* Set the IRQ chaining logic */
161 irq_set_handler_data(data->parent_irq, data);
162 irq_set_chained_handler(data->parent_irq, brcmstb_l2_intc_irq_handle);
163
164 gc = irq_get_domain_generic_chip(data->domain, 0);
165 gc->reg_base = data->base;
166 gc->private = data;
167 ct = gc->chip_types;
168
169 ct->chip.irq_ack = irq_gc_ack_set_bit;
170 ct->regs.ack = CPU_CLEAR;
171
172 ct->chip.irq_mask = irq_gc_mask_disable_reg;
173 ct->regs.disable = CPU_MASK_SET;
174
175 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
176 ct->regs.enable = CPU_MASK_CLEAR;
177
178 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
179 ct->chip.irq_resume = brcmstb_l2_intc_resume;
180
181 if (of_property_read_bool(np, "brcm,irq-can-wake")) {
182 data->can_wake = true;
183 /* This IRQ chip can wake the system, set all child interrupts
184 * in wake_enabled mask
185 */
186 gc->wake_enabled = 0xffffffff;
187 ct->chip.irq_set_wake = irq_gc_set_wake;
188 }
189
190 pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n",
191 data->base, data->parent_irq);
192
193 return 0;
194
195out_free_domain:
196 irq_domain_remove(data->domain);
197out_unmap:
198 iounmap(data->base);
199out_free:
200 kfree(data);
201 return ret;
202}
203IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init);