blob: 9d833728ed005be06f5e8fc4464f0b56098bcc50 [file] [log] [blame]
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
Alex Deucher40e2a5c2010-06-04 18:41:42 -040028#include <linux/kernel.h>
David Howells760285e2012-10-02 18:01:07 +010029#include <drm/drmP.h>
Jerome Glisse3ce0a232009-09-08 10:10:24 +100030#include "radeon.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100031#include "r600d.h"
Jerome Glisse961fb592010-02-10 22:30:05 +000032#include "r600_reg_safe.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100033
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
Jerome Glisse961fb592010-02-10 22:30:05 +000040extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
Jerome Glisse3ce0a232009-09-08 10:10:24 +100042
Jerome Glissec8c15ff2010-01-18 13:01:36 +010043struct r600_cs_track {
Jerome Glisse961fb592010-02-10 22:30:05 +000044 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
Alex Deucher5f77df32010-03-26 14:52:32 -040049 u32 sq_config;
Marek Olšákc116cc92012-08-19 02:22:09 +020050 u32 log_nsamples;
Jerome Glisse961fb592010-02-10 22:30:05 +000051 u32 nsamples;
52 u32 cb_color_base_last[8];
53 struct radeon_bo *cb_color_bo[8];
Alex Deucher16790562010-11-14 20:24:35 -050054 u64 cb_color_bo_mc[8];
Marek Olšákc116cc92012-08-19 02:22:09 +020055 u64 cb_color_bo_offset[8];
56 struct radeon_bo *cb_color_frag_bo[8];
57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
Jerome Glisse961fb592010-02-10 22:30:05 +000061 u32 cb_color_info[8];
Jerome Glisse285484e2011-12-16 17:03:42 -050062 u32 cb_color_view[8];
Marek Olšák3c125132012-03-19 03:09:38 +010063 u32 cb_color_size_idx[8]; /* unused */
Jerome Glisse961fb592010-02-10 22:30:05 +000064 u32 cb_target_mask;
Marek Olšák3c125132012-03-19 03:09:38 +010065 u32 cb_shader_mask; /* unused */
Marek Olšák523885d2012-08-24 14:27:36 +020066 bool is_resolve;
Jerome Glisse961fb592010-02-10 22:30:05 +000067 u32 cb_color_size[8];
68 u32 vgt_strmout_en;
69 u32 vgt_strmout_buffer_en;
Marek Olšákdd220a02012-01-27 12:17:59 -050070 struct radeon_bo *vgt_strmout_bo[4];
Marek Olšák3c125132012-03-19 03:09:38 +010071 u64 vgt_strmout_bo_mc[4]; /* unused */
Marek Olšákdd220a02012-01-27 12:17:59 -050072 u32 vgt_strmout_bo_offset[4];
73 u32 vgt_strmout_size[4];
Jerome Glisse961fb592010-02-10 22:30:05 +000074 u32 db_depth_control;
75 u32 db_depth_info;
76 u32 db_depth_size_idx;
77 u32 db_depth_view;
78 u32 db_depth_size;
79 u32 db_offset;
80 struct radeon_bo *db_bo;
Alex Deucher16790562010-11-14 20:24:35 -050081 u64 db_bo_mc;
Marek Olšák779923b2012-03-08 00:56:00 +010082 bool sx_misc_kill_all_prims;
Marek Olšák3c125132012-03-19 03:09:38 +010083 bool cb_dirty;
84 bool db_dirty;
85 bool streamout_dirty;
Jerome Glisse88f50c82012-03-21 19:18:21 -040086 struct radeon_bo *htile_bo;
87 u64 htile_offset;
88 u32 htile_surface;
Jerome Glissec8c15ff2010-01-18 13:01:36 +010089};
90
Marek Olšákfe6f0bd2011-05-07 01:09:57 +020091#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
92#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
Jerome Glisse285484e2011-12-16 17:03:42 -050093#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
Marek Olšákfe6f0bd2011-05-07 01:09:57 +020094#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
Jerome Glisse285484e2011-12-16 17:03:42 -050095#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
Marek Olšákfe6f0bd2011-05-07 01:09:57 +020096#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
97#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
98#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
Dave Airlie60b212f2011-02-18 05:51:58 +000099
100struct gpu_formats {
101 unsigned blockwidth;
102 unsigned blockheight;
103 unsigned blocksize;
104 unsigned valid_color;
Marek Olšákfe6f0bd2011-05-07 01:09:57 +0200105 enum radeon_family min_family;
Dave Airlie60b212f2011-02-18 05:51:58 +0000106};
107
108static const struct gpu_formats color_formats_table[] = {
109 /* 8 bit */
110 FMT_8_BIT(V_038004_COLOR_8, 1),
111 FMT_8_BIT(V_038004_COLOR_4_4, 1),
112 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
113 FMT_8_BIT(V_038004_FMT_1, 0),
114
115 /* 16-bit */
116 FMT_16_BIT(V_038004_COLOR_16, 1),
117 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
118 FMT_16_BIT(V_038004_COLOR_8_8, 1),
119 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
120 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
121 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
122 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
123 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
124
125 /* 24-bit */
126 FMT_24_BIT(V_038004_FMT_8_8_8),
Jerome Glisse285484e2011-12-16 17:03:42 -0500127
Dave Airlie60b212f2011-02-18 05:51:58 +0000128 /* 32-bit */
129 FMT_32_BIT(V_038004_COLOR_32, 1),
130 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
131 FMT_32_BIT(V_038004_COLOR_16_16, 1),
132 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
133 FMT_32_BIT(V_038004_COLOR_8_24, 1),
134 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
135 FMT_32_BIT(V_038004_COLOR_24_8, 1),
136 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
137 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
138 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
139 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
140 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
141 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
142 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
143 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
144 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
145 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
146 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
147
148 /* 48-bit */
149 FMT_48_BIT(V_038004_FMT_16_16_16),
150 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
151
152 /* 64-bit */
153 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
154 FMT_64_BIT(V_038004_COLOR_32_32, 1),
155 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
156 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
157 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
158
159 FMT_96_BIT(V_038004_FMT_32_32_32),
160 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
161
162 /* 128-bit */
163 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
164 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
165
166 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
167 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
168
169 /* block compressed formats */
170 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
171 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
172 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
173 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
174 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
Marek Olšákfe6f0bd2011-05-07 01:09:57 +0200175 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
176 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
Dave Airlie60b212f2011-02-18 05:51:58 +0000177
Marek Olšákfe6f0bd2011-05-07 01:09:57 +0200178 /* The other Evergreen formats */
179 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
Dave Airlie60b212f2011-02-18 05:51:58 +0000180};
181
Jerome Glisse285484e2011-12-16 17:03:42 -0500182bool r600_fmt_is_valid_color(u32 format)
Dave Airlie60b212f2011-02-18 05:51:58 +0000183{
Dan Carpentercf8a47d2011-02-26 04:48:18 +0300184 if (format >= ARRAY_SIZE(color_formats_table))
Dave Airlie60b212f2011-02-18 05:51:58 +0000185 return false;
Jerome Glisse285484e2011-12-16 17:03:42 -0500186
Dave Airlie60b212f2011-02-18 05:51:58 +0000187 if (color_formats_table[format].valid_color)
188 return true;
189
190 return false;
191}
192
Jerome Glisse285484e2011-12-16 17:03:42 -0500193bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
Dave Airlie60b212f2011-02-18 05:51:58 +0000194{
Dan Carpentercf8a47d2011-02-26 04:48:18 +0300195 if (format >= ARRAY_SIZE(color_formats_table))
Dave Airlie60b212f2011-02-18 05:51:58 +0000196 return false;
Jerome Glisse285484e2011-12-16 17:03:42 -0500197
Marek Olšákfe6f0bd2011-05-07 01:09:57 +0200198 if (family < color_formats_table[format].min_family)
199 return false;
200
Dave Airlie60b212f2011-02-18 05:51:58 +0000201 if (color_formats_table[format].blockwidth > 0)
202 return true;
203
204 return false;
205}
206
Jerome Glisse285484e2011-12-16 17:03:42 -0500207int r600_fmt_get_blocksize(u32 format)
Dave Airlie60b212f2011-02-18 05:51:58 +0000208{
Dan Carpentercf8a47d2011-02-26 04:48:18 +0300209 if (format >= ARRAY_SIZE(color_formats_table))
Dave Airlie60b212f2011-02-18 05:51:58 +0000210 return 0;
211
212 return color_formats_table[format].blocksize;
213}
214
Jerome Glisse285484e2011-12-16 17:03:42 -0500215int r600_fmt_get_nblocksx(u32 format, u32 w)
Dave Airlie60b212f2011-02-18 05:51:58 +0000216{
217 unsigned bw;
Dan Carpentercf8a47d2011-02-26 04:48:18 +0300218
219 if (format >= ARRAY_SIZE(color_formats_table))
Dave Airlie60b212f2011-02-18 05:51:58 +0000220 return 0;
221
222 bw = color_formats_table[format].blockwidth;
223 if (bw == 0)
224 return 0;
225
226 return (w + bw - 1) / bw;
227}
228
Jerome Glisse285484e2011-12-16 17:03:42 -0500229int r600_fmt_get_nblocksy(u32 format, u32 h)
Dave Airlie60b212f2011-02-18 05:51:58 +0000230{
231 unsigned bh;
Dan Carpentercf8a47d2011-02-26 04:48:18 +0300232
233 if (format >= ARRAY_SIZE(color_formats_table))
Dave Airlie60b212f2011-02-18 05:51:58 +0000234 return 0;
235
236 bh = color_formats_table[format].blockheight;
237 if (bh == 0)
238 return 0;
239
240 return (h + bh - 1) / bh;
241}
242
Alex Deucher16790562010-11-14 20:24:35 -0500243struct array_mode_checker {
244 int array_mode;
245 u32 group_size;
246 u32 nbanks;
247 u32 npipes;
248 u32 nsamples;
Dave Airlie60b212f2011-02-18 05:51:58 +0000249 u32 blocksize;
Alex Deucher16790562010-11-14 20:24:35 -0500250};
251
252/* returns alignment in pixels for pitch/height/depth and bytes for base */
Andi Kleen488479e2011-10-13 16:08:41 -0700253static int r600_get_array_mode_alignment(struct array_mode_checker *values,
Alex Deucher16790562010-11-14 20:24:35 -0500254 u32 *pitch_align,
255 u32 *height_align,
256 u32 *depth_align,
257 u64 *base_align)
258{
259 u32 tile_width = 8;
260 u32 tile_height = 8;
261 u32 macro_tile_width = values->nbanks;
262 u32 macro_tile_height = values->npipes;
Dave Airlie60b212f2011-02-18 05:51:58 +0000263 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
Alex Deucher16790562010-11-14 20:24:35 -0500264 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
265
266 switch (values->array_mode) {
267 case ARRAY_LINEAR_GENERAL:
268 /* technically tile_width/_height for pitch/height */
269 *pitch_align = 1; /* tile_width */
270 *height_align = 1; /* tile_height */
271 *depth_align = 1;
272 *base_align = 1;
273 break;
274 case ARRAY_LINEAR_ALIGNED:
Dave Airlie60b212f2011-02-18 05:51:58 +0000275 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
Jerome Glisse285484e2011-12-16 17:03:42 -0500276 *height_align = 1;
Alex Deucher16790562010-11-14 20:24:35 -0500277 *depth_align = 1;
278 *base_align = values->group_size;
279 break;
280 case ARRAY_1D_TILED_THIN1:
281 *pitch_align = max((u32)tile_width,
282 (u32)(values->group_size /
Dave Airlie60b212f2011-02-18 05:51:58 +0000283 (tile_height * values->blocksize * values->nsamples)));
Alex Deucher16790562010-11-14 20:24:35 -0500284 *height_align = tile_height;
285 *depth_align = 1;
286 *base_align = values->group_size;
287 break;
288 case ARRAY_2D_TILED_THIN1:
Jerome Glisse285484e2011-12-16 17:03:42 -0500289 *pitch_align = max((u32)macro_tile_width * tile_width,
290 (u32)((values->group_size * values->nbanks) /
291 (values->blocksize * values->nsamples * tile_width)));
Alex Deucher16790562010-11-14 20:24:35 -0500292 *height_align = macro_tile_height * tile_height;
293 *depth_align = 1;
294 *base_align = max(macro_tile_bytes,
Dave Airlie60b212f2011-02-18 05:51:58 +0000295 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
Alex Deucher16790562010-11-14 20:24:35 -0500296 break;
297 default:
298 return -EINVAL;
299 }
300
301 return 0;
302}
303
Jerome Glisse961fb592010-02-10 22:30:05 +0000304static void r600_cs_track_init(struct r600_cs_track *track)
305{
306 int i;
307
Alex Deucher5f77df32010-03-26 14:52:32 -0400308 /* assume DX9 mode */
309 track->sq_config = DX9_CONSTS;
Jerome Glisse961fb592010-02-10 22:30:05 +0000310 for (i = 0; i < 8; i++) {
311 track->cb_color_base_last[i] = 0;
312 track->cb_color_size[i] = 0;
313 track->cb_color_size_idx[i] = 0;
314 track->cb_color_info[i] = 0;
Jerome Glisse285484e2011-12-16 17:03:42 -0500315 track->cb_color_view[i] = 0xFFFFFFFF;
Jerome Glisse961fb592010-02-10 22:30:05 +0000316 track->cb_color_bo[i] = NULL;
317 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
Alex Deucher16790562010-11-14 20:24:35 -0500318 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
Marek Olšák3b5ef592012-08-22 17:02:43 +0200319 track->cb_color_frag_bo[i] = NULL;
320 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
321 track->cb_color_tile_bo[i] = NULL;
322 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
323 track->cb_color_mask[i] = 0xFFFFFFFF;
Jerome Glisse961fb592010-02-10 22:30:05 +0000324 }
Marek Olšák523885d2012-08-24 14:27:36 +0200325 track->is_resolve = false;
Marek Olšák3b5ef592012-08-22 17:02:43 +0200326 track->nsamples = 16;
327 track->log_nsamples = 4;
Jerome Glisse961fb592010-02-10 22:30:05 +0000328 track->cb_target_mask = 0xFFFFFFFF;
329 track->cb_shader_mask = 0xFFFFFFFF;
Marek Olšák3c125132012-03-19 03:09:38 +0100330 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +0000331 track->db_bo = NULL;
Alex Deucher16790562010-11-14 20:24:35 -0500332 track->db_bo_mc = 0xFFFFFFFF;
Jerome Glisse961fb592010-02-10 22:30:05 +0000333 /* assume the biggest format and that htile is enabled */
334 track->db_depth_info = 7 | (1 << 25);
335 track->db_depth_view = 0xFFFFC000;
336 track->db_depth_size = 0xFFFFFFFF;
337 track->db_depth_size_idx = 0;
338 track->db_depth_control = 0xFFFFFFFF;
Marek Olšák3c125132012-03-19 03:09:38 +0100339 track->db_dirty = true;
Jerome Glisse88f50c82012-03-21 19:18:21 -0400340 track->htile_bo = NULL;
341 track->htile_offset = 0xFFFFFFFF;
342 track->htile_surface = 0;
Marek Olšákdd220a02012-01-27 12:17:59 -0500343
344 for (i = 0; i < 4; i++) {
345 track->vgt_strmout_size[i] = 0;
346 track->vgt_strmout_bo[i] = NULL;
347 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
348 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
349 }
Marek Olšák3c125132012-03-19 03:09:38 +0100350 track->streamout_dirty = true;
Marek Olšák779923b2012-03-08 00:56:00 +0100351 track->sx_misc_kill_all_prims = false;
Jerome Glisse961fb592010-02-10 22:30:05 +0000352}
353
Andi Kleen488479e2011-10-13 16:08:41 -0700354static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
Jerome Glisse961fb592010-02-10 22:30:05 +0000355{
356 struct r600_cs_track *track = p->track;
Dave Airlie60b212f2011-02-18 05:51:58 +0000357 u32 slice_tile_max, size, tmp;
Alex Deucher16790562010-11-14 20:24:35 -0500358 u32 height, height_align, pitch, pitch_align, depth_align;
359 u64 base_offset, base_align;
360 struct array_mode_checker array_check;
Jerome Glissef2e39222012-05-09 15:35:02 +0200361 volatile u32 *ib = p->ib.ptr;
Dave Airlief30df2f2010-10-21 13:55:40 +1000362 unsigned array_mode;
Dave Airlie60b212f2011-02-18 05:51:58 +0000363 u32 format;
Marek Olšák523885d2012-08-24 14:27:36 +0200364 /* When resolve is used, the second colorbuffer has always 1 sample. */
365 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
Jerome Glisse285484e2011-12-16 17:03:42 -0500366
Alex Deucher1729dd32010-08-06 02:54:05 -0400367 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
Dave Airlie60b212f2011-02-18 05:51:58 +0000368 format = G_0280A0_FORMAT(track->cb_color_info[i]);
Jerome Glisse285484e2011-12-16 17:03:42 -0500369 if (!r600_fmt_is_valid_color(format)) {
Jerome Glisse961fb592010-02-10 22:30:05 +0000370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
Dave Airlie60b212f2011-02-18 05:51:58 +0000371 __func__, __LINE__, format,
Jerome Glisse961fb592010-02-10 22:30:05 +0000372 i, track->cb_color_info[i]);
373 return -EINVAL;
374 }
Alex Deucher16790562010-11-14 20:24:35 -0500375 /* pitch in pixels */
376 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
Jerome Glisse961fb592010-02-10 22:30:05 +0000377 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
Dave Airlief30df2f2010-10-21 13:55:40 +1000378 slice_tile_max *= 64;
Alex Deucher16790562010-11-14 20:24:35 -0500379 height = slice_tile_max / pitch;
Jerome Glisse961fb592010-02-10 22:30:05 +0000380 if (height > 8192)
381 height = 8192;
Dave Airlief30df2f2010-10-21 13:55:40 +1000382 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
Alex Deucher16790562010-11-14 20:24:35 -0500383
384 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
385 array_check.array_mode = array_mode;
386 array_check.group_size = track->group_size;
387 array_check.nbanks = track->nbanks;
388 array_check.npipes = track->npipes;
Marek Olšák523885d2012-08-24 14:27:36 +0200389 array_check.nsamples = nsamples;
Jerome Glisse285484e2011-12-16 17:03:42 -0500390 array_check.blocksize = r600_fmt_get_blocksize(format);
Alex Deucher16790562010-11-14 20:24:35 -0500391 if (r600_get_array_mode_alignment(&array_check,
392 &pitch_align, &height_align, &depth_align, &base_align)) {
393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
394 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
395 track->cb_color_info[i]);
396 return -EINVAL;
397 }
Dave Airlief30df2f2010-10-21 13:55:40 +1000398 switch (array_mode) {
Jerome Glisse961fb592010-02-10 22:30:05 +0000399 case V_0280A0_ARRAY_LINEAR_GENERAL:
Alex Deucher40e2a5c2010-06-04 18:41:42 -0400400 break;
Jerome Glisse961fb592010-02-10 22:30:05 +0000401 case V_0280A0_ARRAY_LINEAR_ALIGNED:
Jerome Glisse961fb592010-02-10 22:30:05 +0000402 break;
403 case V_0280A0_ARRAY_1D_TILED_THIN1:
Alex Deucher8f895da2010-10-26 20:22:42 -0400404 /* avoid breaking userspace */
405 if (height > 7)
406 height &= ~0x7;
Jerome Glisse961fb592010-02-10 22:30:05 +0000407 break;
408 case V_0280A0_ARRAY_2D_TILED_THIN1:
Jerome Glisse961fb592010-02-10 22:30:05 +0000409 break;
410 default:
411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
412 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
413 track->cb_color_info[i]);
414 return -EINVAL;
415 }
Alex Deucher16790562010-11-14 20:24:35 -0500416
417 if (!IS_ALIGNED(pitch, pitch_align)) {
Alex Deucherc2049b32011-02-13 18:42:41 -0500418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
419 __func__, __LINE__, pitch, pitch_align, array_mode);
Alex Deucher16790562010-11-14 20:24:35 -0500420 return -EINVAL;
421 }
422 if (!IS_ALIGNED(height, height_align)) {
Alex Deucherc2049b32011-02-13 18:42:41 -0500423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
424 __func__, __LINE__, height, height_align, array_mode);
Alex Deucher16790562010-11-14 20:24:35 -0500425 return -EINVAL;
426 }
427 if (!IS_ALIGNED(base_offset, base_align)) {
Alex Deucherc2049b32011-02-13 18:42:41 -0500428 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
429 base_offset, base_align, array_mode);
Alex Deucher16790562010-11-14 20:24:35 -0500430 return -EINVAL;
431 }
432
Jerome Glisse961fb592010-02-10 22:30:05 +0000433 /* check offset */
Marek Olšákfcdeefe2012-08-19 21:23:26 +0200434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
Marek Olšák523885d2012-08-24 14:27:36 +0200435 r600_fmt_get_blocksize(format) * nsamples;
Jerome Glisse285484e2011-12-16 17:03:42 -0500436 switch (array_mode) {
437 default:
438 case V_0280A0_ARRAY_LINEAR_GENERAL:
439 case V_0280A0_ARRAY_LINEAR_ALIGNED:
440 tmp += track->cb_color_view[i] & 0xFF;
441 break;
442 case V_0280A0_ARRAY_1D_TILED_THIN1:
443 case V_0280A0_ARRAY_2D_TILED_THIN1:
444 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
445 break;
446 }
Jerome Glisse961fb592010-02-10 22:30:05 +0000447 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
Dave Airlief30df2f2010-10-21 13:55:40 +1000448 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
449 /* the initial DDX does bad things with the CB size occasionally */
450 /* it rounds up height too far for slice tile max but the BO is smaller */
Alex Deuchera1a82132010-12-13 14:03:09 -0500451 /* r600c,g also seem to flush at bad times in some apps resulting in
452 * bogus values here. So for linear just allow anything to avoid breaking
453 * broken userspace.
454 */
Dave Airlief30df2f2010-10-21 13:55:40 +1000455 } else {
Marek Olšákc116cc92012-08-19 02:22:09 +0200456 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
Jerome Glisse285484e2011-12-16 17:03:42 -0500457 __func__, i, array_mode,
Alex Deucherc2049b32011-02-13 18:42:41 -0500458 track->cb_color_bo_offset[i], tmp,
Jerome Glisse285484e2011-12-16 17:03:42 -0500459 radeon_bo_size(track->cb_color_bo[i]),
460 pitch, height, r600_fmt_get_nblocksx(format, pitch),
461 r600_fmt_get_nblocksy(format, height),
462 r600_fmt_get_blocksize(format));
Dave Airlief30df2f2010-10-21 13:55:40 +1000463 return -EINVAL;
464 }
Alex Deucher40e2a5c2010-06-04 18:41:42 -0400465 }
Jerome Glisse961fb592010-02-10 22:30:05 +0000466 /* limit max tile */
Alex Deucher16790562010-11-14 20:24:35 -0500467 tmp = (height * pitch) >> 6;
Jerome Glisse961fb592010-02-10 22:30:05 +0000468 if (tmp < slice_tile_max)
469 slice_tile_max = tmp;
Alex Deucher16790562010-11-14 20:24:35 -0500470 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
Jerome Glisse961fb592010-02-10 22:30:05 +0000471 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
472 ib[track->cb_color_size_idx[i]] = tmp;
Marek Olšákc116cc92012-08-19 02:22:09 +0200473
474 /* FMASK/CMASK */
475 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
476 case V_0280A0_TILE_DISABLE:
477 break;
478 case V_0280A0_FRAG_ENABLE:
479 if (track->nsamples > 1) {
480 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
481 /* the tile size is 8x8, but the size is in units of bits.
482 * for bytes, do just * 8. */
483 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
484
485 if (bytes + track->cb_color_frag_offset[i] >
486 radeon_bo_size(track->cb_color_frag_bo[i])) {
487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
488 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
489 __func__, tile_max, bytes,
490 track->cb_color_frag_offset[i],
491 radeon_bo_size(track->cb_color_frag_bo[i]));
492 return -EINVAL;
493 }
494 }
495 /* fall through */
496 case V_0280A0_CLEAR_ENABLE:
497 {
498 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
499 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
500 * (128*128) / (8*8) / 2 = 128 bytes per block. */
501 uint32_t bytes = (block_max + 1) * 128;
502
503 if (bytes + track->cb_color_tile_offset[i] >
504 radeon_bo_size(track->cb_color_tile_bo[i])) {
505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
506 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
507 __func__, block_max, bytes,
508 track->cb_color_tile_offset[i],
509 radeon_bo_size(track->cb_color_tile_bo[i]));
510 return -EINVAL;
511 }
512 break;
513 }
514 default:
515 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
516 return -EINVAL;
517 }
Jerome Glisse961fb592010-02-10 22:30:05 +0000518 return 0;
519}
520
Jerome Glisse88f50c82012-03-21 19:18:21 -0400521static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
522{
523 struct r600_cs_track *track = p->track;
524 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
525 u32 height_align, pitch_align, depth_align;
526 u32 pitch = 8192;
527 u32 height = 8192;
528 u64 base_offset, base_align;
529 struct array_mode_checker array_check;
530 int array_mode;
Jerome Glissef2e39222012-05-09 15:35:02 +0200531 volatile u32 *ib = p->ib.ptr;
Jerome Glisse88f50c82012-03-21 19:18:21 -0400532
533
534 if (track->db_bo == NULL) {
535 dev_warn(p->dev, "z/stencil with no depth buffer\n");
536 return -EINVAL;
537 }
538 switch (G_028010_FORMAT(track->db_depth_info)) {
539 case V_028010_DEPTH_16:
540 bpe = 2;
541 break;
542 case V_028010_DEPTH_X8_24:
543 case V_028010_DEPTH_8_24:
544 case V_028010_DEPTH_X8_24_FLOAT:
545 case V_028010_DEPTH_8_24_FLOAT:
546 case V_028010_DEPTH_32_FLOAT:
547 bpe = 4;
548 break;
549 case V_028010_DEPTH_X24_8_32_FLOAT:
550 bpe = 8;
551 break;
552 default:
553 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
554 return -EINVAL;
555 }
556 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
557 if (!track->db_depth_size_idx) {
558 dev_warn(p->dev, "z/stencil buffer size not set\n");
559 return -EINVAL;
560 }
561 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
562 tmp = (tmp / bpe) >> 6;
563 if (!tmp) {
564 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
565 track->db_depth_size, bpe, track->db_offset,
566 radeon_bo_size(track->db_bo));
567 return -EINVAL;
568 }
569 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
570 } else {
571 size = radeon_bo_size(track->db_bo);
572 /* pitch in pixels */
573 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
574 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
575 slice_tile_max *= 64;
576 height = slice_tile_max / pitch;
577 if (height > 8192)
578 height = 8192;
579 base_offset = track->db_bo_mc + track->db_offset;
580 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
581 array_check.array_mode = array_mode;
582 array_check.group_size = track->group_size;
583 array_check.nbanks = track->nbanks;
584 array_check.npipes = track->npipes;
585 array_check.nsamples = track->nsamples;
586 array_check.blocksize = bpe;
587 if (r600_get_array_mode_alignment(&array_check,
588 &pitch_align, &height_align, &depth_align, &base_align)) {
589 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
590 G_028010_ARRAY_MODE(track->db_depth_info),
591 track->db_depth_info);
592 return -EINVAL;
593 }
594 switch (array_mode) {
595 case V_028010_ARRAY_1D_TILED_THIN1:
596 /* don't break userspace */
597 height &= ~0x7;
598 break;
599 case V_028010_ARRAY_2D_TILED_THIN1:
600 break;
601 default:
602 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
603 G_028010_ARRAY_MODE(track->db_depth_info),
604 track->db_depth_info);
605 return -EINVAL;
606 }
607
608 if (!IS_ALIGNED(pitch, pitch_align)) {
609 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
610 __func__, __LINE__, pitch, pitch_align, array_mode);
611 return -EINVAL;
612 }
613 if (!IS_ALIGNED(height, height_align)) {
614 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
615 __func__, __LINE__, height, height_align, array_mode);
616 return -EINVAL;
617 }
618 if (!IS_ALIGNED(base_offset, base_align)) {
619 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
620 base_offset, base_align, array_mode);
621 return -EINVAL;
622 }
623
624 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
625 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
Marek Olšákfcdeefe2012-08-19 21:23:26 +0200626 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
Jerome Glisse88f50c82012-03-21 19:18:21 -0400627 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
628 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
629 array_mode,
630 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
631 radeon_bo_size(track->db_bo));
632 return -EINVAL;
633 }
634 }
635
636 /* hyperz */
637 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
638 unsigned long size;
639 unsigned nbx, nby;
640
641 if (track->htile_bo == NULL) {
642 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
643 __func__, __LINE__, track->db_depth_info);
644 return -EINVAL;
645 }
646 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
647 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
648 __func__, __LINE__, track->db_depth_size);
649 return -EINVAL;
650 }
651
652 nbx = pitch;
653 nby = height;
654 if (G_028D24_LINEAR(track->htile_surface)) {
655 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
656 nbx = round_up(nbx, 16 * 8);
657 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
658 nby = round_up(nby, track->npipes * 8);
659 } else {
Jerome Glisse4ac05332012-12-13 12:08:11 -0500660 /* always assume 8x8 htile */
Jerome Glisse88f50c82012-03-21 19:18:21 -0400661 /* align is htile align * 8, htile align vary according to
662 * number of pipe and tile width and nby
663 */
664 switch (track->npipes) {
665 case 8:
Jerome Glisse4ac05332012-12-13 12:08:11 -0500666 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
667 nbx = round_up(nbx, 64 * 8);
668 nby = round_up(nby, 64 * 8);
Jerome Glisse88f50c82012-03-21 19:18:21 -0400669 break;
670 case 4:
Jerome Glisse4ac05332012-12-13 12:08:11 -0500671 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
672 nbx = round_up(nbx, 64 * 8);
673 nby = round_up(nby, 32 * 8);
Jerome Glisse88f50c82012-03-21 19:18:21 -0400674 break;
675 case 2:
Jerome Glisse4ac05332012-12-13 12:08:11 -0500676 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
677 nbx = round_up(nbx, 32 * 8);
678 nby = round_up(nby, 32 * 8);
Jerome Glisse88f50c82012-03-21 19:18:21 -0400679 break;
680 case 1:
Jerome Glisse4ac05332012-12-13 12:08:11 -0500681 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
682 nbx = round_up(nbx, 32 * 8);
683 nby = round_up(nby, 16 * 8);
Jerome Glisse88f50c82012-03-21 19:18:21 -0400684 break;
685 default:
686 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
687 __func__, __LINE__, track->npipes);
688 return -EINVAL;
689 }
690 }
691 /* compute number of htile */
Jerome Glisse4ac05332012-12-13 12:08:11 -0500692 nbx = nbx >> 3;
693 nby = nby >> 3;
694 /* size must be aligned on npipes * 2K boundary */
695 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
Jerome Glisse88f50c82012-03-21 19:18:21 -0400696 size += track->htile_offset;
697
698 if (size > radeon_bo_size(track->htile_bo)) {
699 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
700 __func__, __LINE__, radeon_bo_size(track->htile_bo),
701 size, nbx, nby);
702 return -EINVAL;
703 }
704 }
705
706 track->db_dirty = false;
707 return 0;
708}
709
Jerome Glisse961fb592010-02-10 22:30:05 +0000710static int r600_cs_track_check(struct radeon_cs_parser *p)
711{
712 struct r600_cs_track *track = p->track;
713 u32 tmp;
714 int r, i;
Jerome Glisse961fb592010-02-10 22:30:05 +0000715
716 /* on legacy kernel we don't perform advanced check */
717 if (p->rdev == NULL)
718 return 0;
Marek Olšákdd220a02012-01-27 12:17:59 -0500719
720 /* check streamout */
Marek Olšák3c125132012-03-19 03:09:38 +0100721 if (track->streamout_dirty && track->vgt_strmout_en) {
Marek Olšákdd220a02012-01-27 12:17:59 -0500722 for (i = 0; i < 4; i++) {
723 if (track->vgt_strmout_buffer_en & (1 << i)) {
724 if (track->vgt_strmout_bo[i]) {
725 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
726 (u64)track->vgt_strmout_size[i];
727 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
728 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
729 i, offset,
730 radeon_bo_size(track->vgt_strmout_bo[i]));
731 return -EINVAL;
732 }
733 } else {
734 dev_warn(p->dev, "No buffer for streamout %d\n", i);
735 return -EINVAL;
736 }
737 }
738 }
Marek Olšák3c125132012-03-19 03:09:38 +0100739 track->streamout_dirty = false;
Jerome Glisse961fb592010-02-10 22:30:05 +0000740 }
Marek Olšákdd220a02012-01-27 12:17:59 -0500741
Marek Olšák779923b2012-03-08 00:56:00 +0100742 if (track->sx_misc_kill_all_prims)
743 return 0;
744
Jerome Glisse961fb592010-02-10 22:30:05 +0000745 /* check that we have a cb for each enabled target, we don't check
746 * shader_mask because it seems mesa isn't always setting it :(
747 */
Marek Olšák3c125132012-03-19 03:09:38 +0100748 if (track->cb_dirty) {
749 tmp = track->cb_target_mask;
Marek Olšák523885d2012-08-24 14:27:36 +0200750
751 /* We must check both colorbuffers for RESOLVE. */
752 if (track->is_resolve) {
753 tmp |= 0xff;
754 }
755
Marek Olšák3c125132012-03-19 03:09:38 +0100756 for (i = 0; i < 8; i++) {
757 if ((tmp >> (i * 4)) & 0xF) {
758 /* at least one component is enabled */
759 if (track->cb_color_bo[i] == NULL) {
760 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
761 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
762 return -EINVAL;
763 }
764 /* perform rewrite of CB_COLOR[0-7]_SIZE */
765 r = r600_cs_track_validate_cb(p, i);
766 if (r)
767 return r;
Jerome Glisse961fb592010-02-10 22:30:05 +0000768 }
Jerome Glisse961fb592010-02-10 22:30:05 +0000769 }
Marek Olšák3c125132012-03-19 03:09:38 +0100770 track->cb_dirty = false;
Jerome Glisse961fb592010-02-10 22:30:05 +0000771 }
Alex Deucher16790562010-11-14 20:24:35 -0500772
Jerome Glisse88f50c82012-03-21 19:18:21 -0400773 /* Check depth buffer */
Marek Olšák0f457e42012-07-29 16:24:57 +0200774 if (track->db_dirty &&
775 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
776 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
777 G_028800_Z_ENABLE(track->db_depth_control))) {
Jerome Glisse88f50c82012-03-21 19:18:21 -0400778 r = r600_cs_track_validate_db(p);
779 if (r)
780 return r;
Jerome Glisse961fb592010-02-10 22:30:05 +0000781 }
Jerome Glisse88f50c82012-03-21 19:18:21 -0400782
Jerome Glisse961fb592010-02-10 22:30:05 +0000783 return 0;
784}
785
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000786/**
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000787 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
788 * @parser: parser structure holding parsing context.
789 * @data: pointer to relocation data
790 * @offset_start: starting offset
791 * @offset_mask: offset mask (to align start offset on)
792 * @reloc: reloc informations
793 *
794 * Check next packet is relocation packet3, do bo validation and compute
795 * GPU offset using the provided start.
796 **/
797static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
798 struct radeon_cs_reloc **cs_reloc)
799{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000800 struct radeon_cs_chunk *relocs_chunk;
801 struct radeon_cs_packet p3reloc;
802 unsigned idx;
803 int r;
804
805 if (p->chunk_relocs_idx == -1) {
806 DRM_ERROR("No relocation chunk !\n");
807 return -EINVAL;
808 }
809 *cs_reloc = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000810 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
Ilija Hadzicc38f34b2013-01-02 18:27:41 -0500811 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000812 if (r) {
813 return r;
814 }
815 p->idx += p3reloc.count + 2;
816 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
817 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
818 p3reloc.idx);
819 return -EINVAL;
820 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000821 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000822 if (idx >= relocs_chunk->length_dw) {
823 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
824 idx, relocs_chunk->length_dw);
825 return -EINVAL;
826 }
827 /* FIXME: we assume reloc size is 4 dwords */
828 *cs_reloc = p->relocs_ptr[(idx / 4)];
829 return 0;
830}
831
832/**
833 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
834 * @parser: parser structure holding parsing context.
835 * @data: pointer to relocation data
836 * @offset_start: starting offset
837 * @offset_mask: offset mask (to align start offset on)
838 * @reloc: reloc informations
839 *
840 * Check next packet is relocation packet3, do bo validation and compute
841 * GPU offset using the provided start.
842 **/
843static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
844 struct radeon_cs_reloc **cs_reloc)
845{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000846 struct radeon_cs_chunk *relocs_chunk;
847 struct radeon_cs_packet p3reloc;
848 unsigned idx;
849 int r;
850
851 if (p->chunk_relocs_idx == -1) {
852 DRM_ERROR("No relocation chunk !\n");
853 return -EINVAL;
854 }
855 *cs_reloc = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000856 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
Ilija Hadzicc38f34b2013-01-02 18:27:41 -0500857 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000858 if (r) {
859 return r;
860 }
861 p->idx += p3reloc.count + 2;
862 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
863 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
864 p3reloc.idx);
865 return -EINVAL;
866 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000867 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000868 if (idx >= relocs_chunk->length_dw) {
869 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
870 idx, relocs_chunk->length_dw);
871 return -EINVAL;
872 }
Julia Lawalle265f39e2009-12-19 08:16:33 +0100873 *cs_reloc = p->relocs;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000874 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
875 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
876 return 0;
877}
878
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400879/**
Ilija Hadzic40592a12013-01-02 18:27:43 -0500880 * r600_cs_packet_parse_vline() - parse userspace VLINE packet
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400881 * @parser: parser structure holding parsing context.
882 *
Ilija Hadzic40592a12013-01-02 18:27:43 -0500883 * This is an R600-specific function for parsing VLINE packets.
884 * Real work is done by r600_cs_common_vline_parse function.
885 * Here we just set up ASIC-specific register table and call
886 * the common implementation function.
887 */
888static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
889{
890 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,
891 AVIVO_D2MODE_VLINE_START_END};
892 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,
893 AVIVO_D2MODE_VLINE_STATUS};
894
895 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
896}
897
898/**
899 * r600_cs_common_vline_parse() - common vline parser
900 * @parser: parser structure holding parsing context.
901 * @vline_start_end: table of vline_start_end registers
902 * @vline_status: table of vline_status registers
903 *
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400904 * Userspace sends a special sequence for VLINE waits.
905 * PACKET0 - VLINE_START_END + value
906 * PACKET3 - WAIT_REG_MEM poll vline status reg
907 * RELOC (P3) - crtc_id in reloc.
908 *
909 * This function parses this and relocates the VLINE START END
910 * and WAIT_REG_MEM packets to the correct crtc.
911 * It also detects a switched off crtc and nulls out the
Ilija Hadzic40592a12013-01-02 18:27:43 -0500912 * wait in that case. This function is common for all ASICs that
913 * are R600 and newer. The parsing algorithm is the same, and only
914 * differs in which registers are used.
915 *
916 * Caller is the ASIC-specific function which passes the parser
917 * context and ASIC-specific register table
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400918 */
Ilija Hadzic40592a12013-01-02 18:27:43 -0500919int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
920 uint32_t *vline_start_end,
921 uint32_t *vline_status)
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400922{
923 struct drm_mode_object *obj;
924 struct drm_crtc *crtc;
925 struct radeon_crtc *radeon_crtc;
926 struct radeon_cs_packet p3reloc, wait_reg_mem;
927 int crtc_id;
928 int r;
929 uint32_t header, h_idx, reg, wait_reg_mem_info;
930 volatile uint32_t *ib;
931
Jerome Glissef2e39222012-05-09 15:35:02 +0200932 ib = p->ib.ptr;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400933
934 /* parse the WAIT_REG_MEM */
Ilija Hadzicc38f34b2013-01-02 18:27:41 -0500935 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400936 if (r)
937 return r;
938
939 /* check its a WAIT_REG_MEM */
940 if (wait_reg_mem.type != PACKET_TYPE3 ||
941 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
942 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
Paul Bollea3a88a62011-03-16 22:10:06 +0100943 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400944 }
945
946 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
947 /* bit 4 is reg (0) or mem (1) */
948 if (wait_reg_mem_info & 0x10) {
Ilija Hadzic40592a12013-01-02 18:27:43 -0500949 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
Paul Bollea3a88a62011-03-16 22:10:06 +0100950 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400951 }
Ilija Hadzicd6e18a32013-01-02 18:27:44 -0500952 /* bit 8 is me (0) or pfp (1) */
953 if (wait_reg_mem_info & 0x100) {
954 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
955 return -EINVAL;
956 }
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400957 /* waiting for value to be equal */
958 if ((wait_reg_mem_info & 0x7) != 0x3) {
959 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
Paul Bollea3a88a62011-03-16 22:10:06 +0100960 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400961 }
Ilija Hadzic40592a12013-01-02 18:27:43 -0500962 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400963 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
Paul Bollea3a88a62011-03-16 22:10:06 +0100964 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400965 }
966
Ilija Hadzic40592a12013-01-02 18:27:43 -0500967 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400968 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
Paul Bollea3a88a62011-03-16 22:10:06 +0100969 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400970 }
971
972 /* jump over the NOP */
Ilija Hadzicc38f34b2013-01-02 18:27:41 -0500973 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400974 if (r)
975 return r;
976
977 h_idx = p->idx - 2;
978 p->idx += wait_reg_mem.count + 2;
979 p->idx += p3reloc.count + 2;
980
981 header = radeon_get_ib_value(p, h_idx);
982 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
Dave Airlied4ac6a02009-10-08 11:32:49 +1000983 reg = CP_PACKET0_GET_REG(header);
Dave Airlie29508eb2010-07-22 09:57:13 +1000984
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400985 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
986 if (!obj) {
987 DRM_ERROR("cannot find crtc %d\n", crtc_id);
Paul Bollea3a88a62011-03-16 22:10:06 +0100988 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400989 }
990 crtc = obj_to_crtc(obj);
991 radeon_crtc = to_radeon_crtc(crtc);
992 crtc_id = radeon_crtc->crtc_id;
993
994 if (!crtc->enabled) {
Ilija Hadzic40592a12013-01-02 18:27:43 -0500995 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
Alex Deucher2f67c6e2009-09-25 16:35:11 -0400996 ib[h_idx + 2] = PACKET2(0);
997 ib[h_idx + 3] = PACKET2(0);
998 ib[h_idx + 4] = PACKET2(0);
999 ib[h_idx + 5] = PACKET2(0);
1000 ib[h_idx + 6] = PACKET2(0);
1001 ib[h_idx + 7] = PACKET2(0);
1002 ib[h_idx + 8] = PACKET2(0);
Ilija Hadzic40592a12013-01-02 18:27:43 -05001003 } else if (reg == vline_start_end[0]) {
1004 header &= ~R600_CP_PACKET0_REG_MASK;
1005 header |= vline_start_end[crtc_id] >> 2;
Alex Deucher2f67c6e2009-09-25 16:35:11 -04001006 ib[h_idx] = header;
Ilija Hadzic40592a12013-01-02 18:27:43 -05001007 ib[h_idx + 4] = vline_status[crtc_id] >> 2;
1008 } else {
1009 DRM_ERROR("unknown crtc reloc\n");
1010 return -EINVAL;
Alex Deucher2f67c6e2009-09-25 16:35:11 -04001011 }
Paul Bollea3a88a62011-03-16 22:10:06 +01001012 return 0;
Alex Deucher2f67c6e2009-09-25 16:35:11 -04001013}
1014
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001015static int r600_packet0_check(struct radeon_cs_parser *p,
1016 struct radeon_cs_packet *pkt,
1017 unsigned idx, unsigned reg)
1018{
Alex Deucher2f67c6e2009-09-25 16:35:11 -04001019 int r;
1020
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001021 switch (reg) {
1022 case AVIVO_D1MODE_VLINE_START_END:
Alex Deucher2f67c6e2009-09-25 16:35:11 -04001023 r = r600_cs_packet_parse_vline(p);
1024 if (r) {
1025 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1026 idx, reg);
1027 return r;
1028 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001029 break;
1030 default:
1031 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1032 reg, idx);
1033 return -EINVAL;
1034 }
1035 return 0;
1036}
1037
1038static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1039 struct radeon_cs_packet *pkt)
1040{
1041 unsigned reg, i;
1042 unsigned idx;
1043 int r;
1044
1045 idx = pkt->idx + 1;
1046 reg = pkt->reg;
1047 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1048 r = r600_packet0_check(p, pkt, idx, reg);
1049 if (r) {
1050 return r;
1051 }
1052 }
1053 return 0;
1054}
1055
Jerome Glisse961fb592010-02-10 22:30:05 +00001056/**
1057 * r600_cs_check_reg() - check if register is authorized or not
1058 * @parser: parser structure holding parsing context
1059 * @reg: register we are testing
1060 * @idx: index into the cs buffer
1061 *
1062 * This function will test against r600_reg_safe_bm and return 0
1063 * if register is safe. If register is not flag as safe this function
1064 * will test it against a list of register needind special handling.
1065 */
Andi Kleen488479e2011-10-13 16:08:41 -07001066static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
Jerome Glisse961fb592010-02-10 22:30:05 +00001067{
1068 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1069 struct radeon_cs_reloc *reloc;
Jerome Glisse961fb592010-02-10 22:30:05 +00001070 u32 m, i, tmp, *ib;
1071 int r;
1072
1073 i = (reg >> 7);
Dan Carpenter88498832011-07-27 09:53:40 +00001074 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
Jerome Glisse961fb592010-02-10 22:30:05 +00001075 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1076 return -EINVAL;
1077 }
1078 m = 1 << ((reg >> 2) & 31);
1079 if (!(r600_reg_safe_bm[i] & m))
1080 return 0;
Jerome Glissef2e39222012-05-09 15:35:02 +02001081 ib = p->ib.ptr;
Jerome Glisse961fb592010-02-10 22:30:05 +00001082 switch (reg) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001083 /* force following reg to 0 in an attempt to disable out buffer
Jerome Glisse961fb592010-02-10 22:30:05 +00001084 * which will need us to better understand how it works to perform
1085 * security check on it (Jerome)
1086 */
1087 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1088 case R_008C44_SQ_ESGS_RING_SIZE:
1089 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1090 case R_008C54_SQ_ESTMP_RING_SIZE:
1091 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1092 case R_008C74_SQ_FBUF_RING_SIZE:
1093 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1094 case R_008C5C_SQ_GSTMP_RING_SIZE:
1095 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1096 case R_008C4C_SQ_GSVS_RING_SIZE:
1097 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1098 case R_008C6C_SQ_PSTMP_RING_SIZE:
1099 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1100 case R_008C7C_SQ_REDUC_RING_SIZE:
1101 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1102 case R_008C64_SQ_VSTMP_RING_SIZE:
1103 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1104 /* get value to populate the IB don't remove */
1105 tmp =radeon_get_ib_value(p, idx);
1106 ib[idx] = 0;
1107 break;
Alex Deucher5f77df32010-03-26 14:52:32 -04001108 case SQ_CONFIG:
1109 track->sq_config = radeon_get_ib_value(p, idx);
1110 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001111 case R_028800_DB_DEPTH_CONTROL:
1112 track->db_depth_control = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001113 track->db_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001114 break;
1115 case R_028010_DB_DEPTH_INFO:
Jerome Glisse721604a2012-01-05 22:11:05 -05001116 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05001117 radeon_cs_packet_next_is_pkt3_nop(p)) {
Alex Deucher7f813372010-05-20 12:43:52 -04001118 r = r600_cs_packet_next_reloc(p, &reloc);
1119 if (r) {
1120 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1121 "0x%04X\n", reg);
1122 return -EINVAL;
1123 }
1124 track->db_depth_info = radeon_get_ib_value(p, idx);
1125 ib[idx] &= C_028010_ARRAY_MODE;
1126 track->db_depth_info &= C_028010_ARRAY_MODE;
1127 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1128 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1129 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1130 } else {
1131 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1132 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1133 }
Marek Olšák3c125132012-03-19 03:09:38 +01001134 } else {
Alex Deucher7f813372010-05-20 12:43:52 -04001135 track->db_depth_info = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001136 }
1137 track->db_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001138 break;
1139 case R_028004_DB_DEPTH_VIEW:
1140 track->db_depth_view = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001141 track->db_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001142 break;
1143 case R_028000_DB_DEPTH_SIZE:
1144 track->db_depth_size = radeon_get_ib_value(p, idx);
1145 track->db_depth_size_idx = idx;
Marek Olšák3c125132012-03-19 03:09:38 +01001146 track->db_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001147 break;
1148 case R_028AB0_VGT_STRMOUT_EN:
1149 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001150 track->streamout_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001151 break;
1152 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1153 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001154 track->streamout_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001155 break;
Marek Olšákdd220a02012-01-27 12:17:59 -05001156 case VGT_STRMOUT_BUFFER_BASE_0:
1157 case VGT_STRMOUT_BUFFER_BASE_1:
1158 case VGT_STRMOUT_BUFFER_BASE_2:
1159 case VGT_STRMOUT_BUFFER_BASE_3:
1160 r = r600_cs_packet_next_reloc(p, &reloc);
1161 if (r) {
1162 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1163 "0x%04X\n", reg);
1164 return -EINVAL;
1165 }
1166 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1167 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1168 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1169 track->vgt_strmout_bo[tmp] = reloc->robj;
1170 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
Marek Olšák3c125132012-03-19 03:09:38 +01001171 track->streamout_dirty = true;
Marek Olšákdd220a02012-01-27 12:17:59 -05001172 break;
1173 case VGT_STRMOUT_BUFFER_SIZE_0:
1174 case VGT_STRMOUT_BUFFER_SIZE_1:
1175 case VGT_STRMOUT_BUFFER_SIZE_2:
1176 case VGT_STRMOUT_BUFFER_SIZE_3:
1177 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1178 /* size in register is DWs, convert to bytes */
1179 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
Marek Olšák3c125132012-03-19 03:09:38 +01001180 track->streamout_dirty = true;
Marek Olšákdd220a02012-01-27 12:17:59 -05001181 break;
1182 case CP_COHER_BASE:
1183 r = r600_cs_packet_next_reloc(p, &reloc);
1184 if (r) {
1185 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1186 "0x%04X\n", reg);
1187 return -EINVAL;
1188 }
1189 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1190 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001191 case R_028238_CB_TARGET_MASK:
1192 track->cb_target_mask = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001193 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001194 break;
1195 case R_02823C_CB_SHADER_MASK:
1196 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1197 break;
1198 case R_028C04_PA_SC_AA_CONFIG:
1199 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
Marek Olšákc116cc92012-08-19 02:22:09 +02001200 track->log_nsamples = tmp;
Jerome Glisse961fb592010-02-10 22:30:05 +00001201 track->nsamples = 1 << tmp;
Marek Olšák3c125132012-03-19 03:09:38 +01001202 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001203 break;
Marek Olšák523885d2012-08-24 14:27:36 +02001204 case R_028808_CB_COLOR_CONTROL:
1205 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1206 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1207 track->cb_dirty = true;
1208 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001209 case R_0280A0_CB_COLOR0_INFO:
1210 case R_0280A4_CB_COLOR1_INFO:
1211 case R_0280A8_CB_COLOR2_INFO:
1212 case R_0280AC_CB_COLOR3_INFO:
1213 case R_0280B0_CB_COLOR4_INFO:
1214 case R_0280B4_CB_COLOR5_INFO:
1215 case R_0280B8_CB_COLOR6_INFO:
1216 case R_0280BC_CB_COLOR7_INFO:
Jerome Glisse721604a2012-01-05 22:11:05 -05001217 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05001218 radeon_cs_packet_next_is_pkt3_nop(p)) {
Alex Deucher7f813372010-05-20 12:43:52 -04001219 r = r600_cs_packet_next_reloc(p, &reloc);
1220 if (r) {
1221 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1222 return -EINVAL;
1223 }
1224 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1225 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1226 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1227 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1228 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1229 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1230 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1231 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1232 }
1233 } else {
1234 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1235 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1236 }
Marek Olšák3c125132012-03-19 03:09:38 +01001237 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001238 break;
Jerome Glisse285484e2011-12-16 17:03:42 -05001239 case R_028080_CB_COLOR0_VIEW:
1240 case R_028084_CB_COLOR1_VIEW:
1241 case R_028088_CB_COLOR2_VIEW:
1242 case R_02808C_CB_COLOR3_VIEW:
1243 case R_028090_CB_COLOR4_VIEW:
1244 case R_028094_CB_COLOR5_VIEW:
1245 case R_028098_CB_COLOR6_VIEW:
1246 case R_02809C_CB_COLOR7_VIEW:
1247 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1248 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
Marek Olšák3c125132012-03-19 03:09:38 +01001249 track->cb_dirty = true;
Jerome Glisse285484e2011-12-16 17:03:42 -05001250 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001251 case R_028060_CB_COLOR0_SIZE:
1252 case R_028064_CB_COLOR1_SIZE:
1253 case R_028068_CB_COLOR2_SIZE:
1254 case R_02806C_CB_COLOR3_SIZE:
1255 case R_028070_CB_COLOR4_SIZE:
1256 case R_028074_CB_COLOR5_SIZE:
1257 case R_028078_CB_COLOR6_SIZE:
1258 case R_02807C_CB_COLOR7_SIZE:
1259 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1260 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1261 track->cb_color_size_idx[tmp] = idx;
Marek Olšák3c125132012-03-19 03:09:38 +01001262 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001263 break;
1264 /* This register were added late, there is userspace
1265 * which does provide relocation for those but set
1266 * 0 offset. In order to avoid breaking old userspace
1267 * we detect this and set address to point to last
1268 * CB_COLOR0_BASE, note that if userspace doesn't set
1269 * CB_COLOR0_BASE before this register we will report
1270 * error. Old userspace always set CB_COLOR0_BASE
1271 * before any of this.
1272 */
1273 case R_0280E0_CB_COLOR0_FRAG:
1274 case R_0280E4_CB_COLOR1_FRAG:
1275 case R_0280E8_CB_COLOR2_FRAG:
1276 case R_0280EC_CB_COLOR3_FRAG:
1277 case R_0280F0_CB_COLOR4_FRAG:
1278 case R_0280F4_CB_COLOR5_FRAG:
1279 case R_0280F8_CB_COLOR6_FRAG:
1280 case R_0280FC_CB_COLOR7_FRAG:
1281 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05001282 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
Jerome Glisse961fb592010-02-10 22:30:05 +00001283 if (!track->cb_color_base_last[tmp]) {
1284 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1285 return -EINVAL;
1286 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001287 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
Marek Olšákc116cc92012-08-19 02:22:09 +02001288 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1289 ib[idx] = track->cb_color_base_last[tmp];
Jerome Glisse961fb592010-02-10 22:30:05 +00001290 } else {
1291 r = r600_cs_packet_next_reloc(p, &reloc);
1292 if (r) {
1293 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1294 return -EINVAL;
1295 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001296 track->cb_color_frag_bo[tmp] = reloc->robj;
Marek Olšákc116cc92012-08-19 02:22:09 +02001297 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1298 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1299 }
1300 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1301 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001302 }
1303 break;
1304 case R_0280C0_CB_COLOR0_TILE:
1305 case R_0280C4_CB_COLOR1_TILE:
1306 case R_0280C8_CB_COLOR2_TILE:
1307 case R_0280CC_CB_COLOR3_TILE:
1308 case R_0280D0_CB_COLOR4_TILE:
1309 case R_0280D4_CB_COLOR5_TILE:
1310 case R_0280D8_CB_COLOR6_TILE:
1311 case R_0280DC_CB_COLOR7_TILE:
1312 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05001313 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
Jerome Glisse961fb592010-02-10 22:30:05 +00001314 if (!track->cb_color_base_last[tmp]) {
1315 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1316 return -EINVAL;
1317 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001318 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
Marek Olšákc116cc92012-08-19 02:22:09 +02001319 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1320 ib[idx] = track->cb_color_base_last[tmp];
Jerome Glisse961fb592010-02-10 22:30:05 +00001321 } else {
1322 r = r600_cs_packet_next_reloc(p, &reloc);
1323 if (r) {
1324 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1325 return -EINVAL;
1326 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001327 track->cb_color_tile_bo[tmp] = reloc->robj;
Marek Olšákc116cc92012-08-19 02:22:09 +02001328 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1329 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1330 }
1331 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1332 track->cb_dirty = true;
1333 }
1334 break;
1335 case R_028100_CB_COLOR0_MASK:
1336 case R_028104_CB_COLOR1_MASK:
1337 case R_028108_CB_COLOR2_MASK:
1338 case R_02810C_CB_COLOR3_MASK:
1339 case R_028110_CB_COLOR4_MASK:
1340 case R_028114_CB_COLOR5_MASK:
1341 case R_028118_CB_COLOR6_MASK:
1342 case R_02811C_CB_COLOR7_MASK:
1343 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
Marek Olšák305a3d22012-08-22 17:02:42 +02001344 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
Marek Olšákc116cc92012-08-19 02:22:09 +02001345 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1346 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001347 }
1348 break;
1349 case CB_COLOR0_BASE:
1350 case CB_COLOR1_BASE:
1351 case CB_COLOR2_BASE:
1352 case CB_COLOR3_BASE:
1353 case CB_COLOR4_BASE:
1354 case CB_COLOR5_BASE:
1355 case CB_COLOR6_BASE:
1356 case CB_COLOR7_BASE:
1357 r = r600_cs_packet_next_reloc(p, &reloc);
1358 if (r) {
1359 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1360 "0x%04X\n", reg);
1361 return -EINVAL;
1362 }
Jerome Glisse7cb72ef2010-02-11 12:44:32 +01001363 tmp = (reg - CB_COLOR0_BASE) / 4;
Alex Deucher1729dd32010-08-06 02:54:05 -04001364 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
Jerome Glisse961fb592010-02-10 22:30:05 +00001365 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
Jerome Glisse961fb592010-02-10 22:30:05 +00001366 track->cb_color_base_last[tmp] = ib[idx];
1367 track->cb_color_bo[tmp] = reloc->robj;
Alex Deucher16790562010-11-14 20:24:35 -05001368 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
Marek Olšák3c125132012-03-19 03:09:38 +01001369 track->cb_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001370 break;
1371 case DB_DEPTH_BASE:
1372 r = r600_cs_packet_next_reloc(p, &reloc);
1373 if (r) {
1374 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1375 "0x%04X\n", reg);
1376 return -EINVAL;
1377 }
Alex Deucher1729dd32010-08-06 02:54:05 -04001378 track->db_offset = radeon_get_ib_value(p, idx) << 8;
Jerome Glisse961fb592010-02-10 22:30:05 +00001379 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1380 track->db_bo = reloc->robj;
Alex Deucher16790562010-11-14 20:24:35 -05001381 track->db_bo_mc = reloc->lobj.gpu_offset;
Marek Olšák3c125132012-03-19 03:09:38 +01001382 track->db_dirty = true;
Jerome Glisse961fb592010-02-10 22:30:05 +00001383 break;
1384 case DB_HTILE_DATA_BASE:
Jerome Glisse88f50c82012-03-21 19:18:21 -04001385 r = r600_cs_packet_next_reloc(p, &reloc);
1386 if (r) {
1387 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1388 "0x%04X\n", reg);
1389 return -EINVAL;
1390 }
1391 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1392 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1393 track->htile_bo = reloc->robj;
1394 track->db_dirty = true;
1395 break;
1396 case DB_HTILE_SURFACE:
1397 track->htile_surface = radeon_get_ib_value(p, idx);
Jerome Glisse4ac05332012-12-13 12:08:11 -05001398 /* force 8x8 htile width and height */
1399 ib[idx] |= 3;
Jerome Glisse88f50c82012-03-21 19:18:21 -04001400 track->db_dirty = true;
1401 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001402 case SQ_PGM_START_FS:
1403 case SQ_PGM_START_ES:
1404 case SQ_PGM_START_VS:
1405 case SQ_PGM_START_GS:
1406 case SQ_PGM_START_PS:
Alex Deucher5f77df32010-03-26 14:52:32 -04001407 case SQ_ALU_CONST_CACHE_GS_0:
1408 case SQ_ALU_CONST_CACHE_GS_1:
1409 case SQ_ALU_CONST_CACHE_GS_2:
1410 case SQ_ALU_CONST_CACHE_GS_3:
1411 case SQ_ALU_CONST_CACHE_GS_4:
1412 case SQ_ALU_CONST_CACHE_GS_5:
1413 case SQ_ALU_CONST_CACHE_GS_6:
1414 case SQ_ALU_CONST_CACHE_GS_7:
1415 case SQ_ALU_CONST_CACHE_GS_8:
1416 case SQ_ALU_CONST_CACHE_GS_9:
1417 case SQ_ALU_CONST_CACHE_GS_10:
1418 case SQ_ALU_CONST_CACHE_GS_11:
1419 case SQ_ALU_CONST_CACHE_GS_12:
1420 case SQ_ALU_CONST_CACHE_GS_13:
1421 case SQ_ALU_CONST_CACHE_GS_14:
1422 case SQ_ALU_CONST_CACHE_GS_15:
1423 case SQ_ALU_CONST_CACHE_PS_0:
1424 case SQ_ALU_CONST_CACHE_PS_1:
1425 case SQ_ALU_CONST_CACHE_PS_2:
1426 case SQ_ALU_CONST_CACHE_PS_3:
1427 case SQ_ALU_CONST_CACHE_PS_4:
1428 case SQ_ALU_CONST_CACHE_PS_5:
1429 case SQ_ALU_CONST_CACHE_PS_6:
1430 case SQ_ALU_CONST_CACHE_PS_7:
1431 case SQ_ALU_CONST_CACHE_PS_8:
1432 case SQ_ALU_CONST_CACHE_PS_9:
1433 case SQ_ALU_CONST_CACHE_PS_10:
1434 case SQ_ALU_CONST_CACHE_PS_11:
1435 case SQ_ALU_CONST_CACHE_PS_12:
1436 case SQ_ALU_CONST_CACHE_PS_13:
1437 case SQ_ALU_CONST_CACHE_PS_14:
1438 case SQ_ALU_CONST_CACHE_PS_15:
1439 case SQ_ALU_CONST_CACHE_VS_0:
1440 case SQ_ALU_CONST_CACHE_VS_1:
1441 case SQ_ALU_CONST_CACHE_VS_2:
1442 case SQ_ALU_CONST_CACHE_VS_3:
1443 case SQ_ALU_CONST_CACHE_VS_4:
1444 case SQ_ALU_CONST_CACHE_VS_5:
1445 case SQ_ALU_CONST_CACHE_VS_6:
1446 case SQ_ALU_CONST_CACHE_VS_7:
1447 case SQ_ALU_CONST_CACHE_VS_8:
1448 case SQ_ALU_CONST_CACHE_VS_9:
1449 case SQ_ALU_CONST_CACHE_VS_10:
1450 case SQ_ALU_CONST_CACHE_VS_11:
1451 case SQ_ALU_CONST_CACHE_VS_12:
1452 case SQ_ALU_CONST_CACHE_VS_13:
1453 case SQ_ALU_CONST_CACHE_VS_14:
1454 case SQ_ALU_CONST_CACHE_VS_15:
Jerome Glisse961fb592010-02-10 22:30:05 +00001455 r = r600_cs_packet_next_reloc(p, &reloc);
1456 if (r) {
1457 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1458 "0x%04X\n", reg);
1459 return -EINVAL;
1460 }
1461 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1462 break;
Alex Deucher033b5652011-06-08 15:26:45 -04001463 case SX_MEMORY_EXPORT_BASE:
1464 r = r600_cs_packet_next_reloc(p, &reloc);
1465 if (r) {
1466 dev_warn(p->dev, "bad SET_CONFIG_REG "
1467 "0x%04X\n", reg);
1468 return -EINVAL;
1469 }
1470 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1471 break;
Marek Olšák779923b2012-03-08 00:56:00 +01001472 case SX_MISC:
1473 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1474 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001475 default:
1476 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1477 return -EINVAL;
1478 }
1479 return 0;
1480}
1481
Jerome Glisse285484e2011-12-16 17:03:42 -05001482unsigned r600_mip_minify(unsigned size, unsigned level)
Jerome Glisse961fb592010-02-10 22:30:05 +00001483{
Dave Airlie60b212f2011-02-18 05:51:58 +00001484 unsigned val;
1485
1486 val = max(1U, size >> level);
1487 if (level > 0)
1488 val = roundup_pow_of_two(val);
1489 return val;
Jerome Glisse961fb592010-02-10 22:30:05 +00001490}
1491
Dave Airlie60b212f2011-02-18 05:51:58 +00001492static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
Marek Olšákfcdeefe2012-08-19 21:23:26 +02001493 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
Dave Airlie60b212f2011-02-18 05:51:58 +00001494 unsigned block_align, unsigned height_align, unsigned base_align,
Alex Deucher40e2a5c2010-06-04 18:41:42 -04001495 unsigned *l0_size, unsigned *mipmap_size)
Jerome Glisse961fb592010-02-10 22:30:05 +00001496{
Dave Airlie60b212f2011-02-18 05:51:58 +00001497 unsigned offset, i, level;
1498 unsigned width, height, depth, size;
1499 unsigned blocksize;
1500 unsigned nbx, nby;
1501 unsigned nlevels = llevel - blevel + 1;
Jerome Glisse961fb592010-02-10 22:30:05 +00001502
Dave Airlie60b212f2011-02-18 05:51:58 +00001503 *l0_size = -1;
Jerome Glisse285484e2011-12-16 17:03:42 -05001504 blocksize = r600_fmt_get_blocksize(format);
Dave Airlie60b212f2011-02-18 05:51:58 +00001505
Jerome Glisse285484e2011-12-16 17:03:42 -05001506 w0 = r600_mip_minify(w0, 0);
1507 h0 = r600_mip_minify(h0, 0);
1508 d0 = r600_mip_minify(d0, 0);
Jerome Glisse961fb592010-02-10 22:30:05 +00001509 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
Jerome Glisse285484e2011-12-16 17:03:42 -05001510 width = r600_mip_minify(w0, i);
1511 nbx = r600_fmt_get_nblocksx(format, width);
Dave Airlie60b212f2011-02-18 05:51:58 +00001512
1513 nbx = round_up(nbx, block_align);
1514
Jerome Glisse285484e2011-12-16 17:03:42 -05001515 height = r600_mip_minify(h0, i);
1516 nby = r600_fmt_get_nblocksy(format, height);
Dave Airlie60b212f2011-02-18 05:51:58 +00001517 nby = round_up(nby, height_align);
1518
Jerome Glisse285484e2011-12-16 17:03:42 -05001519 depth = r600_mip_minify(d0, i);
Dave Airlie60b212f2011-02-18 05:51:58 +00001520
Marek Olšákfcdeefe2012-08-19 21:23:26 +02001521 size = nbx * nby * blocksize * nsamples;
Dave Airlie60b212f2011-02-18 05:51:58 +00001522 if (nfaces)
1523 size *= nfaces;
1524 else
1525 size *= depth;
1526
1527 if (i == 0)
1528 *l0_size = size;
1529
1530 if (i == 0 || i == 1)
1531 offset = round_up(offset, base_align);
1532
1533 offset += size;
Jerome Glisse961fb592010-02-10 22:30:05 +00001534 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001535 *mipmap_size = offset;
Dave Airlie60b212f2011-02-18 05:51:58 +00001536 if (llevel == 0)
Jerome Glisse961fb592010-02-10 22:30:05 +00001537 *mipmap_size = *l0_size;
Alex Deucher1729dd32010-08-06 02:54:05 -04001538 if (!blevel)
1539 *mipmap_size -= *l0_size;
Jerome Glisse961fb592010-02-10 22:30:05 +00001540}
1541
1542/**
1543 * r600_check_texture_resource() - check if register is authorized or not
1544 * @p: parser structure holding parsing context
1545 * @idx: index into the cs buffer
1546 * @texture: texture's bo structure
1547 * @mipmap: mipmap's bo structure
1548 *
1549 * This function will check that the resource has valid field and that
1550 * the texture and mipmap bo object are big enough to cover this resource.
1551 */
Andi Kleen488479e2011-10-13 16:08:41 -07001552static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
Alex Deucher7f813372010-05-20 12:43:52 -04001553 struct radeon_bo *texture,
1554 struct radeon_bo *mipmap,
Alex Deucher16790562010-11-14 20:24:35 -05001555 u64 base_offset,
1556 u64 mip_offset,
Alex Deucher7f813372010-05-20 12:43:52 -04001557 u32 tiling_flags)
Jerome Glisse961fb592010-02-10 22:30:05 +00001558{
Alex Deucher40e2a5c2010-06-04 18:41:42 -04001559 struct r600_cs_track *track = p->track;
Marek Olšákf00245f2012-08-09 16:34:15 +02001560 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1561 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
Alex Deucher16790562010-11-14 20:24:35 -05001562 u32 height_align, pitch, pitch_align, depth_align;
Marek Olšákf00245f2012-08-09 16:34:15 +02001563 u32 barray, larray;
Alex Deucher16790562010-11-14 20:24:35 -05001564 u64 base_align;
1565 struct array_mode_checker array_check;
Dave Airlie60b212f2011-02-18 05:51:58 +00001566 u32 format;
Marek Olšákf00245f2012-08-09 16:34:15 +02001567 bool is_array;
Jerome Glisse961fb592010-02-10 22:30:05 +00001568
1569 /* on legacy kernel we don't perform advanced check */
1570 if (p->rdev == NULL)
1571 return 0;
Alex Deucher7f813372010-05-20 12:43:52 -04001572
Alex Deucher16790562010-11-14 20:24:35 -05001573 /* convert to bytes */
1574 base_offset <<= 8;
1575 mip_offset <<= 8;
1576
Jerome Glisse961fb592010-02-10 22:30:05 +00001577 word0 = radeon_get_ib_value(p, idx + 0);
Jerome Glisse721604a2012-01-05 22:11:05 -05001578 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
Marek Olšáke70f2242011-10-25 01:38:45 +02001579 if (tiling_flags & RADEON_TILING_MACRO)
1580 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1581 else if (tiling_flags & RADEON_TILING_MICRO)
1582 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1583 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001584 word1 = radeon_get_ib_value(p, idx + 1);
Marek Olšákf00245f2012-08-09 16:34:15 +02001585 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1586 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1587 word4 = radeon_get_ib_value(p, idx + 4);
1588 word5 = radeon_get_ib_value(p, idx + 5);
1589 dim = G_038000_DIM(word0);
Jerome Glisse961fb592010-02-10 22:30:05 +00001590 w0 = G_038000_TEX_WIDTH(word0) + 1;
Marek Olšákf00245f2012-08-09 16:34:15 +02001591 pitch = (G_038000_PITCH(word0) + 1) * 8;
Jerome Glisse961fb592010-02-10 22:30:05 +00001592 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1593 d0 = G_038004_TEX_DEPTH(word1);
Marek Olšákf00245f2012-08-09 16:34:15 +02001594 format = G_038004_DATA_FORMAT(word1);
1595 blevel = G_038010_BASE_LEVEL(word4);
1596 llevel = G_038014_LAST_LEVEL(word5);
1597 /* pitch in texels */
1598 array_check.array_mode = G_038000_TILE_MODE(word0);
1599 array_check.group_size = track->group_size;
1600 array_check.nbanks = track->nbanks;
1601 array_check.npipes = track->npipes;
1602 array_check.nsamples = 1;
1603 array_check.blocksize = r600_fmt_get_blocksize(format);
Jerome Glisse961fb592010-02-10 22:30:05 +00001604 nfaces = 1;
Marek Olšákf00245f2012-08-09 16:34:15 +02001605 is_array = false;
1606 switch (dim) {
Jerome Glisse961fb592010-02-10 22:30:05 +00001607 case V_038000_SQ_TEX_DIM_1D:
1608 case V_038000_SQ_TEX_DIM_2D:
1609 case V_038000_SQ_TEX_DIM_3D:
1610 break;
1611 case V_038000_SQ_TEX_DIM_CUBEMAP:
Dave Airlie60b212f2011-02-18 05:51:58 +00001612 if (p->family >= CHIP_RV770)
1613 nfaces = 8;
1614 else
1615 nfaces = 6;
Jerome Glisse961fb592010-02-10 22:30:05 +00001616 break;
1617 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1618 case V_038000_SQ_TEX_DIM_2D_ARRAY:
Marek Olšákf00245f2012-08-09 16:34:15 +02001619 is_array = true;
Dave Airlie60b212f2011-02-18 05:51:58 +00001620 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001621 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
Marek Olšákb51ad122012-08-09 16:34:16 +02001622 is_array = true;
1623 /* fall through */
1624 case V_038000_SQ_TEX_DIM_2D_MSAA:
1625 array_check.nsamples = 1 << llevel;
1626 llevel = 0;
1627 break;
Jerome Glisse961fb592010-02-10 22:30:05 +00001628 default:
1629 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1630 return -EINVAL;
1631 }
Jerome Glisse285484e2011-12-16 17:03:42 -05001632 if (!r600_fmt_is_valid_texture(format, p->family)) {
Jerome Glisse961fb592010-02-10 22:30:05 +00001633 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
Dave Airlie60b212f2011-02-18 05:51:58 +00001634 __func__, __LINE__, format);
Jerome Glisse961fb592010-02-10 22:30:05 +00001635 return -EINVAL;
1636 }
Alex Deucher40e2a5c2010-06-04 18:41:42 -04001637
Alex Deucher16790562010-11-14 20:24:35 -05001638 if (r600_get_array_mode_alignment(&array_check,
1639 &pitch_align, &height_align, &depth_align, &base_align)) {
1640 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1641 __func__, __LINE__, G_038000_TILE_MODE(word0));
Alex Deucher40e2a5c2010-06-04 18:41:42 -04001642 return -EINVAL;
1643 }
Alex Deucher16790562010-11-14 20:24:35 -05001644
1645 /* XXX check height as well... */
1646
1647 if (!IS_ALIGNED(pitch, pitch_align)) {
Alex Deucherc2049b32011-02-13 18:42:41 -05001648 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1649 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
Alex Deucher16790562010-11-14 20:24:35 -05001650 return -EINVAL;
1651 }
1652 if (!IS_ALIGNED(base_offset, base_align)) {
Alex Deucherc2049b32011-02-13 18:42:41 -05001653 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1654 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
Alex Deucher16790562010-11-14 20:24:35 -05001655 return -EINVAL;
1656 }
1657 if (!IS_ALIGNED(mip_offset, base_align)) {
Alex Deucherc2049b32011-02-13 18:42:41 -05001658 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1659 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
Alex Deucher16790562010-11-14 20:24:35 -05001660 return -EINVAL;
1661 }
Alex Deucher40e2a5c2010-06-04 18:41:42 -04001662
Jerome Glisse285484e2011-12-16 17:03:42 -05001663 if (blevel > llevel) {
1664 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1665 blevel, llevel);
1666 }
Marek Olšákf00245f2012-08-09 16:34:15 +02001667 if (is_array) {
1668 barray = G_038014_BASE_ARRAY(word5);
1669 larray = G_038014_LAST_ARRAY(word5);
Dave Airlie60b212f2011-02-18 05:51:58 +00001670
1671 nfaces = larray - barray + 1;
1672 }
Marek Olšákfcdeefe2012-08-19 21:23:26 +02001673 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
Dave Airlie60b212f2011-02-18 05:51:58 +00001674 pitch_align, height_align, base_align,
Alex Deucher40e2a5c2010-06-04 18:41:42 -04001675 &l0_size, &mipmap_size);
Jerome Glisse961fb592010-02-10 22:30:05 +00001676 /* using get ib will give us the offset into the texture bo */
Dave Airlieaf506212011-02-28 14:27:03 +10001677 if ((l0_size + word2) > radeon_bo_size(texture)) {
Jerome Glisse285484e2011-12-16 17:03:42 -05001678 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1679 w0, h0, pitch_align, height_align,
1680 array_check.array_mode, format, word2,
1681 l0_size, radeon_bo_size(texture));
Dave Airlie60b212f2011-02-18 05:51:58 +00001682 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
Jerome Glisse961fb592010-02-10 22:30:05 +00001683 return -EINVAL;
1684 }
1685 /* using get ib will give us the offset into the mipmap bo */
Dave Airlieaf506212011-02-28 14:27:03 +10001686 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
Alex Deucherfe725d42010-09-14 10:10:47 -04001687 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
Dave Airlieaf506212011-02-28 14:27:03 +10001688 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
Jerome Glisse961fb592010-02-10 22:30:05 +00001689 }
1690 return 0;
1691}
1692
Marek Olšákdd220a02012-01-27 12:17:59 -05001693static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1694{
1695 u32 m, i;
1696
1697 i = (reg >> 7);
1698 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1699 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1700 return false;
1701 }
1702 m = 1 << ((reg >> 2) & 31);
1703 if (!(r600_reg_safe_bm[i] & m))
1704 return true;
1705 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1706 return false;
1707}
1708
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001709static int r600_packet3_check(struct radeon_cs_parser *p,
1710 struct radeon_cs_packet *pkt)
1711{
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001712 struct radeon_cs_reloc *reloc;
Jerome Glissec8c15ff2010-01-18 13:01:36 +01001713 struct r600_cs_track *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001714 volatile u32 *ib;
1715 unsigned idx;
1716 unsigned i;
1717 unsigned start_reg, end_reg, reg;
1718 int r;
Dave Airlieadea4792009-09-25 14:23:47 +10001719 u32 idx_value;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001720
Jerome Glissec8c15ff2010-01-18 13:01:36 +01001721 track = (struct r600_cs_track *)p->track;
Jerome Glissef2e39222012-05-09 15:35:02 +02001722 ib = p->ib.ptr;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001723 idx = pkt->idx + 1;
Dave Airlieadea4792009-09-25 14:23:47 +10001724 idx_value = radeon_get_ib_value(p, idx);
Dave Airlie513bcb42009-09-23 16:56:27 +10001725
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001726 switch (pkt->opcode) {
Dave Airlie2a19cac2011-02-28 16:11:48 +10001727 case PACKET3_SET_PREDICATION:
1728 {
1729 int pred_op;
1730 int tmp;
Marek Olšák63330032012-03-19 03:09:37 +01001731 uint64_t offset;
1732
Dave Airlie2a19cac2011-02-28 16:11:48 +10001733 if (pkt->count != 1) {
1734 DRM_ERROR("bad SET PREDICATION\n");
1735 return -EINVAL;
1736 }
1737
1738 tmp = radeon_get_ib_value(p, idx + 1);
1739 pred_op = (tmp >> 16) & 0x7;
1740
1741 /* for the clear predicate operation */
1742 if (pred_op == 0)
1743 return 0;
1744
1745 if (pred_op > 2) {
1746 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1747 return -EINVAL;
1748 }
1749
1750 r = r600_cs_packet_next_reloc(p, &reloc);
1751 if (r) {
1752 DRM_ERROR("bad SET PREDICATION\n");
1753 return -EINVAL;
1754 }
1755
Marek Olšák63330032012-03-19 03:09:37 +01001756 offset = reloc->lobj.gpu_offset +
1757 (idx_value & 0xfffffff0) +
1758 ((u64)(tmp & 0xff) << 32);
1759
1760 ib[idx + 0] = offset;
1761 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
Dave Airlie2a19cac2011-02-28 16:11:48 +10001762 }
1763 break;
1764
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001765 case PACKET3_START_3D_CMDBUF:
1766 if (p->family >= CHIP_RV770 || pkt->count) {
1767 DRM_ERROR("bad START_3D\n");
1768 return -EINVAL;
1769 }
1770 break;
1771 case PACKET3_CONTEXT_CONTROL:
1772 if (pkt->count != 1) {
1773 DRM_ERROR("bad CONTEXT_CONTROL\n");
1774 return -EINVAL;
1775 }
1776 break;
1777 case PACKET3_INDEX_TYPE:
1778 case PACKET3_NUM_INSTANCES:
1779 if (pkt->count) {
1780 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1781 return -EINVAL;
1782 }
1783 break;
1784 case PACKET3_DRAW_INDEX:
Marek Olšák63330032012-03-19 03:09:37 +01001785 {
1786 uint64_t offset;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001787 if (pkt->count != 3) {
1788 DRM_ERROR("bad DRAW_INDEX\n");
1789 return -EINVAL;
1790 }
1791 r = r600_cs_packet_next_reloc(p, &reloc);
1792 if (r) {
1793 DRM_ERROR("bad DRAW_INDEX\n");
1794 return -EINVAL;
1795 }
Marek Olšák63330032012-03-19 03:09:37 +01001796
1797 offset = reloc->lobj.gpu_offset +
1798 idx_value +
1799 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1800
1801 ib[idx+0] = offset;
1802 ib[idx+1] = upper_32_bits(offset) & 0xff;
1803
Jerome Glisse961fb592010-02-10 22:30:05 +00001804 r = r600_cs_track_check(p);
1805 if (r) {
1806 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1807 return r;
1808 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001809 break;
Marek Olšák63330032012-03-19 03:09:37 +01001810 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001811 case PACKET3_DRAW_INDEX_AUTO:
1812 if (pkt->count != 1) {
1813 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1814 return -EINVAL;
1815 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001816 r = r600_cs_track_check(p);
1817 if (r) {
1818 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1819 return r;
1820 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001821 break;
1822 case PACKET3_DRAW_INDEX_IMMD_BE:
1823 case PACKET3_DRAW_INDEX_IMMD:
1824 if (pkt->count < 2) {
1825 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1826 return -EINVAL;
1827 }
Jerome Glisse961fb592010-02-10 22:30:05 +00001828 r = r600_cs_track_check(p);
1829 if (r) {
1830 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1831 return r;
1832 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001833 break;
1834 case PACKET3_WAIT_REG_MEM:
1835 if (pkt->count != 5) {
1836 DRM_ERROR("bad WAIT_REG_MEM\n");
1837 return -EINVAL;
1838 }
1839 /* bit 4 is reg (0) or mem (1) */
Dave Airlieadea4792009-09-25 14:23:47 +10001840 if (idx_value & 0x10) {
Marek Olšák63330032012-03-19 03:09:37 +01001841 uint64_t offset;
1842
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001843 r = r600_cs_packet_next_reloc(p, &reloc);
1844 if (r) {
1845 DRM_ERROR("bad WAIT_REG_MEM\n");
1846 return -EINVAL;
1847 }
Marek Olšák63330032012-03-19 03:09:37 +01001848
1849 offset = reloc->lobj.gpu_offset +
1850 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1851 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1852
1853 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1854 ib[idx+2] = upper_32_bits(offset) & 0xff;
Ilija Hadzicd6e18a32013-01-02 18:27:44 -05001855 } else if (idx_value & 0x100) {
1856 DRM_ERROR("cannot use PFP on REG wait\n");
1857 return -EINVAL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001858 }
1859 break;
Alex Deucher6830f582012-12-03 19:03:23 -05001860 case PACKET3_CP_DMA:
1861 {
1862 u32 command, size;
1863 u64 offset, tmp;
1864 if (pkt->count != 4) {
1865 DRM_ERROR("bad CP DMA\n");
1866 return -EINVAL;
1867 }
1868 command = radeon_get_ib_value(p, idx+4);
1869 size = command & 0x1fffff;
1870 if (command & PACKET3_CP_DMA_CMD_SAS) {
1871 /* src address space is register */
1872 DRM_ERROR("CP DMA SAS not supported\n");
1873 return -EINVAL;
1874 } else {
1875 if (command & PACKET3_CP_DMA_CMD_SAIC) {
1876 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1877 return -EINVAL;
1878 }
1879 /* src address space is memory */
1880 r = r600_cs_packet_next_reloc(p, &reloc);
1881 if (r) {
1882 DRM_ERROR("bad CP DMA SRC\n");
1883 return -EINVAL;
1884 }
1885
1886 tmp = radeon_get_ib_value(p, idx) +
1887 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1888
1889 offset = reloc->lobj.gpu_offset + tmp;
1890
1891 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1892 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
1893 tmp + size, radeon_bo_size(reloc->robj));
1894 return -EINVAL;
1895 }
1896
1897 ib[idx] = offset;
1898 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1899 }
1900 if (command & PACKET3_CP_DMA_CMD_DAS) {
1901 /* dst address space is register */
1902 DRM_ERROR("CP DMA DAS not supported\n");
1903 return -EINVAL;
1904 } else {
1905 /* dst address space is memory */
1906 if (command & PACKET3_CP_DMA_CMD_DAIC) {
1907 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1908 return -EINVAL;
1909 }
1910 r = r600_cs_packet_next_reloc(p, &reloc);
1911 if (r) {
1912 DRM_ERROR("bad CP DMA DST\n");
1913 return -EINVAL;
1914 }
1915
1916 tmp = radeon_get_ib_value(p, idx+2) +
1917 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1918
1919 offset = reloc->lobj.gpu_offset + tmp;
1920
1921 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1922 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
1923 tmp + size, radeon_bo_size(reloc->robj));
1924 return -EINVAL;
1925 }
1926
1927 ib[idx+2] = offset;
1928 ib[idx+3] = upper_32_bits(offset) & 0xff;
1929 }
1930 break;
1931 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001932 case PACKET3_SURFACE_SYNC:
1933 if (pkt->count != 3) {
1934 DRM_ERROR("bad SURFACE_SYNC\n");
1935 return -EINVAL;
1936 }
1937 /* 0xffffffff/0x0 is flush all cache flag */
Dave Airlie513bcb42009-09-23 16:56:27 +10001938 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1939 radeon_get_ib_value(p, idx + 2) != 0) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001940 r = r600_cs_packet_next_reloc(p, &reloc);
1941 if (r) {
1942 DRM_ERROR("bad SURFACE_SYNC\n");
1943 return -EINVAL;
1944 }
1945 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1946 }
1947 break;
1948 case PACKET3_EVENT_WRITE:
1949 if (pkt->count != 2 && pkt->count != 0) {
1950 DRM_ERROR("bad EVENT_WRITE\n");
1951 return -EINVAL;
1952 }
1953 if (pkt->count) {
Marek Olšák63330032012-03-19 03:09:37 +01001954 uint64_t offset;
1955
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001956 r = r600_cs_packet_next_reloc(p, &reloc);
1957 if (r) {
1958 DRM_ERROR("bad EVENT_WRITE\n");
1959 return -EINVAL;
1960 }
Marek Olšák63330032012-03-19 03:09:37 +01001961 offset = reloc->lobj.gpu_offset +
1962 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1963 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1964
1965 ib[idx+1] = offset & 0xfffffff8;
1966 ib[idx+2] = upper_32_bits(offset) & 0xff;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001967 }
1968 break;
1969 case PACKET3_EVENT_WRITE_EOP:
Marek Olšák63330032012-03-19 03:09:37 +01001970 {
1971 uint64_t offset;
1972
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001973 if (pkt->count != 4) {
1974 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1975 return -EINVAL;
1976 }
1977 r = r600_cs_packet_next_reloc(p, &reloc);
1978 if (r) {
1979 DRM_ERROR("bad EVENT_WRITE\n");
1980 return -EINVAL;
1981 }
Marek Olšák63330032012-03-19 03:09:37 +01001982
1983 offset = reloc->lobj.gpu_offset +
1984 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1985 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1986
1987 ib[idx+1] = offset & 0xfffffffc;
1988 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001989 break;
Marek Olšák63330032012-03-19 03:09:37 +01001990 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001991 case PACKET3_SET_CONFIG_REG:
Dave Airlieadea4792009-09-25 14:23:47 +10001992 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001993 end_reg = 4 * pkt->count + start_reg - 4;
1994 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1995 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1996 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1997 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1998 return -EINVAL;
1999 }
2000 for (i = 0; i < pkt->count; i++) {
2001 reg = start_reg + (4 * i);
Jerome Glisse961fb592010-02-10 22:30:05 +00002002 r = r600_cs_check_reg(p, reg, idx+1+i);
2003 if (r)
2004 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002005 }
2006 break;
2007 case PACKET3_SET_CONTEXT_REG:
Dave Airlieadea4792009-09-25 14:23:47 +10002008 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002009 end_reg = 4 * pkt->count + start_reg - 4;
2010 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
2011 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2012 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2013 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2014 return -EINVAL;
2015 }
2016 for (i = 0; i < pkt->count; i++) {
2017 reg = start_reg + (4 * i);
Jerome Glisse961fb592010-02-10 22:30:05 +00002018 r = r600_cs_check_reg(p, reg, idx+1+i);
2019 if (r)
2020 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002021 }
2022 break;
2023 case PACKET3_SET_RESOURCE:
2024 if (pkt->count % 7) {
2025 DRM_ERROR("bad SET_RESOURCE\n");
2026 return -EINVAL;
2027 }
Dave Airlieadea4792009-09-25 14:23:47 +10002028 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002029 end_reg = 4 * pkt->count + start_reg - 4;
2030 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2031 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2032 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2033 DRM_ERROR("bad SET_RESOURCE\n");
2034 return -EINVAL;
2035 }
2036 for (i = 0; i < (pkt->count / 7); i++) {
Jerome Glisse961fb592010-02-10 22:30:05 +00002037 struct radeon_bo *texture, *mipmap;
Alex Deucher1729dd32010-08-06 02:54:05 -04002038 u32 size, offset, base_offset, mip_offset;
Jerome Glisse961fb592010-02-10 22:30:05 +00002039
Dave Airlieadea4792009-09-25 14:23:47 +10002040 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002041 case SQ_TEX_VTX_VALID_TEXTURE:
2042 /* tex base */
2043 r = r600_cs_packet_next_reloc(p, &reloc);
2044 if (r) {
2045 DRM_ERROR("bad SET_RESOURCE\n");
2046 return -EINVAL;
2047 }
Alex Deucher1729dd32010-08-06 02:54:05 -04002048 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
Jerome Glisse721604a2012-01-05 22:11:05 -05002049 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
Marek Olšáke70f2242011-10-25 01:38:45 +02002050 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2051 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2052 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2053 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2054 }
Jerome Glisse961fb592010-02-10 22:30:05 +00002055 texture = reloc->robj;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002056 /* tex mip base */
2057 r = r600_cs_packet_next_reloc(p, &reloc);
2058 if (r) {
2059 DRM_ERROR("bad SET_RESOURCE\n");
2060 return -EINVAL;
2061 }
Alex Deucher1729dd32010-08-06 02:54:05 -04002062 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
Jerome Glisse961fb592010-02-10 22:30:05 +00002063 mipmap = reloc->robj;
2064 r = r600_check_texture_resource(p, idx+(i*7)+1,
Alex Deucher16790562010-11-14 20:24:35 -05002065 texture, mipmap,
2066 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2067 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2068 reloc->lobj.tiling_flags);
Jerome Glisse961fb592010-02-10 22:30:05 +00002069 if (r)
2070 return r;
Alex Deucher1729dd32010-08-06 02:54:05 -04002071 ib[idx+1+(i*7)+2] += base_offset;
2072 ib[idx+1+(i*7)+3] += mip_offset;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002073 break;
2074 case SQ_TEX_VTX_VALID_BUFFER:
Marek Olšák63330032012-03-19 03:09:37 +01002075 {
2076 uint64_t offset64;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002077 /* vtx base */
2078 r = r600_cs_packet_next_reloc(p, &reloc);
2079 if (r) {
2080 DRM_ERROR("bad SET_RESOURCE\n");
2081 return -EINVAL;
2082 }
Jerome Glisse961fb592010-02-10 22:30:05 +00002083 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
Alex Deucher1729dd32010-08-06 02:54:05 -04002084 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
Jerome Glisse961fb592010-02-10 22:30:05 +00002085 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2086 /* force size to size of the buffer */
Alex Deucher1729dd32010-08-06 02:54:05 -04002087 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2088 size + offset, radeon_bo_size(reloc->robj));
Marek Olšák63330032012-03-19 03:09:37 +01002089 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
Jerome Glisse961fb592010-02-10 22:30:05 +00002090 }
Marek Olšák63330032012-03-19 03:09:37 +01002091
2092 offset64 = reloc->lobj.gpu_offset + offset;
2093 ib[idx+1+(i*8)+0] = offset64;
2094 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2095 (upper_32_bits(offset64) & 0xff);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002096 break;
Marek Olšák63330032012-03-19 03:09:37 +01002097 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002098 case SQ_TEX_VTX_INVALID_TEXTURE:
2099 case SQ_TEX_VTX_INVALID_BUFFER:
2100 default:
2101 DRM_ERROR("bad SET_RESOURCE\n");
2102 return -EINVAL;
2103 }
2104 }
2105 break;
2106 case PACKET3_SET_ALU_CONST:
Alex Deucher5f77df32010-03-26 14:52:32 -04002107 if (track->sq_config & DX9_CONSTS) {
2108 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2109 end_reg = 4 * pkt->count + start_reg - 4;
2110 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2111 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2112 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2113 DRM_ERROR("bad SET_ALU_CONST\n");
2114 return -EINVAL;
2115 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002116 }
2117 break;
2118 case PACKET3_SET_BOOL_CONST:
Dave Airlieadea4792009-09-25 14:23:47 +10002119 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002120 end_reg = 4 * pkt->count + start_reg - 4;
2121 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2122 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2123 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2124 DRM_ERROR("bad SET_BOOL_CONST\n");
2125 return -EINVAL;
2126 }
2127 break;
2128 case PACKET3_SET_LOOP_CONST:
Dave Airlieadea4792009-09-25 14:23:47 +10002129 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002130 end_reg = 4 * pkt->count + start_reg - 4;
2131 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2132 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2133 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2134 DRM_ERROR("bad SET_LOOP_CONST\n");
2135 return -EINVAL;
2136 }
2137 break;
2138 case PACKET3_SET_CTL_CONST:
Dave Airlieadea4792009-09-25 14:23:47 +10002139 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002140 end_reg = 4 * pkt->count + start_reg - 4;
2141 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2142 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2143 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2144 DRM_ERROR("bad SET_CTL_CONST\n");
2145 return -EINVAL;
2146 }
2147 break;
2148 case PACKET3_SET_SAMPLER:
2149 if (pkt->count % 3) {
2150 DRM_ERROR("bad SET_SAMPLER\n");
2151 return -EINVAL;
2152 }
Dave Airlieadea4792009-09-25 14:23:47 +10002153 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002154 end_reg = 4 * pkt->count + start_reg - 4;
2155 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2156 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2157 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2158 DRM_ERROR("bad SET_SAMPLER\n");
2159 return -EINVAL;
2160 }
2161 break;
Alex Deucher7c77bf22012-06-14 22:06:37 +02002162 case PACKET3_STRMOUT_BASE_UPDATE:
Marek Olšák46fc8782012-09-25 01:45:33 +02002163 /* RS780 and RS880 also need this */
2164 if (p->family < CHIP_RS780) {
Alex Deucher7c77bf22012-06-14 22:06:37 +02002165 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2166 return -EINVAL;
2167 }
2168 if (pkt->count != 1) {
2169 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2170 return -EINVAL;
2171 }
2172 if (idx_value > 3) {
2173 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2174 return -EINVAL;
2175 }
2176 {
2177 u64 offset;
2178
2179 r = r600_cs_packet_next_reloc(p, &reloc);
2180 if (r) {
2181 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2182 return -EINVAL;
2183 }
2184
2185 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2186 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2187 return -EINVAL;
2188 }
2189
2190 offset = radeon_get_ib_value(p, idx+1) << 8;
2191 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2192 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2193 offset, track->vgt_strmout_bo_offset[idx_value]);
2194 return -EINVAL;
2195 }
2196
2197 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2198 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2199 offset + 4, radeon_bo_size(reloc->robj));
2200 return -EINVAL;
2201 }
2202 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2203 }
2204 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002205 case PACKET3_SURFACE_BASE_UPDATE:
2206 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2207 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2208 return -EINVAL;
2209 }
2210 if (pkt->count) {
2211 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2212 return -EINVAL;
2213 }
2214 break;
Marek Olšákdd220a02012-01-27 12:17:59 -05002215 case PACKET3_STRMOUT_BUFFER_UPDATE:
2216 if (pkt->count != 4) {
2217 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2218 return -EINVAL;
2219 }
2220 /* Updating memory at DST_ADDRESS. */
2221 if (idx_value & 0x1) {
2222 u64 offset;
2223 r = r600_cs_packet_next_reloc(p, &reloc);
2224 if (r) {
2225 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2226 return -EINVAL;
2227 }
2228 offset = radeon_get_ib_value(p, idx+1);
2229 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2230 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2231 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2232 offset + 4, radeon_bo_size(reloc->robj));
2233 return -EINVAL;
2234 }
Marek Olšák63330032012-03-19 03:09:37 +01002235 offset += reloc->lobj.gpu_offset;
2236 ib[idx+1] = offset;
2237 ib[idx+2] = upper_32_bits(offset) & 0xff;
Marek Olšákdd220a02012-01-27 12:17:59 -05002238 }
2239 /* Reading data from SRC_ADDRESS. */
2240 if (((idx_value >> 1) & 0x3) == 2) {
2241 u64 offset;
2242 r = r600_cs_packet_next_reloc(p, &reloc);
2243 if (r) {
2244 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2245 return -EINVAL;
2246 }
2247 offset = radeon_get_ib_value(p, idx+3);
2248 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2249 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2250 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2251 offset + 4, radeon_bo_size(reloc->robj));
2252 return -EINVAL;
2253 }
Marek Olšák63330032012-03-19 03:09:37 +01002254 offset += reloc->lobj.gpu_offset;
2255 ib[idx+3] = offset;
2256 ib[idx+4] = upper_32_bits(offset) & 0xff;
Marek Olšákdd220a02012-01-27 12:17:59 -05002257 }
2258 break;
Jerome Glisse4613ca12012-12-19 12:26:45 -05002259 case PACKET3_MEM_WRITE:
2260 {
2261 u64 offset;
2262
2263 if (pkt->count != 3) {
2264 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2265 return -EINVAL;
2266 }
2267 r = r600_cs_packet_next_reloc(p, &reloc);
2268 if (r) {
2269 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2270 return -EINVAL;
2271 }
2272 offset = radeon_get_ib_value(p, idx+0);
2273 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2274 if (offset & 0x7) {
2275 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2276 return -EINVAL;
2277 }
2278 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2279 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2280 offset + 8, radeon_bo_size(reloc->robj));
2281 return -EINVAL;
2282 }
2283 offset += reloc->lobj.gpu_offset;
2284 ib[idx+0] = offset;
2285 ib[idx+1] = upper_32_bits(offset) & 0xff;
2286 break;
2287 }
Marek Olšákdd220a02012-01-27 12:17:59 -05002288 case PACKET3_COPY_DW:
2289 if (pkt->count != 4) {
2290 DRM_ERROR("bad COPY_DW (invalid count)\n");
2291 return -EINVAL;
2292 }
2293 if (idx_value & 0x1) {
2294 u64 offset;
2295 /* SRC is memory. */
2296 r = r600_cs_packet_next_reloc(p, &reloc);
2297 if (r) {
2298 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2299 return -EINVAL;
2300 }
2301 offset = radeon_get_ib_value(p, idx+1);
2302 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2303 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2304 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2305 offset + 4, radeon_bo_size(reloc->robj));
2306 return -EINVAL;
2307 }
Marek Olšák63330032012-03-19 03:09:37 +01002308 offset += reloc->lobj.gpu_offset;
2309 ib[idx+1] = offset;
2310 ib[idx+2] = upper_32_bits(offset) & 0xff;
Marek Olšákdd220a02012-01-27 12:17:59 -05002311 } else {
2312 /* SRC is a reg. */
2313 reg = radeon_get_ib_value(p, idx+1) << 2;
2314 if (!r600_is_safe_reg(p, reg, idx+1))
2315 return -EINVAL;
2316 }
2317 if (idx_value & 0x2) {
2318 u64 offset;
2319 /* DST is memory. */
2320 r = r600_cs_packet_next_reloc(p, &reloc);
2321 if (r) {
2322 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2323 return -EINVAL;
2324 }
2325 offset = radeon_get_ib_value(p, idx+3);
2326 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2327 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2328 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2329 offset + 4, radeon_bo_size(reloc->robj));
2330 return -EINVAL;
2331 }
Marek Olšák63330032012-03-19 03:09:37 +01002332 offset += reloc->lobj.gpu_offset;
2333 ib[idx+3] = offset;
2334 ib[idx+4] = upper_32_bits(offset) & 0xff;
Marek Olšákdd220a02012-01-27 12:17:59 -05002335 } else {
2336 /* DST is a reg. */
2337 reg = radeon_get_ib_value(p, idx+3) << 2;
2338 if (!r600_is_safe_reg(p, reg, idx+3))
2339 return -EINVAL;
2340 }
2341 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002342 case PACKET3_NOP:
2343 break;
2344 default:
2345 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2346 return -EINVAL;
2347 }
2348 return 0;
2349}
2350
2351int r600_cs_parse(struct radeon_cs_parser *p)
2352{
2353 struct radeon_cs_packet pkt;
Jerome Glissec8c15ff2010-01-18 13:01:36 +01002354 struct r600_cs_track *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002355 int r;
2356
Jerome Glisse961fb592010-02-10 22:30:05 +00002357 if (p->track == NULL) {
2358 /* initialize tracker, we are in kms */
2359 track = kzalloc(sizeof(*track), GFP_KERNEL);
2360 if (track == NULL)
2361 return -ENOMEM;
2362 r600_cs_track_init(track);
2363 if (p->rdev->family < CHIP_RV770) {
2364 track->npipes = p->rdev->config.r600.tiling_npipes;
2365 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2366 track->group_size = p->rdev->config.r600.tiling_group_size;
2367 } else if (p->rdev->family <= CHIP_RV740) {
2368 track->npipes = p->rdev->config.rv770.tiling_npipes;
2369 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2370 track->group_size = p->rdev->config.rv770.tiling_group_size;
2371 }
2372 p->track = track;
2373 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002374 do {
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05002375 r = radeon_cs_packet_parse(p, &pkt, p->idx);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002376 if (r) {
Jerome Glisse7cb72ef2010-02-11 12:44:32 +01002377 kfree(p->track);
2378 p->track = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002379 return r;
2380 }
2381 p->idx += pkt.count + 2;
2382 switch (pkt.type) {
2383 case PACKET_TYPE0:
2384 r = r600_cs_parse_packet0(p, &pkt);
2385 break;
2386 case PACKET_TYPE2:
2387 break;
2388 case PACKET_TYPE3:
2389 r = r600_packet3_check(p, &pkt);
2390 break;
2391 default:
2392 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
Jerome Glisse961fb592010-02-10 22:30:05 +00002393 kfree(p->track);
Jerome Glisse7cb72ef2010-02-11 12:44:32 +01002394 p->track = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002395 return -EINVAL;
2396 }
2397 if (r) {
Jerome Glisse961fb592010-02-10 22:30:05 +00002398 kfree(p->track);
Jerome Glisse7cb72ef2010-02-11 12:44:32 +01002399 p->track = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002400 return r;
2401 }
2402 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2403#if 0
Jerome Glissef2e39222012-05-09 15:35:02 +02002404 for (r = 0; r < p->ib.length_dw; r++) {
2405 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002406 mdelay(1);
2407 }
2408#endif
Jerome Glisse961fb592010-02-10 22:30:05 +00002409 kfree(p->track);
Jerome Glisse7cb72ef2010-02-11 12:44:32 +01002410 p->track = NULL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002411 return 0;
2412}
2413
2414static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2415{
2416 if (p->chunk_relocs_idx == -1) {
2417 return 0;
2418 }
Julia Lawalle265f39e2009-12-19 08:16:33 +01002419 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002420 if (p->relocs == NULL) {
2421 return -ENOMEM;
2422 }
2423 return 0;
2424}
2425
2426/**
2427 * cs_parser_fini() - clean parser states
2428 * @parser: parser structure holding parsing context.
2429 * @error: error number
2430 *
2431 * If error is set than unvalidate buffer, otherwise just free memory
2432 * used by parsing context.
2433 **/
2434static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2435{
2436 unsigned i;
2437
2438 kfree(parser->relocs);
2439 for (i = 0; i < parser->nchunks; i++) {
2440 kfree(parser->chunks[i].kdata);
Ilija Hadzica6b7e1a2013-01-07 18:21:58 -05002441 if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
2442 kfree(parser->chunks[i].kpage[0]);
2443 kfree(parser->chunks[i].kpage[1]);
2444 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002445 }
2446 kfree(parser->chunks);
2447 kfree(parser->chunks_array);
2448}
2449
2450int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2451 unsigned family, u32 *ib, int *l)
2452{
2453 struct radeon_cs_parser parser;
2454 struct radeon_cs_chunk *ib_chunk;
Jerome Glisse961fb592010-02-10 22:30:05 +00002455 struct r600_cs_track *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002456 int r;
2457
Jerome Glisse961fb592010-02-10 22:30:05 +00002458 /* initialize tracker */
2459 track = kzalloc(sizeof(*track), GFP_KERNEL);
2460 if (track == NULL)
2461 return -ENOMEM;
2462 r600_cs_track_init(track);
2463 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002464 /* initialize parser */
2465 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2466 parser.filp = filp;
Jerome Glissec8c15ff2010-01-18 13:01:36 +01002467 parser.dev = &dev->pdev->dev;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002468 parser.rdev = NULL;
2469 parser.family = family;
Jerome Glisse961fb592010-02-10 22:30:05 +00002470 parser.track = track;
Jerome Glissef2e39222012-05-09 15:35:02 +02002471 parser.ib.ptr = ib;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002472 r = radeon_cs_parser_init(&parser, data);
2473 if (r) {
2474 DRM_ERROR("Failed to initialize parser !\n");
2475 r600_cs_parser_fini(&parser, r);
2476 return r;
2477 }
2478 r = r600_cs_parser_relocs_legacy(&parser);
2479 if (r) {
2480 DRM_ERROR("Failed to parse relocation !\n");
2481 r600_cs_parser_fini(&parser, r);
2482 return r;
2483 }
2484 /* Copy the packet into the IB, the parser will read from the
2485 * input memory (cached) and write to the IB (which can be
2486 * uncached). */
2487 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
Jerome Glissef2e39222012-05-09 15:35:02 +02002488 parser.ib.length_dw = ib_chunk->length_dw;
2489 *l = parser.ib.length_dw;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002490 r = r600_cs_parse(&parser);
2491 if (r) {
2492 DRM_ERROR("Invalid command stream !\n");
2493 r600_cs_parser_fini(&parser, r);
2494 return r;
2495 }
Dave Airlie513bcb42009-09-23 16:56:27 +10002496 r = radeon_cs_finish_pages(&parser);
2497 if (r) {
2498 DRM_ERROR("Invalid command stream !\n");
2499 r600_cs_parser_fini(&parser, r);
2500 return r;
2501 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002502 r600_cs_parser_fini(&parser, r);
2503 return r;
2504}
2505
2506void r600_cs_legacy_init(void)
2507{
2508 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2509}
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002510
2511/*
2512 * DMA
2513 */
2514/**
2515 * r600_dma_cs_next_reloc() - parse next reloc
2516 * @p: parser structure holding parsing context.
2517 * @cs_reloc: reloc informations
2518 *
2519 * Return the next reloc, do bo validation and compute
2520 * GPU offset using the provided start.
2521 **/
2522int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
2523 struct radeon_cs_reloc **cs_reloc)
2524{
2525 struct radeon_cs_chunk *relocs_chunk;
2526 unsigned idx;
2527
Jerome Glisse9305ede2013-01-09 16:40:42 -05002528 *cs_reloc = NULL;
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002529 if (p->chunk_relocs_idx == -1) {
2530 DRM_ERROR("No relocation chunk !\n");
2531 return -EINVAL;
2532 }
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002533 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
2534 idx = p->dma_reloc_idx;
Jerome Glisse9305ede2013-01-09 16:40:42 -05002535 if (idx >= p->nrelocs) {
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002536 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
Jerome Glisse9305ede2013-01-09 16:40:42 -05002537 idx, p->nrelocs);
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002538 return -EINVAL;
2539 }
2540 *cs_reloc = p->relocs_ptr[idx];
2541 p->dma_reloc_idx++;
2542 return 0;
2543}
2544
2545#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2546#define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2547#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2548
2549/**
2550 * r600_dma_cs_parse() - parse the DMA IB
2551 * @p: parser structure holding parsing context.
2552 *
2553 * Parses the DMA IB from the CS ioctl and updates
2554 * the GPU addresses based on the reloc information and
2555 * checks for errors. (R6xx-R7xx)
2556 * Returns 0 for success and an error on failure.
2557 **/
2558int r600_dma_cs_parse(struct radeon_cs_parser *p)
2559{
2560 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
2561 struct radeon_cs_reloc *src_reloc, *dst_reloc;
2562 u32 header, cmd, count, tiled;
2563 volatile u32 *ib = p->ib.ptr;
2564 u32 idx, idx_value;
2565 u64 src_offset, dst_offset;
2566 int r;
2567
2568 do {
2569 if (p->idx >= ib_chunk->length_dw) {
2570 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2571 p->idx, ib_chunk->length_dw);
2572 return -EINVAL;
2573 }
2574 idx = p->idx;
2575 header = radeon_get_ib_value(p, idx);
2576 cmd = GET_DMA_CMD(header);
2577 count = GET_DMA_COUNT(header);
2578 tiled = GET_DMA_T(header);
2579
2580 switch (cmd) {
2581 case DMA_PACKET_WRITE:
2582 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2583 if (r) {
2584 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2585 return -EINVAL;
2586 }
2587 if (tiled) {
2588 dst_offset = ib[idx+1];
2589 dst_offset <<= 8;
2590
2591 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2592 p->idx += count + 5;
2593 } else {
2594 dst_offset = ib[idx+1];
2595 dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
2596
2597 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2598 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2599 p->idx += count + 3;
2600 }
2601 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2602 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
2603 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2604 return -EINVAL;
2605 }
2606 break;
2607 case DMA_PACKET_COPY:
2608 r = r600_dma_cs_next_reloc(p, &src_reloc);
2609 if (r) {
2610 DRM_ERROR("bad DMA_PACKET_COPY\n");
2611 return -EINVAL;
2612 }
2613 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2614 if (r) {
2615 DRM_ERROR("bad DMA_PACKET_COPY\n");
2616 return -EINVAL;
2617 }
2618 if (tiled) {
2619 idx_value = radeon_get_ib_value(p, idx + 2);
2620 /* detile bit */
2621 if (idx_value & (1 << 31)) {
2622 /* tiled src, linear dst */
2623 src_offset = ib[idx+1];
2624 src_offset <<= 8;
2625 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2626
2627 dst_offset = ib[idx+5];
2628 dst_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
2629 ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2630 ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2631 } else {
2632 /* linear src, tiled dst */
2633 src_offset = ib[idx+5];
2634 src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
2635 ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2636 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2637
2638 dst_offset = ib[idx+1];
2639 dst_offset <<= 8;
2640 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2641 }
2642 p->idx += 7;
2643 } else {
Alex Deuchera10fbb42013-01-04 12:16:05 -05002644 if (p->family >= CHIP_RV770) {
2645 src_offset = ib[idx+2];
2646 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
2647 dst_offset = ib[idx+1];
2648 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002649
Alex Deuchera10fbb42013-01-04 12:16:05 -05002650 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2651 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2652 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2653 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2654 p->idx += 5;
2655 } else {
2656 src_offset = ib[idx+2];
2657 src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
2658 dst_offset = ib[idx+1];
2659 dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
2660
2661 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2662 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2663 ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2664 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
2665 p->idx += 4;
2666 }
Alex Deuchercf4ccd02011-11-18 10:19:47 -05002667 }
2668 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2669 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",
2670 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2671 return -EINVAL;
2672 }
2673 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2674 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n",
2675 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2676 return -EINVAL;
2677 }
2678 break;
2679 case DMA_PACKET_CONSTANT_FILL:
2680 if (p->family < CHIP_RV770) {
2681 DRM_ERROR("Constant Fill is 7xx only !\n");
2682 return -EINVAL;
2683 }
2684 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2685 if (r) {
2686 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2687 return -EINVAL;
2688 }
2689 dst_offset = ib[idx+1];
2690 dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
2691 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2692 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
2693 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2694 return -EINVAL;
2695 }
2696 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2697 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
2698 p->idx += 4;
2699 break;
2700 case DMA_PACKET_NOP:
2701 p->idx += 1;
2702 break;
2703 default:
2704 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
2705 return -EINVAL;
2706 }
2707 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2708#if 0
2709 for (r = 0; r < p->ib->length_dw; r++) {
2710 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2711 mdelay(1);
2712 }
2713#endif
2714 return 0;
2715}