blob: 507731ad8ec1e95a591faf5e6854fd12d098a7c9 [file] [log] [blame]
Dimitris Papastamos195af652011-09-19 14:34:01 +01001/*
2 * Register cache access API - indexed caching support
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/slab.h>
14
15#include "internal.h"
16
17static int regcache_indexed_read(struct regmap *map, unsigned int reg,
18 unsigned int *value)
19{
20 int ret;
21
22 ret = regcache_lookup_reg(map, reg);
Mark Brown6e6ace02011-10-09 13:23:31 +010023 if (ret >= 0)
Dimitris Papastamos195af652011-09-19 14:34:01 +010024 *value = map->reg_defaults[ret].def;
Mark Brown6e6ace02011-10-09 13:23:31 +010025
26 return ret;
Dimitris Papastamos195af652011-09-19 14:34:01 +010027}
28
29static int regcache_indexed_write(struct regmap *map, unsigned int reg,
30 unsigned int value)
31{
32 int ret;
33
34 ret = regcache_lookup_reg(map, reg);
35 if (ret < 0)
36 return regcache_insert_reg(map, reg, value);
37 map->reg_defaults[ret].def = value;
38 return 0;
39}
40
41static int regcache_indexed_sync(struct regmap *map)
42{
Dimitris Papastamosdfdc4442011-09-27 11:25:04 +010043 unsigned int i;
Dimitris Papastamos195af652011-09-19 14:34:01 +010044 int ret;
45
46 for (i = 0; i < map->num_reg_defaults; i++) {
Dimitris Papastamos13753a92011-09-29 14:36:25 +010047 ret = _regmap_write(map, map->reg_defaults[i].reg,
48 map->reg_defaults[i].def);
Dimitris Papastamos195af652011-09-19 14:34:01 +010049 if (ret < 0)
50 return ret;
51 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
52 map->reg_defaults[i].reg,
53 map->reg_defaults[i].def);
54 }
55 return 0;
56}
57
58struct regcache_ops regcache_indexed_ops = {
59 .type = REGCACHE_INDEXED,
60 .name = "indexed",
61 .read = regcache_indexed_read,
62 .write = regcache_indexed_write,
63 .sync = regcache_indexed_sync
64};