| Tony Lin | d080aa5 | 2011-01-11 18:01:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | */ |
| 4 | |
| 5 | /* |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 19 | * |
| 20 | * This file is created by xml file. Don't Edit it. |
| 21 | * |
| 22 | * Xml Revision: 1.36 |
| 23 | * Template revision: 26195 |
| 24 | */ |
| 25 | |
| 26 | #ifndef __ARCH_ARM___PERFMON_H |
| 27 | #define __ARCH_ARM___PERFMON_H |
| 28 | |
| 29 | |
| 30 | #define HW_PERFMON_CTRL (0x00000000) |
| 31 | #define HW_PERFMON_CTRL_SET (0x00000004) |
| 32 | #define HW_PERFMON_CTRL_CLR (0x00000008) |
| 33 | #define HW_PERFMON_CTRL_TOG (0x0000000c) |
| 34 | |
| 35 | #define BM_PERFMON_CTRL_SFTRST 0x80000000 |
| 36 | #define BV_PERFMON_CTRL_SFTRST__RUN 0x0 |
| 37 | #define BV_PERFMON_CTRL_SFTRST__RESET 0x1 |
| 38 | #define BM_PERFMON_CTRL_CLKGATE 0x40000000 |
| 39 | #define BV_PERFMON_CTRL_CLKGATE__RUN 0x0 |
| 40 | #define BV_PERFMON_CTRL_CLKGATE__NO_CLKS 0x1 |
| 41 | #define BP_PERFMON_CTRL_RSVD2 24 |
| 42 | #define BM_PERFMON_CTRL_RSVD2 0x3F000000 |
| 43 | #define BF_PERFMON_CTRL_RSVD2(v) \ |
| 44 | (((v) << 24) & BM_PERFMON_CTRL_RSVD2) |
| 45 | #define BP_PERFMON_CTRL_IRQ_MID 16 |
| 46 | #define BM_PERFMON_CTRL_IRQ_MID 0x00FF0000 |
| 47 | #define BF_PERFMON_CTRL_IRQ_MID(v) \ |
| 48 | (((v) << 16) & BM_PERFMON_CTRL_IRQ_MID) |
| 49 | #define BP_PERFMON_CTRL_RSVD1 13 |
| 50 | #define BM_PERFMON_CTRL_RSVD1 0x0000E000 |
| 51 | #define BF_PERFMON_CTRL_RSVD1(v) \ |
| 52 | (((v) << 13) & BM_PERFMON_CTRL_RSVD1) |
| 53 | #define BM_PERFMON_CTRL_BUS_ERR_IRQ 0x00001000 |
| 54 | #define BM_PERFMON_CTRL_LATENCY_IRQ 0x00000800 |
| 55 | #define BM_PERFMON_CTRL_TRAP_IRQ 0x00000400 |
| 56 | #define BM_PERFMON_CTRL_BUS_ERR_IRQ_EN 0x00000200 |
| 57 | #define BM_PERFMON_CTRL_LATENCY_IRQ_EN 0x00000100 |
| 58 | #define BM_PERFMON_CTRL_TRAP_IRQ_EN 0x00000080 |
| 59 | #define BM_PERFMON_CTRL_LATENCY_ENABLE 0x00000040 |
| 60 | #define BM_PERFMON_CTRL_TRAP_IN_RANGE 0x00000020 |
| 61 | #define BM_PERFMON_CTRL_TRAP_ENABLE 0x00000010 |
| 62 | #define BM_PERFMON_CTRL_READ_EN 0x00000008 |
| 63 | #define BM_PERFMON_CTRL_CLR 0x00000004 |
| 64 | #define BM_PERFMON_CTRL_SNAP 0x00000002 |
| 65 | #define BM_PERFMON_CTRL_RUN 0x00000001 |
| 66 | #define BV_PERFMON_CTRL_RUN__HALT 0x0 |
| 67 | #define BV_PERFMON_CTRL_RUN__RUN 0x1 |
| 68 | |
| 69 | #define HW_PERFMON_MASTER_EN (0x00000010) |
| 70 | |
| 71 | #define BP_PERFMON_MASTER_EN_RSVD0 16 |
| 72 | #define BM_PERFMON_MASTER_EN_RSVD0 0xFFFF0000 |
| 73 | #define BF_PERFMON_MASTER_EN_RSVD0(v) \ |
| 74 | (((v) << 16) & BM_PERFMON_MASTER_EN_RSVD0) |
| 75 | #define BM_PERFMON_MASTER_EN_MID15 0x00008000 |
| 76 | #define BM_PERFMON_MASTER_EN_MID14 0x00004000 |
| 77 | #define BM_PERFMON_MASTER_EN_MID13 0x00002000 |
| 78 | #define BM_PERFMON_MASTER_EN_MID12 0x00001000 |
| 79 | #define BM_PERFMON_MASTER_EN_MID11 0x00000800 |
| 80 | #define BM_PERFMON_MASTER_EN_MID10 0x00000400 |
| 81 | #define BM_PERFMON_MASTER_EN_MID9 0x00000200 |
| 82 | #define BM_PERFMON_MASTER_EN_MID8 0x00000100 |
| 83 | #define BM_PERFMON_MASTER_EN_MID7 0x00000080 |
| 84 | #define BM_PERFMON_MASTER_EN_MID6 0x00000040 |
| 85 | #define BM_PERFMON_MASTER_EN_MID5 0x00000020 |
| 86 | #define BM_PERFMON_MASTER_EN_MID4 0x00000010 |
| 87 | #define BM_PERFMON_MASTER_EN_MID3 0x00000008 |
| 88 | #define BM_PERFMON_MASTER_EN_MID2 0x00000004 |
| 89 | #define BM_PERFMON_MASTER_EN_MID1 0x00000002 |
| 90 | #define BM_PERFMON_MASTER_EN_MID0 0x00000001 |
| 91 | |
| 92 | #define HW_PERFMON_TRAP_ADDR_LOW (0x00000020) |
| 93 | |
| 94 | #define BP_PERFMON_TRAP_ADDR_LOW_ADDR 0 |
| 95 | #define BM_PERFMON_TRAP_ADDR_LOW_ADDR 0xFFFFFFFF |
| 96 | #define BF_PERFMON_TRAP_ADDR_LOW_ADDR(v) (v) |
| 97 | |
| 98 | #define HW_PERFMON_TRAP_ADDR_HIGH (0x00000030) |
| 99 | |
| 100 | #define BP_PERFMON_TRAP_ADDR_HIGH_ADDR 0 |
| 101 | #define BM_PERFMON_TRAP_ADDR_HIGH_ADDR 0xFFFFFFFF |
| 102 | #define BF_PERFMON_TRAP_ADDR_HIGH_ADDR(v) (v) |
| 103 | |
| 104 | #define HW_PERFMON_LAT_THRESHOLD (0x00000040) |
| 105 | |
| 106 | #define BP_PERFMON_LAT_THRESHOLD_RSVD0 12 |
| 107 | #define BM_PERFMON_LAT_THRESHOLD_RSVD0 0xFFFFF000 |
| 108 | #define BF_PERFMON_LAT_THRESHOLD_RSVD0(v) \ |
| 109 | (((v) << 12) & BM_PERFMON_LAT_THRESHOLD_RSVD0) |
| 110 | #define BP_PERFMON_LAT_THRESHOLD_VALUE 0 |
| 111 | #define BM_PERFMON_LAT_THRESHOLD_VALUE 0x00000FFF |
| 112 | #define BF_PERFMON_LAT_THRESHOLD_VALUE(v) \ |
| 113 | (((v) << 0) & BM_PERFMON_LAT_THRESHOLD_VALUE) |
| 114 | |
| 115 | #define HW_PERFMON_ACTIVE_CYCLE (0x00000050) |
| 116 | |
| 117 | #define BP_PERFMON_ACTIVE_CYCLE_COUNT 0 |
| 118 | #define BM_PERFMON_ACTIVE_CYCLE_COUNT 0xFFFFFFFF |
| 119 | #define BF_PERFMON_ACTIVE_CYCLE_COUNT(v) (v) |
| 120 | |
| 121 | #define HW_PERFMON_TRANSFER_COUNT (0x00000060) |
| 122 | |
| 123 | #define BP_PERFMON_TRANSFER_COUNT_VALUE 0 |
| 124 | #define BM_PERFMON_TRANSFER_COUNT_VALUE 0xFFFFFFFF |
| 125 | #define BF_PERFMON_TRANSFER_COUNT_VALUE(v) (v) |
| 126 | |
| 127 | #define HW_PERFMON_TOTAL_LATENCY (0x00000070) |
| 128 | |
| 129 | #define BP_PERFMON_TOTAL_LATENCY_COUNT 0 |
| 130 | #define BM_PERFMON_TOTAL_LATENCY_COUNT 0xFFFFFFFF |
| 131 | #define BF_PERFMON_TOTAL_LATENCY_COUNT(v) (v) |
| 132 | |
| 133 | #define HW_PERFMON_DATA_COUNT (0x00000080) |
| 134 | |
| 135 | #define BP_PERFMON_DATA_COUNT_COUNT 0 |
| 136 | #define BM_PERFMON_DATA_COUNT_COUNT 0xFFFFFFFF |
| 137 | #define BF_PERFMON_DATA_COUNT_COUNT(v) (v) |
| 138 | |
| 139 | #define HW_PERFMON_MAX_LATENCY (0x00000090) |
| 140 | |
| 141 | #define BP_PERFMON_MAX_LATENCY_ABURST 30 |
| 142 | #define BM_PERFMON_MAX_LATENCY_ABURST 0xC0000000 |
| 143 | #define BF_PERFMON_MAX_LATENCY_ABURST(v) \ |
| 144 | (((v) << 30) & BM_PERFMON_MAX_LATENCY_ABURST) |
| 145 | #define BP_PERFMON_MAX_LATENCY_ALEN 26 |
| 146 | #define BM_PERFMON_MAX_LATENCY_ALEN 0x3C000000 |
| 147 | #define BF_PERFMON_MAX_LATENCY_ALEN(v) \ |
| 148 | (((v) << 26) & BM_PERFMON_MAX_LATENCY_ALEN) |
| 149 | #define BP_PERFMON_MAX_LATENCY_ASIZE 23 |
| 150 | #define BM_PERFMON_MAX_LATENCY_ASIZE 0x03800000 |
| 151 | #define BF_PERFMON_MAX_LATENCY_ASIZE(v) \ |
| 152 | (((v) << 23) & BM_PERFMON_MAX_LATENCY_ASIZE) |
| 153 | #define BP_PERFMON_MAX_LATENCY_TAGID 15 |
| 154 | #define BM_PERFMON_MAX_LATENCY_TAGID 0x007F8000 |
| 155 | #define BF_PERFMON_MAX_LATENCY_TAGID(v) \ |
| 156 | (((v) << 15) & BM_PERFMON_MAX_LATENCY_TAGID) |
| 157 | #define BP_PERFMON_MAX_LATENCY_RSVD0 12 |
| 158 | #define BM_PERFMON_MAX_LATENCY_RSVD0 0x00007000 |
| 159 | #define BF_PERFMON_MAX_LATENCY_RSVD0(v) \ |
| 160 | (((v) << 12) & BM_PERFMON_MAX_LATENCY_RSVD0) |
| 161 | #define BP_PERFMON_MAX_LATENCY_COUNT 0 |
| 162 | #define BM_PERFMON_MAX_LATENCY_COUNT 0x00000FFF |
| 163 | #define BF_PERFMON_MAX_LATENCY_COUNT(v) \ |
| 164 | (((v) << 0) & BM_PERFMON_MAX_LATENCY_COUNT) |
| 165 | |
| 166 | #define HW_PERFMON_DEBUG (0x000000a0) |
| 167 | |
| 168 | #define BP_PERFMON_DEBUG_RSVD 2 |
| 169 | #define BM_PERFMON_DEBUG_RSVD 0xFFFFFFFC |
| 170 | #define BF_PERFMON_DEBUG_RSVD(v) \ |
| 171 | (((v) << 2) & BM_PERFMON_DEBUG_RSVD) |
| 172 | #define BM_PERFMON_DEBUG_TOTAL_CYCLE_CLR_EN 0x00000002 |
| 173 | #define BM_PERFMON_DEBUG_ERR_MID 0x00000001 |
| 174 | |
| 175 | #define HW_PERFMON_VERSION (0x000000b0) |
| 176 | |
| 177 | #define BP_PERFMON_VERSION_MAJOR 24 |
| 178 | #define BM_PERFMON_VERSION_MAJOR 0xFF000000 |
| 179 | #define BF_PERFMON_VERSION_MAJOR(v) \ |
| 180 | (((v) << 24) & BM_PERFMON_VERSION_MAJOR) |
| 181 | #define BP_PERFMON_VERSION_MINOR 16 |
| 182 | #define BM_PERFMON_VERSION_MINOR 0x00FF0000 |
| 183 | #define BF_PERFMON_VERSION_MINOR(v) \ |
| 184 | (((v) << 16) & BM_PERFMON_VERSION_MINOR) |
| 185 | #define BP_PERFMON_VERSION_STEP 0 |
| 186 | #define BM_PERFMON_VERSION_STEP 0x0000FFFF |
| 187 | #define BF_PERFMON_VERSION_STEP(v) \ |
| 188 | (((v) << 0) & BM_PERFMON_VERSION_STEP) |
| 189 | #endif /* __ARCH_ARM___PERFMON_H */ |