| Zeng Zhaoming | a9ce0be | 2011-06-28 09:15:47 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __ARCH_ARM_MACH_MX51_SERIAL_H__ |
| 20 | #define __ARCH_ARM_MACH_MX51_SERIAL_H__ |
| 21 | |
| 22 | /* UART 1 configuration */ |
| 23 | /*! |
| 24 | * This specifies the threshold at which the CTS pin is deasserted by the |
| 25 | * RXFIFO. Set this value in Decimal to anything from 0 to 32 for |
| 26 | * hardware-driven hardware flow control. Read the HW spec while specifying |
| 27 | * this value. When using interrupt-driven software controlled hardware |
| 28 | * flow control set this option to -1. |
| 29 | */ |
| 30 | #define UART1_UCR4_CTSTL 16 |
| 31 | /*! |
| 32 | * Specify the size of the DMA receive buffer. The minimum buffer size is 512 |
| 33 | * bytes. The buffer size should be a multiple of 256. |
| 34 | */ |
| 35 | #define UART1_DMA_RXBUFSIZE 1024 |
| 36 | /*! |
| 37 | * Specify the MXC UART's Receive Trigger Level. This controls the threshold at |
| 38 | * which a maskable interrupt is generated by the RxFIFO. Set this value in |
| 39 | * Decimal to anything from 0 to 32. Read the HW spec while specifying this |
| 40 | * value. |
| 41 | */ |
| 42 | #define UART1_UFCR_RXTL 16 |
| 43 | /*! |
| 44 | * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at |
| 45 | * which a maskable interrupt is generated by the TxFIFO. Set this value in |
| 46 | * Decimal to anything from 0 to 32. Read the HW spec while specifying this |
| 47 | * value. |
| 48 | */ |
| 49 | #define UART1_UFCR_TXTL 16 |
| 50 | #define UART1_DMA_ENABLE 0 |
| 51 | /* UART 2 configuration */ |
| 52 | #define UART2_UCR4_CTSTL -1 |
| 53 | #define UART2_DMA_ENABLE 1 |
| 54 | #define UART2_DMA_RXBUFSIZE 512 |
| 55 | #define UART2_UFCR_RXTL 16 |
| 56 | #define UART2_UFCR_TXTL 16 |
| 57 | /* UART 3 configuration */ |
| 58 | #define UART3_UCR4_CTSTL 16 |
| 59 | #define UART3_DMA_ENABLE 1 |
| 60 | #define UART3_DMA_RXBUFSIZE 1024 |
| 61 | #define UART3_UFCR_RXTL 16 |
| 62 | #define UART3_UFCR_TXTL 16 |
| 63 | /* UART 4 configuration */ |
| 64 | #define UART4_UCR4_CTSTL -1 |
| 65 | #define UART4_DMA_ENABLE 0 |
| 66 | #define UART4_DMA_RXBUFSIZE 512 |
| 67 | #define UART4_UFCR_RXTL 16 |
| 68 | #define UART4_UFCR_TXTL 16 |
| 69 | /* UART 5 configuration */ |
| 70 | #define UART5_UCR4_CTSTL -1 |
| 71 | #define UART5_DMA_ENABLE 0 |
| 72 | #define UART5_DMA_RXBUFSIZE 512 |
| 73 | #define UART5_UFCR_RXTL 16 |
| 74 | #define UART5_UFCR_TXTL 16 |
| 75 | |
| 76 | #endif /* __ARCH_ARM_MACH_MX51_SERIAL_H__ */ |