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Stephen Warrena50a3992011-01-07 22:36:15 -07001/*
2 * tegra_asoc_utils.c - Harmony machine ASoC driver
3 *
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010 - NVIDIA, Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/clk.h>
Stephen Warrend64e57c2011-01-28 14:26:40 -070024#include <linux/device.h>
Stephen Warrena50a3992011-01-07 22:36:15 -070025#include <linux/err.h>
26#include <linux/kernel.h>
27
28#include "tegra_asoc_utils.h"
29
Stephen Warrend64e57c2011-01-28 14:26:40 -070030int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
Stephen Warren07541392011-04-19 15:25:09 -060031 int mclk)
Stephen Warrena50a3992011-01-07 22:36:15 -070032{
33 int new_baseclock;
Stephen Warren07541392011-04-19 15:25:09 -060034 bool clk_change;
Stephen Warrena50a3992011-01-07 22:36:15 -070035 int err;
36
37 switch (srate) {
38 case 11025:
39 case 22050:
40 case 44100:
41 case 88200:
42 new_baseclock = 56448000;
43 break;
44 case 8000:
45 case 16000:
46 case 32000:
47 case 48000:
48 case 64000:
49 case 96000:
50 new_baseclock = 73728000;
51 break;
52 default:
53 return -EINVAL;
54 }
55
Stephen Warren07541392011-04-19 15:25:09 -060056 clk_change = ((new_baseclock != data->set_baseclock) ||
Stephen Warrend64e57c2011-01-28 14:26:40 -070057 (mclk != data->set_mclk));
Stephen Warren07541392011-04-19 15:25:09 -060058 if (!clk_change)
59 return 0;
Stephen Warrena50a3992011-01-07 22:36:15 -070060
Stephen Warrend64e57c2011-01-28 14:26:40 -070061 data->set_baseclock = 0;
62 data->set_mclk = 0;
Stephen Warrena50a3992011-01-07 22:36:15 -070063
Stephen Warrend64e57c2011-01-28 14:26:40 -070064 clk_disable(data->clk_cdev1);
65 clk_disable(data->clk_pll_a_out0);
66 clk_disable(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -070067
Stephen Warrend64e57c2011-01-28 14:26:40 -070068 err = clk_set_rate(data->clk_pll_a, new_baseclock);
Stephen Warrena50a3992011-01-07 22:36:15 -070069 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070070 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070071 return err;
72 }
73
Stephen Warrend64e57c2011-01-28 14:26:40 -070074 err = clk_set_rate(data->clk_pll_a_out0, mclk);
Stephen Warrena50a3992011-01-07 22:36:15 -070075 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070076 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070077 return err;
78 }
79
80 /* Don't set cdev1 rate; its locked to pll_a_out0 */
81
Stephen Warrend64e57c2011-01-28 14:26:40 -070082 err = clk_enable(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -070083 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070084 dev_err(data->dev, "Can't enable pll_a: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070085 return err;
86 }
87
Stephen Warrend64e57c2011-01-28 14:26:40 -070088 err = clk_enable(data->clk_pll_a_out0);
Stephen Warrena50a3992011-01-07 22:36:15 -070089 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070090 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070091 return err;
92 }
93
Stephen Warrend64e57c2011-01-28 14:26:40 -070094 err = clk_enable(data->clk_cdev1);
Stephen Warrena50a3992011-01-07 22:36:15 -070095 if (err) {
Stephen Warrend64e57c2011-01-28 14:26:40 -070096 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
Stephen Warrena50a3992011-01-07 22:36:15 -070097 return err;
98 }
99
Stephen Warrend64e57c2011-01-28 14:26:40 -0700100 data->set_baseclock = new_baseclock;
101 data->set_mclk = mclk;
Stephen Warrena50a3992011-01-07 22:36:15 -0700102
103 return 0;
104}
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700105EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
Stephen Warrena50a3992011-01-07 22:36:15 -0700106
Stephen Warrend64e57c2011-01-28 14:26:40 -0700107int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
108 struct device *dev)
Stephen Warrena50a3992011-01-07 22:36:15 -0700109{
110 int ret;
111
Stephen Warrend64e57c2011-01-28 14:26:40 -0700112 data->dev = dev;
113
114 data->clk_pll_a = clk_get_sys(NULL, "pll_a");
115 if (IS_ERR(data->clk_pll_a)) {
116 dev_err(data->dev, "Can't retrieve clk pll_a\n");
117 ret = PTR_ERR(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -0700118 goto err;
119 }
120
Stephen Warrend64e57c2011-01-28 14:26:40 -0700121 data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
122 if (IS_ERR(data->clk_pll_a_out0)) {
123 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
124 ret = PTR_ERR(data->clk_pll_a_out0);
Stephen Warren422650e2011-01-11 12:48:53 -0700125 goto err_put_pll_a;
Stephen Warrena50a3992011-01-07 22:36:15 -0700126 }
127
Stephen Warrend64e57c2011-01-28 14:26:40 -0700128 data->clk_cdev1 = clk_get_sys(NULL, "cdev1");
129 if (IS_ERR(data->clk_cdev1)) {
130 dev_err(data->dev, "Can't retrieve clk cdev1\n");
131 ret = PTR_ERR(data->clk_cdev1);
Stephen Warren422650e2011-01-11 12:48:53 -0700132 goto err_put_pll_a_out0;
Stephen Warrena50a3992011-01-07 22:36:15 -0700133 }
134
135 return 0;
136
Stephen Warren422650e2011-01-11 12:48:53 -0700137err_put_pll_a_out0:
Stephen Warrend64e57c2011-01-28 14:26:40 -0700138 clk_put(data->clk_pll_a_out0);
Stephen Warren422650e2011-01-11 12:48:53 -0700139err_put_pll_a:
Stephen Warrend64e57c2011-01-28 14:26:40 -0700140 clk_put(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -0700141err:
Stephen Warrena50a3992011-01-07 22:36:15 -0700142 return ret;
143}
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700144EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
Stephen Warrena50a3992011-01-07 22:36:15 -0700145
Stephen Warrend64e57c2011-01-28 14:26:40 -0700146void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
Stephen Warrena50a3992011-01-07 22:36:15 -0700147{
Stephen Warrend64e57c2011-01-28 14:26:40 -0700148 clk_put(data->clk_cdev1);
149 clk_put(data->clk_pll_a_out0);
150 clk_put(data->clk_pll_a);
Stephen Warrena50a3992011-01-07 22:36:15 -0700151}
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700152EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
Stephen Warrena50a3992011-01-07 22:36:15 -0700153
Stephen Warrena3cd50d2011-02-22 17:23:56 -0700154MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
155MODULE_DESCRIPTION("Tegra ASoC utility code");
156MODULE_LICENSE("GPL");