blob: d1eabd4165c4506d52d8d3e8b185c66076dd8374 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070030#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100037#include "drm_dp_helper.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070038
Jesse Barnesa2006cf2011-09-22 11:15:58 +053039#define DP_RECEIVER_CAP_SIZE 0xf
Keith Packarda4fc5ed2009-04-07 16:16:42 -070040#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
Chris Wilsonea5b2132010-08-04 13:50:23 +010045struct intel_dp {
46 struct intel_encoder base;
Keith Packarda4fc5ed2009-04-07 16:16:42 -070047 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -070050 bool has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +010051 int force_audio;
Chris Wilsone953fd72011-02-21 22:23:52 +000052 uint32_t color_range;
Keith Packardd2b996a2011-07-25 22:37:51 -070053 int dpms_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -070054 uint8_t link_bw;
55 uint8_t lane_count;
Jesse Barnesa2006cf2011-09-22 11:15:58 +053056 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -070057 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
Adam Jacksonf0917372010-07-16 14:46:27 -040059 bool is_pch_edp;
Jesse Barnes33a34e42010-09-08 12:42:02 -070060 uint8_t train_set[4];
Keith Packardf01eca22011-09-28 16:48:10 -070061 int panel_power_up_delay;
62 int panel_power_down_delay;
63 int panel_power_cycle_delay;
64 int backlight_on_delay;
65 int backlight_off_delay;
Keith Packardd15456d2011-09-18 17:35:47 -070066 struct drm_display_mode *panel_fixed_mode; /* for eDP */
Keith Packardbd943152011-09-18 23:09:52 -070067 struct delayed_work panel_vdd_work;
68 bool want_panel_vdd;
69 unsigned long panel_off_jiffies;
Keith Packarda4fc5ed2009-04-07 16:16:42 -070070};
71
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070072/**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
79static bool is_edp(struct intel_dp *intel_dp)
80{
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82}
83
84/**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
92static bool is_pch_edp(struct intel_dp *intel_dp)
93{
94 return intel_dp->is_pch_edp;
95}
96
Adam Jackson1c958222011-10-14 17:22:25 -040097/**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103static bool is_cpu_edp(struct intel_dp *intel_dp)
104{
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106}
107
Chris Wilsonea5b2132010-08-04 13:50:23 +0100108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100110 return container_of(encoder, struct intel_dp, base.base);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100111}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700112
Chris Wilsondf0e9242010-09-09 16:20:55 +0100113static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114{
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117}
118
Jesse Barnes814948a2010-10-07 16:01:09 -0700119/**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
126bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127{
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136}
137
Jesse Barnes33a34e42010-09-08 12:42:02 -0700138static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100140static void intel_dp_link_down(struct intel_dp *intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700141
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800142void
Akshay Joshi0206e352011-08-16 15:34:10 -0400143intel_edp_link_config(struct intel_encoder *intel_encoder,
Chris Wilsonea5b2132010-08-04 13:50:23 +0100144 int *lane_num, int *link_bw)
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800145{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800147
Chris Wilsonea5b2132010-08-04 13:50:23 +0100148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800150 *link_bw = 162000;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800152 *link_bw = 270000;
153}
154
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700155static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100156intel_dp_max_lane_count(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700157{
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700158 int max_lane_count = 4;
159
Jesse Barnes7183dc22011-07-07 11:10:58 -0700160 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
161 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700162 switch (max_lane_count) {
163 case 1: case 2: case 4:
164 break;
165 default:
166 max_lane_count = 4;
167 }
168 }
169 return max_lane_count;
170}
171
172static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100173intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700174{
Jesse Barnes7183dc22011-07-07 11:10:58 -0700175 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700176
177 switch (max_link_bw) {
178 case DP_LINK_BW_1_62:
179 case DP_LINK_BW_2_7:
180 break;
181 default:
182 max_link_bw = DP_LINK_BW_1_62;
183 break;
184 }
185 return max_link_bw;
186}
187
188static int
189intel_dp_link_clock(uint8_t link_bw)
190{
191 if (link_bw == DP_LINK_BW_2_7)
192 return 270000;
193 else
194 return 162000;
195}
196
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400197/*
198 * The units on the numbers in the next two are... bizarre. Examples will
199 * make it clearer; this one parallels an example in the eDP spec.
200 *
201 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
202 *
203 * 270000 * 1 * 8 / 10 == 216000
204 *
205 * The actual data capacity of that configuration is 2.16Gbit/s, so the
206 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
207 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
208 * 119000. At 18bpp that's 2142000 kilobits per second.
209 *
210 * Thus the strange-looking division by 10 in intel_dp_link_required, to
211 * get the result in decakilobits instead of kilobits.
212 */
213
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700214static int
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400215intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700216{
Jesse Barnes89c61432011-06-24 12:19:28 -0700217 struct drm_crtc *crtc = intel_dp->base.base.crtc;
218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
219 int bpp = 24;
Zhenyu Wang885a5fb2010-01-12 05:38:31 +0800220
Jesse Barnes89c61432011-06-24 12:19:28 -0700221 if (intel_crtc)
222 bpp = intel_crtc->bpp;
223
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400224 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700225}
226
227static int
Dave Airliefe27d532010-06-30 11:46:17 +1000228intel_dp_max_data_rate(int max_link_clock, int max_lanes)
229{
230 return (max_link_clock * max_lanes * 8) / 10;
231}
232
233static int
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700234intel_dp_mode_valid(struct drm_connector *connector,
235 struct drm_display_mode *mode)
236{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100237 struct intel_dp *intel_dp = intel_attached_dp(connector);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100238 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
239 int max_lanes = intel_dp_max_lane_count(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700240
Keith Packardd15456d2011-09-18 17:35:47 -0700241 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
242 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100243 return MODE_PANEL;
244
Keith Packardd15456d2011-09-18 17:35:47 -0700245 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100246 return MODE_PANEL;
247 }
248
Adam Jacksondc22ee62011-10-14 12:43:50 -0400249 if (intel_dp_link_required(intel_dp, mode->clock)
250 > intel_dp_max_data_rate(max_link_clock, max_lanes))
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700251 return MODE_CLOCK_HIGH;
252
253 if (mode->clock < 10000)
254 return MODE_CLOCK_LOW;
255
256 return MODE_OK;
257}
258
259static uint32_t
260pack_aux(uint8_t *src, int src_bytes)
261{
262 int i;
263 uint32_t v = 0;
264
265 if (src_bytes > 4)
266 src_bytes = 4;
267 for (i = 0; i < src_bytes; i++)
268 v |= ((uint32_t) src[i]) << ((3-i) * 8);
269 return v;
270}
271
272static void
273unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
274{
275 int i;
276 if (dst_bytes > 4)
277 dst_bytes = 4;
278 for (i = 0; i < dst_bytes; i++)
279 dst[i] = src >> ((3-i) * 8);
280}
281
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700282/* hrawclock is 1/4 the FSB frequency */
283static int
284intel_hrawclk(struct drm_device *dev)
285{
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 uint32_t clkcfg;
288
289 clkcfg = I915_READ(CLKCFG);
290 switch (clkcfg & CLKCFG_FSB_MASK) {
291 case CLKCFG_FSB_400:
292 return 100;
293 case CLKCFG_FSB_533:
294 return 133;
295 case CLKCFG_FSB_667:
296 return 166;
297 case CLKCFG_FSB_800:
298 return 200;
299 case CLKCFG_FSB_1067:
300 return 266;
301 case CLKCFG_FSB_1333:
302 return 333;
303 /* these two are just a guess; one of them might be right */
304 case CLKCFG_FSB_1600:
305 case CLKCFG_FSB_1600_ALT:
306 return 400;
307 default:
308 return 133;
309 }
310}
311
Keith Packardebf33b12011-09-29 15:53:27 -0700312static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp->base.base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
318}
319
320static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
321{
322 struct drm_device *dev = intel_dp->base.base.dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
326}
327
Keith Packard9b984da2011-09-19 13:54:47 -0700328static void
329intel_dp_check_edp(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp->base.base.dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700333
Keith Packard9b984da2011-09-19 13:54:47 -0700334 if (!is_edp(intel_dp))
335 return;
Keith Packardebf33b12011-09-29 15:53:27 -0700336 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700337 WARN(1, "eDP powered off while attempting aux channel communication.\n");
338 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Keith Packardebf33b12011-09-29 15:53:27 -0700339 I915_READ(PCH_PP_STATUS),
Keith Packard9b984da2011-09-19 13:54:47 -0700340 I915_READ(PCH_PP_CONTROL));
341 }
342}
343
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700344static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100345intel_dp_aux_ch(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700346 uint8_t *send, int send_bytes,
347 uint8_t *recv, int recv_size)
348{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100349 uint32_t output_reg = intel_dp->output_reg;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100350 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700351 struct drm_i915_private *dev_priv = dev->dev_private;
352 uint32_t ch_ctl = output_reg + 0x10;
353 uint32_t ch_data = ch_ctl + 4;
354 int i;
355 int recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700356 uint32_t status;
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700357 uint32_t aux_clock_divider;
Zhenyu Wange3421a12010-04-08 09:43:27 +0800358 int try, precharge;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700359
Keith Packard9b984da2011-09-19 13:54:47 -0700360 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700361 /* The clock divider is based off the hrawclk,
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
Jesse Barnes6176b8f2010-09-08 12:42:00 -0700364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700367 */
Adam Jackson1c958222011-10-14 17:22:25 -0400368 if (is_cpu_edp(intel_dp)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +0800369 if (IS_GEN6(dev))
370 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
371 else
372 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
373 } else if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500374 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800375 else
376 aux_clock_divider = intel_hrawclk(dev) / 2;
377
Zhenyu Wange3421a12010-04-08 09:43:27 +0800378 if (IS_GEN6(dev))
379 precharge = 3;
380 else
381 precharge = 5;
382
Jesse Barnes11bee432011-08-01 15:02:20 -0700383 /* Try to wait for any previous AUX channel activity */
384 for (try = 0; try < 3; try++) {
385 status = I915_READ(ch_ctl);
386 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
387 break;
388 msleep(1);
389 }
390
391 if (try == 3) {
392 WARN(1, "dp_aux_ch not started status 0x%08x\n",
393 I915_READ(ch_ctl));
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100394 return -EBUSY;
395 }
396
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700397 /* Must try at least 3 times according to DP spec */
398 for (try = 0; try < 5; try++) {
399 /* Load the send data into the aux channel data registers */
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100400 for (i = 0; i < send_bytes; i += 4)
401 I915_WRITE(ch_data + i,
402 pack_aux(send + i, send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400403
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700404 /* Send the command and wait for it to complete */
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100405 I915_WRITE(ch_ctl,
406 DP_AUX_CH_CTL_SEND_BUSY |
407 DP_AUX_CH_CTL_TIME_OUT_400us |
408 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
409 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
410 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
411 DP_AUX_CH_CTL_DONE |
412 DP_AUX_CH_CTL_TIME_OUT_ERROR |
413 DP_AUX_CH_CTL_RECEIVE_ERROR);
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700414 for (;;) {
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700415 status = I915_READ(ch_ctl);
416 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
417 break;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100418 udelay(100);
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700419 }
Akshay Joshi0206e352011-08-16 15:34:10 -0400420
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700421 /* Clear done status and any errors */
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100422 I915_WRITE(ch_ctl,
423 status |
424 DP_AUX_CH_CTL_DONE |
425 DP_AUX_CH_CTL_TIME_OUT_ERROR |
426 DP_AUX_CH_CTL_RECEIVE_ERROR);
427 if (status & DP_AUX_CH_CTL_DONE)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700428 break;
429 }
430
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700431 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700432 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Keith Packarda5b3da52009-06-11 22:30:32 -0700433 return -EBUSY;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700434 }
435
436 /* Check for timeout or receive error.
437 * Timeouts occur when the sink is not connected
438 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700439 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700440 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Keith Packarda5b3da52009-06-11 22:30:32 -0700441 return -EIO;
442 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700443
444 /* Timeouts occur when the device isn't connected, so they're
445 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700446 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800447 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Keith Packarda5b3da52009-06-11 22:30:32 -0700448 return -ETIMEDOUT;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700449 }
450
451 /* Unload any bytes sent back from the other side */
452 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
453 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700454 if (recv_bytes > recv_size)
455 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400456
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100457 for (i = 0; i < recv_bytes; i += 4)
458 unpack_aux(I915_READ(ch_data + i),
459 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700460
461 return recv_bytes;
462}
463
464/* Write data to the aux channel in native mode */
465static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100466intel_dp_aux_native_write(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700467 uint16_t address, uint8_t *send, int send_bytes)
468{
469 int ret;
470 uint8_t msg[20];
471 int msg_bytes;
472 uint8_t ack;
473
Keith Packard9b984da2011-09-19 13:54:47 -0700474 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700475 if (send_bytes > 16)
476 return -1;
477 msg[0] = AUX_NATIVE_WRITE << 4;
478 msg[1] = address >> 8;
Zhenyu Wangeebc8632009-07-24 01:00:30 +0800479 msg[2] = address & 0xff;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700480 msg[3] = send_bytes - 1;
481 memcpy(&msg[4], send, send_bytes);
482 msg_bytes = send_bytes + 4;
483 for (;;) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100484 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700485 if (ret < 0)
486 return ret;
487 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
488 break;
489 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
490 udelay(100);
491 else
Keith Packarda5b3da52009-06-11 22:30:32 -0700492 return -EIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700493 }
494 return send_bytes;
495}
496
497/* Write a single byte to the aux channel in native mode */
498static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100499intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700500 uint16_t address, uint8_t byte)
501{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100502 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700503}
504
505/* read bytes from a native aux channel */
506static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100507intel_dp_aux_native_read(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700508 uint16_t address, uint8_t *recv, int recv_bytes)
509{
510 uint8_t msg[4];
511 int msg_bytes;
512 uint8_t reply[20];
513 int reply_bytes;
514 uint8_t ack;
515 int ret;
516
Keith Packard9b984da2011-09-19 13:54:47 -0700517 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700518 msg[0] = AUX_NATIVE_READ << 4;
519 msg[1] = address >> 8;
520 msg[2] = address & 0xff;
521 msg[3] = recv_bytes - 1;
522
523 msg_bytes = 4;
524 reply_bytes = recv_bytes + 1;
525
526 for (;;) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100527 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700528 reply, reply_bytes);
Keith Packarda5b3da52009-06-11 22:30:32 -0700529 if (ret == 0)
530 return -EPROTO;
531 if (ret < 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700532 return ret;
533 ack = reply[0];
534 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
535 memcpy(recv, reply + 1, ret - 1);
536 return ret - 1;
537 }
538 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
539 udelay(100);
540 else
Keith Packarda5b3da52009-06-11 22:30:32 -0700541 return -EIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700542 }
543}
544
545static int
Dave Airlieab2c0672009-12-04 10:55:24 +1000546intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
547 uint8_t write_byte, uint8_t *read_byte)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700548{
Dave Airlieab2c0672009-12-04 10:55:24 +1000549 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100550 struct intel_dp *intel_dp = container_of(adapter,
551 struct intel_dp,
552 adapter);
Dave Airlieab2c0672009-12-04 10:55:24 +1000553 uint16_t address = algo_data->address;
554 uint8_t msg[5];
555 uint8_t reply[2];
David Flynn8316f332010-12-08 16:10:21 +0000556 unsigned retry;
Dave Airlieab2c0672009-12-04 10:55:24 +1000557 int msg_bytes;
558 int reply_bytes;
559 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700560
Keith Packard9b984da2011-09-19 13:54:47 -0700561 intel_dp_check_edp(intel_dp);
Dave Airlieab2c0672009-12-04 10:55:24 +1000562 /* Set up the command byte */
563 if (mode & MODE_I2C_READ)
564 msg[0] = AUX_I2C_READ << 4;
565 else
566 msg[0] = AUX_I2C_WRITE << 4;
567
568 if (!(mode & MODE_I2C_STOP))
569 msg[0] |= AUX_I2C_MOT << 4;
570
571 msg[1] = address >> 8;
572 msg[2] = address;
573
574 switch (mode) {
575 case MODE_I2C_WRITE:
576 msg[3] = 0;
577 msg[4] = write_byte;
578 msg_bytes = 5;
579 reply_bytes = 1;
580 break;
581 case MODE_I2C_READ:
582 msg[3] = 0;
583 msg_bytes = 4;
584 reply_bytes = 2;
585 break;
586 default:
587 msg_bytes = 3;
588 reply_bytes = 1;
589 break;
590 }
591
David Flynn8316f332010-12-08 16:10:21 +0000592 for (retry = 0; retry < 5; retry++) {
593 ret = intel_dp_aux_ch(intel_dp,
594 msg, msg_bytes,
595 reply, reply_bytes);
Dave Airlieab2c0672009-12-04 10:55:24 +1000596 if (ret < 0) {
Dave Airlie3ff99162009-12-08 14:03:47 +1000597 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
Dave Airlieab2c0672009-12-04 10:55:24 +1000598 return ret;
599 }
David Flynn8316f332010-12-08 16:10:21 +0000600
601 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
602 case AUX_NATIVE_REPLY_ACK:
603 /* I2C-over-AUX Reply field is only valid
604 * when paired with AUX ACK.
605 */
606 break;
607 case AUX_NATIVE_REPLY_NACK:
608 DRM_DEBUG_KMS("aux_ch native nack\n");
609 return -EREMOTEIO;
610 case AUX_NATIVE_REPLY_DEFER:
611 udelay(100);
612 continue;
613 default:
614 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
615 reply[0]);
616 return -EREMOTEIO;
617 }
618
Dave Airlieab2c0672009-12-04 10:55:24 +1000619 switch (reply[0] & AUX_I2C_REPLY_MASK) {
620 case AUX_I2C_REPLY_ACK:
621 if (mode == MODE_I2C_READ) {
622 *read_byte = reply[1];
623 }
624 return reply_bytes - 1;
625 case AUX_I2C_REPLY_NACK:
David Flynn8316f332010-12-08 16:10:21 +0000626 DRM_DEBUG_KMS("aux_i2c nack\n");
Dave Airlieab2c0672009-12-04 10:55:24 +1000627 return -EREMOTEIO;
628 case AUX_I2C_REPLY_DEFER:
David Flynn8316f332010-12-08 16:10:21 +0000629 DRM_DEBUG_KMS("aux_i2c defer\n");
Dave Airlieab2c0672009-12-04 10:55:24 +1000630 udelay(100);
631 break;
632 default:
David Flynn8316f332010-12-08 16:10:21 +0000633 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
Dave Airlieab2c0672009-12-04 10:55:24 +1000634 return -EREMOTEIO;
635 }
636 }
David Flynn8316f332010-12-08 16:10:21 +0000637
638 DRM_ERROR("too many retries, giving up\n");
639 return -EREMOTEIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700640}
641
Keith Packard0b5c5412011-09-28 16:41:05 -0700642static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -0700643static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
Keith Packard0b5c5412011-09-28 16:41:05 -0700644
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700645static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100646intel_dp_i2c_init(struct intel_dp *intel_dp,
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800647 struct intel_connector *intel_connector, const char *name)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700648{
Keith Packard0b5c5412011-09-28 16:41:05 -0700649 int ret;
650
Zhenyu Wangd54e9d22009-10-19 15:43:51 +0800651 DRM_DEBUG_KMS("i2c_init %s\n", name);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100652 intel_dp->algo.running = false;
653 intel_dp->algo.address = 0;
654 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700655
Akshay Joshi0206e352011-08-16 15:34:10 -0400656 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100657 intel_dp->adapter.owner = THIS_MODULE;
658 intel_dp->adapter.class = I2C_CLASS_DDC;
Akshay Joshi0206e352011-08-16 15:34:10 -0400659 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100660 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
661 intel_dp->adapter.algo_data = &intel_dp->algo;
662 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
663
Keith Packard0b5c5412011-09-28 16:41:05 -0700664 ironlake_edp_panel_vdd_on(intel_dp);
665 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
Keith Packardbd943152011-09-18 23:09:52 -0700666 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard0b5c5412011-09-28 16:41:05 -0700667 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700668}
669
670static bool
671intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
672 struct drm_display_mode *adjusted_mode)
673{
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100674 struct drm_device *dev = encoder->dev;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100675 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700676 int lane_count, clock;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100677 int max_lane_count = intel_dp_max_lane_count(intel_dp);
678 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
680
Keith Packardd15456d2011-09-18 17:35:47 -0700681 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
682 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
Chris Wilson1d8e1c72010-08-07 11:01:28 +0100683 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
684 mode, adjusted_mode);
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100685 /*
686 * the mode->clock is used to calculate the Data&Link M/N
687 * of the pipe. For the eDP the fixed clock should be used.
688 */
Keith Packardd15456d2011-09-18 17:35:47 -0700689 mode->clock = intel_dp->panel_fixed_mode->clock;
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100690 }
691
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700692 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
693 for (clock = 0; clock <= max_clock; clock++) {
Dave Airliefe27d532010-06-30 11:46:17 +1000694 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700695
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400696 if (intel_dp_link_required(intel_dp, mode->clock)
Zhenyu Wang885a5fb2010-01-12 05:38:31 +0800697 <= link_avail) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100698 intel_dp->link_bw = bws[clock];
699 intel_dp->lane_count = lane_count;
700 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
Zhao Yakui28c97732009-10-09 11:39:41 +0800701 DRM_DEBUG_KMS("Display port link bw %02x lane "
702 "count %d clock %d\n",
Chris Wilsonea5b2132010-08-04 13:50:23 +0100703 intel_dp->link_bw, intel_dp->lane_count,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700704 adjusted_mode->clock);
705 return true;
706 }
707 }
708 }
Dave Airliefe27d532010-06-30 11:46:17 +1000709
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700710 return false;
711}
712
713struct intel_dp_m_n {
714 uint32_t tu;
715 uint32_t gmch_m;
716 uint32_t gmch_n;
717 uint32_t link_m;
718 uint32_t link_n;
719};
720
721static void
722intel_reduce_ratio(uint32_t *num, uint32_t *den)
723{
724 while (*num > 0xffffff || *den > 0xffffff) {
725 *num >>= 1;
726 *den >>= 1;
727 }
728}
729
730static void
Zhao Yakui36e83a12010-06-12 14:32:21 +0800731intel_dp_compute_m_n(int bpp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700732 int nlanes,
733 int pixel_clock,
734 int link_clock,
735 struct intel_dp_m_n *m_n)
736{
737 m_n->tu = 64;
Zhao Yakui36e83a12010-06-12 14:32:21 +0800738 m_n->gmch_m = (pixel_clock * bpp) >> 3;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700739 m_n->gmch_n = link_clock * nlanes;
740 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
741 m_n->link_m = pixel_clock;
742 m_n->link_n = link_clock;
743 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
744}
745
746void
747intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
748 struct drm_display_mode *adjusted_mode)
749{
750 struct drm_device *dev = crtc->dev;
751 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800752 struct drm_encoder *encoder;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700753 struct drm_i915_private *dev_priv = dev->dev_private;
754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes858fa0352011-06-24 12:19:24 -0700755 int lane_count = 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700756 struct intel_dp_m_n m_n;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800757 int pipe = intel_crtc->pipe;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700758
759 /*
Eric Anholt21d40d32010-03-25 11:11:14 -0700760 * Find the lane count in the intel_encoder private
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700761 */
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800762 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100763 struct intel_dp *intel_dp;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700764
Dan Carpenterd8201ab2010-05-07 10:39:00 +0200765 if (encoder->crtc != crtc)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700766 continue;
767
Chris Wilsonea5b2132010-08-04 13:50:23 +0100768 intel_dp = enc_to_intel_dp(encoder);
Keith Packard417e8222011-11-01 19:54:11 -0700769 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || is_pch_edp(intel_dp)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100770 lane_count = intel_dp->lane_count;
Jesse Barnes51190662010-10-07 16:01:08 -0700771 break;
Keith Packard417e8222011-11-01 19:54:11 -0700772 } else if (is_cpu_edp(intel_dp)) {
Jesse Barnes51190662010-10-07 16:01:08 -0700773 lane_count = dev_priv->edp.lanes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700774 break;
775 }
776 }
777
778 /*
779 * Compute the GMCH and Link ratios. The '3' here is
780 * the number of bytes_per_pixel post-LUT, which we always
781 * set up for 8-bits of R/G/B, or 3 bytes total.
782 */
Jesse Barnes858fa0352011-06-24 12:19:24 -0700783 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700784 mode->clock, adjusted_mode->clock, &m_n);
785
Eric Anholtc619eed2010-01-28 16:45:52 -0800786 if (HAS_PCH_SPLIT(dev)) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800787 I915_WRITE(TRANSDATA_M1(pipe),
788 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
789 m_n.gmch_m);
790 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
791 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
792 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700793 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800794 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
795 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
796 m_n.gmch_m);
797 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
798 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
799 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700800 }
801}
802
Keith Packardf01eca22011-09-28 16:48:10 -0700803static void ironlake_edp_pll_on(struct drm_encoder *encoder);
804static void ironlake_edp_pll_off(struct drm_encoder *encoder);
805
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700806static void
807intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
808 struct drm_display_mode *adjusted_mode)
809{
Zhenyu Wange3421a12010-04-08 09:43:27 +0800810 struct drm_device *dev = encoder->dev;
Keith Packard417e8222011-11-01 19:54:11 -0700811 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100812 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Chris Wilson4ef69c72010-09-09 15:14:28 +0100813 struct drm_crtc *crtc = intel_dp->base.base.crtc;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
815
Keith Packardf01eca22011-09-28 16:48:10 -0700816 /* Turn on the eDP PLL if needed */
817 if (is_edp(intel_dp)) {
818 if (!is_pch_edp(intel_dp))
819 ironlake_edp_pll_on(encoder);
820 else
821 ironlake_edp_pll_off(encoder);
822 }
823
Keith Packard417e8222011-11-01 19:54:11 -0700824 /*
825 * There are three kinds of DP registers:
826 *
827 * IBX PCH
828 * CPU
829 * CPT PCH
830 *
831 * IBX PCH and CPU are the same for almost everything,
832 * except that the CPU DP PLL is configured in this
833 * register
834 *
835 * CPT PCH is quite different, having many bits moved
836 * to the TRANS_DP_CTL register instead. That
837 * configuration happens (oddly) in ironlake_pch_enable
838 */
Adam Jackson9c9e7922010-04-05 17:57:59 -0400839
Keith Packard417e8222011-11-01 19:54:11 -0700840 /* Preserve the BIOS-computed detected bit. This is
841 * supposed to be read-only.
842 */
843 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
844 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700845
Keith Packard417e8222011-11-01 19:54:11 -0700846 /* Handle DP bits in common between all three register formats */
847
848 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700849
Chris Wilsonea5b2132010-08-04 13:50:23 +0100850 switch (intel_dp->lane_count) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700851 case 1:
Chris Wilsonea5b2132010-08-04 13:50:23 +0100852 intel_dp->DP |= DP_PORT_WIDTH_1;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700853 break;
854 case 2:
Chris Wilsonea5b2132010-08-04 13:50:23 +0100855 intel_dp->DP |= DP_PORT_WIDTH_2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700856 break;
857 case 4:
Chris Wilsonea5b2132010-08-04 13:50:23 +0100858 intel_dp->DP |= DP_PORT_WIDTH_4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700859 break;
860 }
Wu Fengguange0dac652011-09-05 14:25:34 +0800861 if (intel_dp->has_audio) {
862 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
863 pipe_name(intel_crtc->pipe));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100864 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Wu Fengguange0dac652011-09-05 14:25:34 +0800865 intel_write_eld(encoder, adjusted_mode);
866 }
Chris Wilsonea5b2132010-08-04 13:50:23 +0100867 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
868 intel_dp->link_configuration[0] = intel_dp->link_bw;
869 intel_dp->link_configuration[1] = intel_dp->lane_count;
Adam Jacksona2cab1b2011-07-12 17:38:05 -0400870 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700871 /*
Adam Jackson9962c922010-05-13 14:45:42 -0400872 * Check for DPCD version > 1.1 and enhanced framing support
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700873 */
Jesse Barnes7183dc22011-07-07 11:10:58 -0700874 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
875 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100876 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700877 }
878
Keith Packard417e8222011-11-01 19:54:11 -0700879 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800880
Keith Packard417e8222011-11-01 19:54:11 -0700881 if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
882 intel_dp->DP |= intel_dp->color_range;
883
884 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
885 intel_dp->DP |= DP_SYNC_HS_HIGH;
886 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
887 intel_dp->DP |= DP_SYNC_VS_HIGH;
888 intel_dp->DP |= DP_LINK_TRAIN_OFF;
889
890 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
891 intel_dp->DP |= DP_ENHANCED_FRAMING;
892
893 if (intel_crtc->pipe == 1)
894 intel_dp->DP |= DP_PIPEB_SELECT;
895
896 if (is_cpu_edp(intel_dp)) {
897 /* don't miss out required setting for eDP */
898 intel_dp->DP |= DP_PLL_ENABLE;
899 if (adjusted_mode->clock < 200000)
900 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
901 else
902 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
903 }
904 } else {
905 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800906 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700907}
908
Keith Packardbd943152011-09-18 23:09:52 -0700909static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
910{
911 unsigned long off_time;
912 unsigned long delay;
Keith Packard32ce6972011-09-29 16:51:26 -0700913
Keith Packardbd943152011-09-18 23:09:52 -0700914 DRM_DEBUG_KMS("Wait for panel power off time\n");
Keith Packard32ce6972011-09-29 16:51:26 -0700915
916 if (ironlake_edp_have_panel_power(intel_dp) ||
917 ironlake_edp_have_panel_vdd(intel_dp))
918 {
919 DRM_DEBUG_KMS("Panel still on, no delay needed\n");
920 return;
921 }
922
Keith Packardbd943152011-09-18 23:09:52 -0700923 off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
924 if (time_after(jiffies, off_time)) {
925 DRM_DEBUG_KMS("Time already passed");
926 return;
927 }
928 delay = jiffies_to_msecs(off_time - jiffies);
929 if (delay > intel_dp->panel_power_down_delay)
930 delay = intel_dp->panel_power_down_delay;
931 DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
932 msleep(delay);
933}
934
Keith Packard832dd3c2011-11-01 19:34:06 -0700935/* Read the current pp_control value, unlocking the register if it
936 * is locked
937 */
938
939static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
940{
941 u32 control = I915_READ(PCH_PP_CONTROL);
942
943 control &= ~PANEL_UNLOCK_MASK;
944 control |= PANEL_UNLOCK_REGS;
945 return control;
946}
947
Jesse Barnes5d613502011-01-24 17:10:54 -0800948static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
949{
950 struct drm_device *dev = intel_dp->base.base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 pp;
953
Keith Packard97af61f572011-09-28 16:23:51 -0700954 if (!is_edp(intel_dp))
955 return;
Keith Packardf01eca22011-09-28 16:48:10 -0700956 DRM_DEBUG_KMS("Turn eDP VDD on\n");
Jesse Barnes5d613502011-01-24 17:10:54 -0800957
Keith Packardbd943152011-09-18 23:09:52 -0700958 WARN(intel_dp->want_panel_vdd,
959 "eDP VDD already requested on\n");
960
961 intel_dp->want_panel_vdd = true;
962 if (ironlake_edp_have_panel_vdd(intel_dp)) {
963 DRM_DEBUG_KMS("eDP VDD already on\n");
964 return;
965 }
966
967 ironlake_wait_panel_off(intel_dp);
Keith Packard832dd3c2011-11-01 19:34:06 -0700968 pp = ironlake_get_pp_control(dev_priv);
Jesse Barnes5d613502011-01-24 17:10:54 -0800969 pp |= EDP_FORCE_VDD;
970 I915_WRITE(PCH_PP_CONTROL, pp);
971 POSTING_READ(PCH_PP_CONTROL);
Keith Packardf01eca22011-09-28 16:48:10 -0700972 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
973 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
Keith Packardebf33b12011-09-29 15:53:27 -0700974
975 /*
976 * If the panel wasn't on, delay before accessing aux channel
977 */
978 if (!ironlake_edp_have_panel_power(intel_dp)) {
Keith Packardbd943152011-09-18 23:09:52 -0700979 DRM_DEBUG_KMS("eDP was not running\n");
Keith Packardf01eca22011-09-28 16:48:10 -0700980 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -0700981 }
Jesse Barnes5d613502011-01-24 17:10:54 -0800982}
983
Keith Packardbd943152011-09-18 23:09:52 -0700984static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -0800985{
986 struct drm_device *dev = intel_dp->base.base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 u32 pp;
989
Keith Packardbd943152011-09-18 23:09:52 -0700990 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
Keith Packard832dd3c2011-11-01 19:34:06 -0700991 pp = ironlake_get_pp_control(dev_priv);
Keith Packardbd943152011-09-18 23:09:52 -0700992 pp &= ~EDP_FORCE_VDD;
993 I915_WRITE(PCH_PP_CONTROL, pp);
994 POSTING_READ(PCH_PP_CONTROL);
Jesse Barnes5d613502011-01-24 17:10:54 -0800995
Keith Packardbd943152011-09-18 23:09:52 -0700996 /* Make sure sequencer is idle before allowing subsequent activity */
997 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
998 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
999 intel_dp->panel_off_jiffies = jiffies;
1000 }
1001}
1002
1003static void ironlake_panel_vdd_work(struct work_struct *__work)
1004{
1005 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1006 struct intel_dp, panel_vdd_work);
1007 struct drm_device *dev = intel_dp->base.base.dev;
1008
Keith Packard627f7672011-10-31 11:30:10 -07001009 mutex_lock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001010 ironlake_panel_vdd_off_sync(intel_dp);
Keith Packard627f7672011-10-31 11:30:10 -07001011 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001012}
1013
1014static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1015{
Keith Packard97af61f572011-09-28 16:23:51 -07001016 if (!is_edp(intel_dp))
1017 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08001018
Keith Packardbd943152011-09-18 23:09:52 -07001019 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1020 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1021
1022 intel_dp->want_panel_vdd = false;
1023
1024 if (sync) {
1025 ironlake_panel_vdd_off_sync(intel_dp);
1026 } else {
1027 /*
1028 * Queue the timer to fire a long
1029 * time from now (relative to the power down delay)
1030 * to keep the panel power up across a sequence of operations
1031 */
1032 schedule_delayed_work(&intel_dp->panel_vdd_work,
1033 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1034 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001035}
1036
Jesse Barnes7eaf5542010-09-08 12:41:59 -07001037/* Returns true if the panel was already on when called */
Keith Packard86a30732011-10-20 13:40:33 -07001038static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001039{
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001040 struct drm_device *dev = intel_dp->base.base.dev;
Jesse Barnes9934c132010-07-22 13:18:19 -07001041 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001042 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
Jesse Barnes9934c132010-07-22 13:18:19 -07001043
Keith Packard97af61f572011-09-28 16:23:51 -07001044 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07001045 return;
Keith Packardebf33b12011-09-29 15:53:27 -07001046 if (ironlake_edp_have_panel_power(intel_dp))
Keith Packard7d639f32011-09-29 16:05:34 -07001047 return;
Jesse Barnes9934c132010-07-22 13:18:19 -07001048
Keith Packardbd943152011-09-18 23:09:52 -07001049 ironlake_wait_panel_off(intel_dp);
Keith Packard832dd3c2011-11-01 19:34:06 -07001050 pp = ironlake_get_pp_control(dev_priv);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001051
Keith Packard05ce1a42011-09-29 16:33:01 -07001052 if (IS_GEN5(dev)) {
1053 /* ILK workaround: disable reset around power sequence */
1054 pp &= ~PANEL_POWER_RESET;
1055 I915_WRITE(PCH_PP_CONTROL, pp);
1056 POSTING_READ(PCH_PP_CONTROL);
1057 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001058
Keith Packard1c0ae802011-09-19 13:59:29 -07001059 pp |= POWER_TARGET_ON;
Jesse Barnes9934c132010-07-22 13:18:19 -07001060 I915_WRITE(PCH_PP_CONTROL, pp);
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001061 POSTING_READ(PCH_PP_CONTROL);
Jesse Barnes9934c132010-07-22 13:18:19 -07001062
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001063 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
1064 5000))
Chris Wilson913d8d12010-08-07 11:01:35 +01001065 DRM_ERROR("panel on wait timed out: 0x%08x\n",
1066 I915_READ(PCH_PP_STATUS));
Jesse Barnes9934c132010-07-22 13:18:19 -07001067
Keith Packard05ce1a42011-09-29 16:33:01 -07001068 if (IS_GEN5(dev)) {
1069 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1070 I915_WRITE(PCH_PP_CONTROL, pp);
1071 POSTING_READ(PCH_PP_CONTROL);
1072 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001073}
1074
Keith Packardf01eca22011-09-28 16:48:10 -07001075static void ironlake_edp_panel_off(struct drm_encoder *encoder)
Jesse Barnes9934c132010-07-22 13:18:19 -07001076{
Keith Packardf01eca22011-09-28 16:48:10 -07001077 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1078 struct drm_device *dev = encoder->dev;
Jesse Barnes9934c132010-07-22 13:18:19 -07001079 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001080 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
1081 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
Jesse Barnes9934c132010-07-22 13:18:19 -07001082
Keith Packard97af61f572011-09-28 16:23:51 -07001083 if (!is_edp(intel_dp))
1084 return;
Keith Packard832dd3c2011-11-01 19:34:06 -07001085 pp = ironlake_get_pp_control(dev_priv);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001086
Keith Packard05ce1a42011-09-29 16:33:01 -07001087 if (IS_GEN5(dev)) {
1088 /* ILK workaround: disable reset around power sequence */
1089 pp &= ~PANEL_POWER_RESET;
1090 I915_WRITE(PCH_PP_CONTROL, pp);
1091 POSTING_READ(PCH_PP_CONTROL);
1092 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001093
Keith Packardbd943152011-09-18 23:09:52 -07001094 intel_dp->panel_off_jiffies = jiffies;
Jesse Barnes9934c132010-07-22 13:18:19 -07001095
Keith Packard05ce1a42011-09-29 16:33:01 -07001096 if (IS_GEN5(dev)) {
1097 pp &= ~POWER_TARGET_ON;
1098 I915_WRITE(PCH_PP_CONTROL, pp);
1099 POSTING_READ(PCH_PP_CONTROL);
1100 pp &= ~POWER_TARGET_ON;
1101 I915_WRITE(PCH_PP_CONTROL, pp);
1102 POSTING_READ(PCH_PP_CONTROL);
1103 msleep(intel_dp->panel_power_cycle_delay);
Jesse Barnes9934c132010-07-22 13:18:19 -07001104
Keith Packard05ce1a42011-09-29 16:33:01 -07001105 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
1106 DRM_ERROR("panel off wait timed out: 0x%08x\n",
1107 I915_READ(PCH_PP_STATUS));
1108
1109 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1110 I915_WRITE(PCH_PP_CONTROL, pp);
1111 POSTING_READ(PCH_PP_CONTROL);
1112 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001113}
1114
Keith Packard86a30732011-10-20 13:40:33 -07001115static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001116{
Keith Packardf01eca22011-09-28 16:48:10 -07001117 struct drm_device *dev = intel_dp->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 u32 pp;
1120
Keith Packardf01eca22011-09-28 16:48:10 -07001121 if (!is_edp(intel_dp))
1122 return;
1123
Zhao Yakui28c97732009-10-09 11:39:41 +08001124 DRM_DEBUG_KMS("\n");
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001125 /*
1126 * If we enable the backlight right away following a panel power
1127 * on, we may see slight flicker as the panel syncs with the eDP
1128 * link. So delay a bit to make sure the image is solid before
1129 * allowing it to appear.
1130 */
Keith Packardf01eca22011-09-28 16:48:10 -07001131 msleep(intel_dp->backlight_on_delay);
Keith Packard832dd3c2011-11-01 19:34:06 -07001132 pp = ironlake_get_pp_control(dev_priv);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001133 pp |= EDP_BLC_ENABLE;
1134 I915_WRITE(PCH_PP_CONTROL, pp);
Keith Packardf01eca22011-09-28 16:48:10 -07001135 POSTING_READ(PCH_PP_CONTROL);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001136}
1137
Keith Packard86a30732011-10-20 13:40:33 -07001138static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001139{
Keith Packardf01eca22011-09-28 16:48:10 -07001140 struct drm_device *dev = intel_dp->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 u32 pp;
1143
Keith Packardf01eca22011-09-28 16:48:10 -07001144 if (!is_edp(intel_dp))
1145 return;
1146
Zhao Yakui28c97732009-10-09 11:39:41 +08001147 DRM_DEBUG_KMS("\n");
Keith Packard832dd3c2011-11-01 19:34:06 -07001148 pp = ironlake_get_pp_control(dev_priv);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001149 pp &= ~EDP_BLC_ENABLE;
1150 I915_WRITE(PCH_PP_CONTROL, pp);
Keith Packardf01eca22011-09-28 16:48:10 -07001151 POSTING_READ(PCH_PP_CONTROL);
1152 msleep(intel_dp->backlight_off_delay);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001153}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001154
Jesse Barnesd240f202010-08-13 15:43:26 -07001155static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1156{
1157 struct drm_device *dev = encoder->dev;
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1159 u32 dpa_ctl;
1160
1161 DRM_DEBUG_KMS("\n");
1162 dpa_ctl = I915_READ(DP_A);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001163 dpa_ctl |= DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001164 I915_WRITE(DP_A, dpa_ctl);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001165 POSTING_READ(DP_A);
1166 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07001167}
1168
1169static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1170{
1171 struct drm_device *dev = encoder->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 dpa_ctl;
1174
1175 dpa_ctl = I915_READ(DP_A);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001176 dpa_ctl &= ~DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001177 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson1af5fa12010-09-08 21:07:28 +01001178 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07001179 udelay(200);
1180}
1181
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001182/* If the sink supports it, try to set the power state appropriately */
1183static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1184{
1185 int ret, i;
1186
1187 /* Should have a valid DPCD by this point */
1188 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1189 return;
1190
1191 if (mode != DRM_MODE_DPMS_ON) {
1192 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1193 DP_SET_POWER_D3);
1194 if (ret != 1)
1195 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1196 } else {
1197 /*
1198 * When turning on, we need to retry for 1ms to give the sink
1199 * time to wake up.
1200 */
1201 for (i = 0; i < 3; i++) {
1202 ret = intel_dp_aux_native_write_1(intel_dp,
1203 DP_SET_POWER,
1204 DP_SET_POWER_D0);
1205 if (ret == 1)
1206 break;
1207 msleep(1);
1208 }
1209 }
1210}
1211
Jesse Barnesd240f202010-08-13 15:43:26 -07001212static void intel_dp_prepare(struct drm_encoder *encoder)
1213{
1214 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jesse Barnesd240f202010-08-13 15:43:26 -07001215
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001216 /* Wake up the sink first */
Keith Packardf58ff852011-09-28 16:44:14 -07001217 ironlake_edp_panel_vdd_on(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001218 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Keith Packardbd943152011-09-18 23:09:52 -07001219 ironlake_edp_panel_vdd_off(intel_dp, false);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001220
Keith Packardf01eca22011-09-28 16:48:10 -07001221 /* Make sure the panel is off before trying to
1222 * change the mode
1223 */
1224 ironlake_edp_backlight_off(intel_dp);
Jesse Barnes736085b2010-10-08 10:35:55 -07001225 intel_dp_link_down(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001226 ironlake_edp_panel_off(encoder);
Jesse Barnesd240f202010-08-13 15:43:26 -07001227}
1228
1229static void intel_dp_commit(struct drm_encoder *encoder)
1230{
1231 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jesse Barnesd4270e52011-10-11 10:43:02 -07001232 struct drm_device *dev = encoder->dev;
1233 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
Jesse Barnesd240f202010-08-13 15:43:26 -07001234
Keith Packard97af61f572011-09-28 16:23:51 -07001235 ironlake_edp_panel_vdd_on(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001236 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Jesse Barnes33a34e42010-09-08 12:42:02 -07001237 intel_dp_start_link_train(intel_dp);
Keith Packard97af61f572011-09-28 16:23:51 -07001238 ironlake_edp_panel_on(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001239 ironlake_edp_panel_vdd_off(intel_dp, true);
Jesse Barnes33a34e42010-09-08 12:42:02 -07001240
1241 intel_dp_complete_link_train(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001242 ironlake_edp_backlight_on(intel_dp);
Keith Packardd2b996a2011-07-25 22:37:51 -07001243
1244 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
Jesse Barnesd4270e52011-10-11 10:43:02 -07001245
1246 if (HAS_PCH_CPT(dev))
1247 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnesd240f202010-08-13 15:43:26 -07001248}
1249
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001250static void
1251intel_dp_dpms(struct drm_encoder *encoder, int mode)
1252{
Chris Wilsonea5b2132010-08-04 13:50:23 +01001253 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08001254 struct drm_device *dev = encoder->dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001255 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001256 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001257
1258 if (mode != DRM_MODE_DPMS_ON) {
Keith Packard245e2702011-10-05 19:53:09 -07001259 ironlake_edp_panel_vdd_on(intel_dp);
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001260 if (is_edp(intel_dp))
Keith Packardf01eca22011-09-28 16:48:10 -07001261 ironlake_edp_backlight_off(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001262 intel_dp_sink_dpms(intel_dp, mode);
Jesse Barnes736085b2010-10-08 10:35:55 -07001263 intel_dp_link_down(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001264 ironlake_edp_panel_off(encoder);
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001265 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
Jesse Barnesd240f202010-08-13 15:43:26 -07001266 ironlake_edp_pll_off(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07001267 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001268 } else {
Keith Packard97af61f572011-09-28 16:23:51 -07001269 ironlake_edp_panel_vdd_on(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001270 intel_dp_sink_dpms(intel_dp, mode);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001271 if (!(dp_reg & DP_PORT_EN)) {
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001272 intel_dp_start_link_train(intel_dp);
Keith Packard97af61f572011-09-28 16:23:51 -07001273 ironlake_edp_panel_on(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001274 ironlake_edp_panel_vdd_off(intel_dp, true);
Jesse Barnes33a34e42010-09-08 12:42:02 -07001275 intel_dp_complete_link_train(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001276 ironlake_edp_backlight_on(intel_dp);
Keith Packardbee7eb22011-09-28 16:28:00 -07001277 } else
Keith Packardbd943152011-09-18 23:09:52 -07001278 ironlake_edp_panel_vdd_off(intel_dp, false);
1279 ironlake_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001280 }
Keith Packardd2b996a2011-07-25 22:37:51 -07001281 intel_dp->dpms_mode = mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001282}
1283
1284/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001285 * Native read with retry for link status and receiver capability reads for
1286 * cases where the sink may still be asleep.
1287 */
1288static bool
1289intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1290 uint8_t *recv, int recv_bytes)
1291{
1292 int ret, i;
1293
1294 /*
1295 * Sinks are *supposed* to come up within 1ms from an off state,
1296 * but we're also supposed to retry 3 times per the spec.
1297 */
1298 for (i = 0; i < 3; i++) {
1299 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1300 recv_bytes);
1301 if (ret == recv_bytes)
1302 return true;
1303 msleep(1);
1304 }
1305
1306 return false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001307}
1308
1309/*
1310 * Fetch AUX CH registers 0x202 - 0x207 which contain
1311 * link status information
1312 */
1313static bool
Keith Packard93f62da2011-11-01 19:45:03 -07001314intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001315{
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001316 return intel_dp_aux_native_read_retry(intel_dp,
1317 DP_LANE0_1_STATUS,
Keith Packard93f62da2011-11-01 19:45:03 -07001318 link_status,
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001319 DP_LINK_STATUS_SIZE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001320}
1321
1322static uint8_t
1323intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1324 int r)
1325{
1326 return link_status[r - DP_LANE0_1_STATUS];
1327}
1328
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001329static uint8_t
Keith Packard93f62da2011-11-01 19:45:03 -07001330intel_get_adjust_request_voltage(uint8_t adjust_request[2],
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001331 int lane)
1332{
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001333 int s = ((lane & 1) ?
1334 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1335 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
Keith Packard93f62da2011-11-01 19:45:03 -07001336 uint8_t l = adjust_request[lane>>1];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001337
1338 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1339}
1340
1341static uint8_t
Keith Packard93f62da2011-11-01 19:45:03 -07001342intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001343 int lane)
1344{
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001345 int s = ((lane & 1) ?
1346 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1347 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
Keith Packard93f62da2011-11-01 19:45:03 -07001348 uint8_t l = adjust_request[lane>>1];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001349
1350 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1351}
1352
1353
1354#if 0
1355static char *voltage_names[] = {
1356 "0.4V", "0.6V", "0.8V", "1.2V"
1357};
1358static char *pre_emph_names[] = {
1359 "0dB", "3.5dB", "6dB", "9.5dB"
1360};
1361static char *link_train_names[] = {
1362 "pattern 1", "pattern 2", "idle", "off"
1363};
1364#endif
1365
1366/*
1367 * These are source-specific values; current Intel hardware supports
1368 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1369 */
1370#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
Keith Packard417e8222011-11-01 19:54:11 -07001371#define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001372
1373static uint8_t
1374intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1375{
1376 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1377 case DP_TRAIN_VOLTAGE_SWING_400:
1378 return DP_TRAIN_PRE_EMPHASIS_6;
1379 case DP_TRAIN_VOLTAGE_SWING_600:
1380 return DP_TRAIN_PRE_EMPHASIS_6;
1381 case DP_TRAIN_VOLTAGE_SWING_800:
1382 return DP_TRAIN_PRE_EMPHASIS_3_5;
1383 case DP_TRAIN_VOLTAGE_SWING_1200:
1384 default:
1385 return DP_TRAIN_PRE_EMPHASIS_0;
1386 }
1387}
1388
1389static void
Keith Packard93f62da2011-11-01 19:45:03 -07001390intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001391{
Keith Packard93f62da2011-11-01 19:45:03 -07001392 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001393 uint8_t v = 0;
1394 uint8_t p = 0;
1395 int lane;
Keith Packard93f62da2011-11-01 19:45:03 -07001396 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1397 int voltage_max;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001398
Jesse Barnes33a34e42010-09-08 12:42:02 -07001399 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Keith Packard93f62da2011-11-01 19:45:03 -07001400 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1401 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001402
1403 if (this_v > v)
1404 v = this_v;
1405 if (this_p > p)
1406 p = this_p;
1407 }
1408
Keith Packard417e8222011-11-01 19:54:11 -07001409 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1410 voltage_max = I830_DP_VOLTAGE_MAX_CPT;
1411 else
1412 voltage_max = I830_DP_VOLTAGE_MAX;
1413 if (v >= voltage_max)
1414 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001415
1416 if (p >= intel_dp_pre_emphasis_max(v))
1417 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1418
1419 for (lane = 0; lane < 4; lane++)
Jesse Barnes33a34e42010-09-08 12:42:02 -07001420 intel_dp->train_set[lane] = v | p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001421}
1422
1423static uint32_t
Keith Packard93f62da2011-11-01 19:45:03 -07001424intel_dp_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001425{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001426 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001427
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001428 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001429 case DP_TRAIN_VOLTAGE_SWING_400:
1430 default:
1431 signal_levels |= DP_VOLTAGE_0_4;
1432 break;
1433 case DP_TRAIN_VOLTAGE_SWING_600:
1434 signal_levels |= DP_VOLTAGE_0_6;
1435 break;
1436 case DP_TRAIN_VOLTAGE_SWING_800:
1437 signal_levels |= DP_VOLTAGE_0_8;
1438 break;
1439 case DP_TRAIN_VOLTAGE_SWING_1200:
1440 signal_levels |= DP_VOLTAGE_1_2;
1441 break;
1442 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001443 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001444 case DP_TRAIN_PRE_EMPHASIS_0:
1445 default:
1446 signal_levels |= DP_PRE_EMPHASIS_0;
1447 break;
1448 case DP_TRAIN_PRE_EMPHASIS_3_5:
1449 signal_levels |= DP_PRE_EMPHASIS_3_5;
1450 break;
1451 case DP_TRAIN_PRE_EMPHASIS_6:
1452 signal_levels |= DP_PRE_EMPHASIS_6;
1453 break;
1454 case DP_TRAIN_PRE_EMPHASIS_9_5:
1455 signal_levels |= DP_PRE_EMPHASIS_9_5;
1456 break;
1457 }
1458 return signal_levels;
1459}
1460
Zhenyu Wange3421a12010-04-08 09:43:27 +08001461/* Gen6's DP voltage swing and pre-emphasis control */
1462static uint32_t
1463intel_gen6_edp_signal_levels(uint8_t train_set)
1464{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001465 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1466 DP_TRAIN_PRE_EMPHASIS_MASK);
1467 switch (signal_levels) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08001468 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001469 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1470 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1471 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1472 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001473 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001474 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1475 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001476 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001477 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1478 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001479 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001480 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1481 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001482 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001483 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1484 "0x%x\n", signal_levels);
1485 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001486 }
1487}
1488
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001489static uint8_t
1490intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1491 int lane)
1492{
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001493 int s = (lane & 1) * 4;
Keith Packard93f62da2011-11-01 19:45:03 -07001494 uint8_t l = link_status[lane>>1];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001495
1496 return (l >> s) & 0xf;
1497}
1498
1499/* Check for clock recovery is done on all channels */
1500static bool
1501intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1502{
1503 int lane;
1504 uint8_t lane_status;
1505
1506 for (lane = 0; lane < lane_count; lane++) {
1507 lane_status = intel_get_lane_status(link_status, lane);
1508 if ((lane_status & DP_LANE_CR_DONE) == 0)
1509 return false;
1510 }
1511 return true;
1512}
1513
1514/* Check to see if channel eq is done on all channels */
1515#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1516 DP_LANE_CHANNEL_EQ_DONE|\
1517 DP_LANE_SYMBOL_LOCKED)
1518static bool
Keith Packard93f62da2011-11-01 19:45:03 -07001519intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001520{
1521 uint8_t lane_align;
1522 uint8_t lane_status;
1523 int lane;
1524
Keith Packard93f62da2011-11-01 19:45:03 -07001525 lane_align = intel_dp_link_status(link_status,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001526 DP_LANE_ALIGN_STATUS_UPDATED);
1527 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1528 return false;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001529 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Keith Packard93f62da2011-11-01 19:45:03 -07001530 lane_status = intel_get_lane_status(link_status, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001531 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1532 return false;
1533 }
1534 return true;
1535}
1536
1537static bool
Chris Wilsonea5b2132010-08-04 13:50:23 +01001538intel_dp_set_link_train(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001539 uint32_t dp_reg_value,
Chris Wilson58e10eb2010-10-03 10:56:11 +01001540 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001541{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001542 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001543 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001544 int ret;
1545
Chris Wilsonea5b2132010-08-04 13:50:23 +01001546 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1547 POSTING_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001548
Chris Wilsonea5b2132010-08-04 13:50:23 +01001549 intel_dp_aux_native_write_1(intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001550 DP_TRAINING_PATTERN_SET,
1551 dp_train_pat);
1552
Chris Wilsonea5b2132010-08-04 13:50:23 +01001553 ret = intel_dp_aux_native_write(intel_dp,
Chris Wilson58e10eb2010-10-03 10:56:11 +01001554 DP_TRAINING_LANE0_SET,
1555 intel_dp->train_set, 4);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001556 if (ret != 4)
1557 return false;
1558
1559 return true;
1560}
1561
Jesse Barnes33a34e42010-09-08 12:42:02 -07001562/* Enable corresponding port and start training pattern 1 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001563static void
Jesse Barnes33a34e42010-09-08 12:42:02 -07001564intel_dp_start_link_train(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001565{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001566 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001567 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001568 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001569 int i;
1570 uint8_t voltage;
1571 bool clock_recovery = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001572 int tries;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001573 u32 reg;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001574 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001575
Adam Jacksone8519462011-07-21 17:48:38 -04001576 /*
1577 * On CPT we have to enable the port in training pattern 1, which
1578 * will happen below in intel_dp_set_link_train. Otherwise, enable
1579 * the port and wait for it to become active.
1580 */
1581 if (!HAS_PCH_CPT(dev)) {
1582 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1583 POSTING_READ(intel_dp->output_reg);
1584 intel_wait_for_vblank(dev, intel_crtc->pipe);
1585 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001586
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001587 /* Write the link configuration data */
1588 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1589 intel_dp->link_configuration,
1590 DP_LINK_CONFIGURATION_SIZE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001591
1592 DP |= DP_PORT_EN;
Adam Jackson82d16552011-10-14 17:22:26 -04001593 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001594 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1595 else
1596 DP &= ~DP_LINK_TRAIN_MASK;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001597 memset(intel_dp->train_set, 0, 4);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001598 voltage = 0xff;
1599 tries = 0;
1600 clock_recovery = false;
1601 for (;;) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001602 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
Keith Packard93f62da2011-11-01 19:45:03 -07001603 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08001604 uint32_t signal_levels;
Keith Packard417e8222011-11-01 19:54:11 -07001605
1606 if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001607 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001608 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1609 } else {
Keith Packard93f62da2011-11-01 19:45:03 -07001610 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1611 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001612 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1613 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001614
Adam Jackson82d16552011-10-14 17:22:26 -04001615 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001616 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1617 else
1618 reg = DP | DP_LINK_TRAIN_PAT_1;
1619
Chris Wilsonea5b2132010-08-04 13:50:23 +01001620 if (!intel_dp_set_link_train(intel_dp, reg,
Adam Jackson81055852011-07-21 17:48:37 -04001621 DP_TRAINING_PATTERN_1 |
1622 DP_LINK_SCRAMBLING_DISABLE))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001623 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001624 /* Set training pattern 1 */
1625
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001626 udelay(100);
Keith Packard93f62da2011-11-01 19:45:03 -07001627 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1628 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001629 break;
Keith Packard93f62da2011-11-01 19:45:03 -07001630 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001631
Keith Packard93f62da2011-11-01 19:45:03 -07001632 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1633 DRM_DEBUG_KMS("clock recovery OK\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001634 clock_recovery = true;
1635 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001636 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001637
1638 /* Check to see if we've tried the max voltage */
1639 for (i = 0; i < intel_dp->lane_count; i++)
1640 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1641 break;
1642 if (i == intel_dp->lane_count)
1643 break;
1644
1645 /* Check to see if we've tried the same voltage 5 times */
1646 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1647 ++tries;
1648 if (tries == 5)
1649 break;
1650 } else
1651 tries = 0;
1652 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1653
1654 /* Compute new intel_dp->train_set as requested by target */
Keith Packard93f62da2011-11-01 19:45:03 -07001655 intel_get_adjust_train(intel_dp, link_status);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001656 }
1657
Jesse Barnes33a34e42010-09-08 12:42:02 -07001658 intel_dp->DP = DP;
1659}
1660
1661static void
1662intel_dp_complete_link_train(struct intel_dp *intel_dp)
1663{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001664 struct drm_device *dev = intel_dp->base.base.dev;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 bool channel_eq = false;
Jesse Barnes37f80972011-01-05 14:45:24 -08001667 int tries, cr_tries;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001668 u32 reg;
1669 uint32_t DP = intel_dp->DP;
1670
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001671 /* channel equalization */
1672 tries = 0;
Jesse Barnes37f80972011-01-05 14:45:24 -08001673 cr_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001674 channel_eq = false;
1675 for (;;) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001676 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
Zhenyu Wange3421a12010-04-08 09:43:27 +08001677 uint32_t signal_levels;
Keith Packard93f62da2011-11-01 19:45:03 -07001678 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08001679
Jesse Barnes37f80972011-01-05 14:45:24 -08001680 if (cr_tries > 5) {
1681 DRM_ERROR("failed to train DP, aborting\n");
1682 intel_dp_link_down(intel_dp);
1683 break;
1684 }
1685
Keith Packard417e8222011-11-01 19:54:11 -07001686 if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001687 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001688 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1689 } else {
Keith Packard93f62da2011-11-01 19:45:03 -07001690 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001691 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1692 }
1693
Adam Jackson82d16552011-10-14 17:22:26 -04001694 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001695 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1696 else
1697 reg = DP | DP_LINK_TRAIN_PAT_2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001698
1699 /* channel eq pattern */
Chris Wilsonea5b2132010-08-04 13:50:23 +01001700 if (!intel_dp_set_link_train(intel_dp, reg,
Adam Jackson81055852011-07-21 17:48:37 -04001701 DP_TRAINING_PATTERN_2 |
1702 DP_LINK_SCRAMBLING_DISABLE))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001703 break;
1704
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001705 udelay(400);
Keith Packard93f62da2011-11-01 19:45:03 -07001706 if (!intel_dp_get_link_status(intel_dp, link_status))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001707 break;
Jesse Barnes869184a2010-10-07 16:01:22 -07001708
Jesse Barnes37f80972011-01-05 14:45:24 -08001709 /* Make sure clock is still ok */
Keith Packard93f62da2011-11-01 19:45:03 -07001710 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Jesse Barnes37f80972011-01-05 14:45:24 -08001711 intel_dp_start_link_train(intel_dp);
1712 cr_tries++;
1713 continue;
1714 }
1715
Keith Packard93f62da2011-11-01 19:45:03 -07001716 if (intel_channel_eq_ok(intel_dp, link_status)) {
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001717 channel_eq = true;
1718 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001719 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001720
Jesse Barnes37f80972011-01-05 14:45:24 -08001721 /* Try 5 times, then try clock recovery if that fails */
1722 if (tries > 5) {
1723 intel_dp_link_down(intel_dp);
1724 intel_dp_start_link_train(intel_dp);
1725 tries = 0;
1726 cr_tries++;
1727 continue;
1728 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001729
1730 /* Compute new intel_dp->train_set as requested by target */
Keith Packard93f62da2011-11-01 19:45:03 -07001731 intel_get_adjust_train(intel_dp, link_status);
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001732 ++tries;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001733 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001734
Adam Jackson82d16552011-10-14 17:22:26 -04001735 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001736 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1737 else
1738 reg = DP | DP_LINK_TRAIN_OFF;
1739
Chris Wilsonea5b2132010-08-04 13:50:23 +01001740 I915_WRITE(intel_dp->output_reg, reg);
1741 POSTING_READ(intel_dp->output_reg);
1742 intel_dp_aux_native_write_1(intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001743 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1744}
1745
1746static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01001747intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001748{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001749 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001750 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001751 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001752
Chris Wilson1b39d6f2010-12-06 11:20:45 +00001753 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1754 return;
1755
Zhao Yakui28c97732009-10-09 11:39:41 +08001756 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001757
Jesse Barnescfcb0fc2010-10-07 16:01:06 -07001758 if (is_edp(intel_dp)) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001759 DP &= ~DP_PLL_ENABLE;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001760 I915_WRITE(intel_dp->output_reg, DP);
1761 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001762 udelay(100);
1763 }
1764
Adam Jackson82d16552011-10-14 17:22:26 -04001765 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08001766 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001767 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001768 } else {
1769 DP &= ~DP_LINK_TRAIN_MASK;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001770 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001771 }
Chris Wilsonfe255d02010-09-11 21:37:48 +01001772 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001773
Chris Wilsonfe255d02010-09-11 21:37:48 +01001774 msleep(17);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001775
Keith Packard417e8222011-11-01 19:54:11 -07001776 if (is_edp(intel_dp)) {
1777 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1778 DP |= DP_LINK_TRAIN_OFF_CPT;
1779 else
1780 DP |= DP_LINK_TRAIN_OFF;
1781 }
Eric Anholt5bddd172010-11-18 09:32:59 +08001782
Chris Wilson1b39d6f2010-12-06 11:20:45 +00001783 if (!HAS_PCH_CPT(dev) &&
1784 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
Chris Wilson31acbcc2011-04-17 06:38:35 +01001785 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1786
Eric Anholt5bddd172010-11-18 09:32:59 +08001787 /* Hardware workaround: leaving our transcoder select
1788 * set to transcoder B while it's off will prevent the
1789 * corresponding HDMI output on transcoder A.
1790 *
1791 * Combine this with another hardware workaround:
1792 * transcoder select bit can only be cleared while the
1793 * port is enabled.
1794 */
1795 DP &= ~DP_PIPEB_SELECT;
1796 I915_WRITE(intel_dp->output_reg, DP);
1797
1798 /* Changes to enable or select take place the vblank
1799 * after being written.
1800 */
Chris Wilson31acbcc2011-04-17 06:38:35 +01001801 if (crtc == NULL) {
1802 /* We can arrive here never having been attached
1803 * to a CRTC, for instance, due to inheriting
1804 * random state from the BIOS.
1805 *
1806 * If the pipe is not running, play safe and
1807 * wait for the clocks to stabilise before
1808 * continuing.
1809 */
1810 POSTING_READ(intel_dp->output_reg);
1811 msleep(50);
1812 } else
1813 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
Eric Anholt5bddd172010-11-18 09:32:59 +08001814 }
1815
Chris Wilsonea5b2132010-08-04 13:50:23 +01001816 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1817 POSTING_READ(intel_dp->output_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07001818 msleep(intel_dp->panel_power_down_delay);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001819}
1820
Keith Packard26d61aa2011-07-25 20:01:09 -07001821static bool
1822intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07001823{
Keith Packard92fd8fd2011-07-25 19:50:10 -07001824 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
Akshay Joshi0206e352011-08-16 15:34:10 -04001825 sizeof(intel_dp->dpcd)) &&
Keith Packard92fd8fd2011-07-25 19:50:10 -07001826 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
Keith Packard26d61aa2011-07-25 20:01:09 -07001827 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07001828 }
1829
Keith Packard26d61aa2011-07-25 20:01:09 -07001830 return false;
Keith Packard92fd8fd2011-07-25 19:50:10 -07001831}
1832
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001833static bool
1834intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1835{
1836 int ret;
1837
1838 ret = intel_dp_aux_native_read_retry(intel_dp,
1839 DP_DEVICE_SERVICE_IRQ_VECTOR,
1840 sink_irq_vector, 1);
1841 if (!ret)
1842 return false;
1843
1844 return true;
1845}
1846
1847static void
1848intel_dp_handle_test_request(struct intel_dp *intel_dp)
1849{
1850 /* NAK by default */
1851 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1852}
1853
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001854/*
1855 * According to DP spec
1856 * 5.1.2:
1857 * 1. Read DPCD
1858 * 2. Configure link according to Receiver Capabilities
1859 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1860 * 4. Check link status on receipt of hot-plug interrupt
1861 */
1862
1863static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01001864intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001865{
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001866 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07001867 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001868
Keith Packardd2b996a2011-07-25 22:37:51 -07001869 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1870 return;
Jesse Barnes59cd09e2011-07-07 11:10:59 -07001871
Chris Wilson4ef69c72010-09-09 15:14:28 +01001872 if (!intel_dp->base.base.crtc)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001873 return;
1874
Keith Packard92fd8fd2011-07-25 19:50:10 -07001875 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07001876 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01001877 intel_dp_link_down(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001878 return;
1879 }
1880
Keith Packard92fd8fd2011-07-25 19:50:10 -07001881 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07001882 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07001883 intel_dp_link_down(intel_dp);
1884 return;
1885 }
1886
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001887 /* Try to read the source of the interrupt */
1888 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1889 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1890 /* Clear interrupt source */
1891 intel_dp_aux_native_write_1(intel_dp,
1892 DP_DEVICE_SERVICE_IRQ_VECTOR,
1893 sink_irq_vector);
1894
1895 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1896 intel_dp_handle_test_request(intel_dp);
1897 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1898 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1899 }
1900
Keith Packard93f62da2011-11-01 19:45:03 -07001901 if (!intel_channel_eq_ok(intel_dp, link_status)) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07001902 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1903 drm_get_encoder_name(&intel_dp->base.base));
Jesse Barnes33a34e42010-09-08 12:42:02 -07001904 intel_dp_start_link_train(intel_dp);
1905 intel_dp_complete_link_train(intel_dp);
1906 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001907}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001908
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001909static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07001910intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba9002011-07-12 17:38:04 -04001911{
Keith Packard26d61aa2011-07-25 20:01:09 -07001912 if (intel_dp_get_dpcd(intel_dp))
1913 return connector_status_connected;
1914 return connector_status_disconnected;
Adam Jackson71ba9002011-07-12 17:38:04 -04001915}
1916
1917static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08001918ironlake_dp_detect(struct intel_dp *intel_dp)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001919{
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001920 enum drm_connector_status status;
1921
Chris Wilsonfe16d942011-02-12 10:29:38 +00001922 /* Can't disconnect eDP, but you can close the lid... */
1923 if (is_edp(intel_dp)) {
1924 status = intel_panel_detect(intel_dp->base.base.dev);
1925 if (status == connector_status_unknown)
1926 status = connector_status_connected;
1927 return status;
1928 }
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001929
Keith Packard26d61aa2011-07-25 20:01:09 -07001930 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001931}
1932
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001933static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08001934g4x_dp_detect(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001935{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001936 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001937 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08001938 uint32_t temp, bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001939
Chris Wilsonea5b2132010-08-04 13:50:23 +01001940 switch (intel_dp->output_reg) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001941 case DP_B:
1942 bit = DPB_HOTPLUG_INT_STATUS;
1943 break;
1944 case DP_C:
1945 bit = DPC_HOTPLUG_INT_STATUS;
1946 break;
1947 case DP_D:
1948 bit = DPD_HOTPLUG_INT_STATUS;
1949 break;
1950 default:
1951 return connector_status_unknown;
1952 }
1953
1954 temp = I915_READ(PORT_HOTPLUG_STAT);
1955
1956 if ((temp & bit) == 0)
1957 return connector_status_disconnected;
1958
Keith Packard26d61aa2011-07-25 20:01:09 -07001959 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08001960}
1961
Keith Packard8c241fe2011-09-28 16:38:44 -07001962static struct edid *
1963intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1964{
1965 struct intel_dp *intel_dp = intel_attached_dp(connector);
1966 struct edid *edid;
1967
1968 ironlake_edp_panel_vdd_on(intel_dp);
1969 edid = drm_get_edid(connector, adapter);
Keith Packardbd943152011-09-18 23:09:52 -07001970 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard8c241fe2011-09-28 16:38:44 -07001971 return edid;
1972}
1973
1974static int
1975intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1976{
1977 struct intel_dp *intel_dp = intel_attached_dp(connector);
1978 int ret;
1979
1980 ironlake_edp_panel_vdd_on(intel_dp);
1981 ret = intel_ddc_get_modes(connector, adapter);
Keith Packardbd943152011-09-18 23:09:52 -07001982 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard8c241fe2011-09-28 16:38:44 -07001983 return ret;
1984}
1985
1986
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08001987/**
1988 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1989 *
1990 * \return true if DP port is connected.
1991 * \return false if DP port is disconnected.
1992 */
1993static enum drm_connector_status
1994intel_dp_detect(struct drm_connector *connector, bool force)
1995{
1996 struct intel_dp *intel_dp = intel_attached_dp(connector);
1997 struct drm_device *dev = intel_dp->base.base.dev;
1998 enum drm_connector_status status;
1999 struct edid *edid = NULL;
2000
2001 intel_dp->has_audio = false;
2002
2003 if (HAS_PCH_SPLIT(dev))
2004 status = ironlake_dp_detect(intel_dp);
2005 else
2006 status = g4x_dp_detect(intel_dp);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04002007
Adam Jacksonac66ae82011-07-12 17:38:03 -04002008 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2009 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2010 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2011 intel_dp->dpcd[6], intel_dp->dpcd[7]);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04002012
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002013 if (status != connector_status_connected)
2014 return status;
2015
Chris Wilsonf6849602010-09-19 09:29:33 +01002016 if (intel_dp->force_audio) {
2017 intel_dp->has_audio = intel_dp->force_audio > 0;
2018 } else {
Keith Packard8c241fe2011-09-28 16:38:44 -07002019 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
Chris Wilsonf6849602010-09-19 09:29:33 +01002020 if (edid) {
2021 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2022 connector->display_info.raw_edid = NULL;
2023 kfree(edid);
2024 }
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002025 }
2026
2027 return connector_status_connected;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002028}
2029
2030static int intel_dp_get_modes(struct drm_connector *connector)
2031{
Chris Wilsondf0e9242010-09-09 16:20:55 +01002032 struct intel_dp *intel_dp = intel_attached_dp(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01002033 struct drm_device *dev = intel_dp->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002036
2037 /* We should parse the EDID data and find out if it has an audio sink
2038 */
2039
Keith Packard8c241fe2011-09-28 16:38:44 -07002040 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
Zhao Yakuib9efc482010-07-19 09:43:11 +01002041 if (ret) {
Keith Packardd15456d2011-09-18 17:35:47 -07002042 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
Zhao Yakuib9efc482010-07-19 09:43:11 +01002043 struct drm_display_mode *newmode;
2044 list_for_each_entry(newmode, &connector->probed_modes,
2045 head) {
Keith Packardd15456d2011-09-18 17:35:47 -07002046 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2047 intel_dp->panel_fixed_mode =
Zhao Yakuib9efc482010-07-19 09:43:11 +01002048 drm_mode_duplicate(dev, newmode);
2049 break;
2050 }
2051 }
2052 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002053 return ret;
Zhao Yakuib9efc482010-07-19 09:43:11 +01002054 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002055
2056 /* if eDP has no EDID, try to use fixed panel mode from VBT */
Jesse Barnes4d926462010-10-07 16:01:07 -07002057 if (is_edp(intel_dp)) {
Keith Packard47f0eb22011-09-19 14:33:26 -07002058 /* initialize panel mode from VBT if available for eDP */
Keith Packardd15456d2011-09-18 17:35:47 -07002059 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2060 intel_dp->panel_fixed_mode =
Keith Packard47f0eb22011-09-19 14:33:26 -07002061 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
Keith Packardd15456d2011-09-18 17:35:47 -07002062 if (intel_dp->panel_fixed_mode) {
2063 intel_dp->panel_fixed_mode->type |=
Keith Packard47f0eb22011-09-19 14:33:26 -07002064 DRM_MODE_TYPE_PREFERRED;
2065 }
2066 }
Keith Packardd15456d2011-09-18 17:35:47 -07002067 if (intel_dp->panel_fixed_mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002068 struct drm_display_mode *mode;
Keith Packardd15456d2011-09-18 17:35:47 -07002069 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002070 drm_mode_probed_add(connector, mode);
2071 return 1;
2072 }
2073 }
2074 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002075}
2076
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002077static bool
2078intel_dp_detect_audio(struct drm_connector *connector)
2079{
2080 struct intel_dp *intel_dp = intel_attached_dp(connector);
2081 struct edid *edid;
2082 bool has_audio = false;
2083
Keith Packard8c241fe2011-09-28 16:38:44 -07002084 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002085 if (edid) {
2086 has_audio = drm_detect_monitor_audio(edid);
2087
2088 connector->display_info.raw_edid = NULL;
2089 kfree(edid);
2090 }
2091
2092 return has_audio;
2093}
2094
Chris Wilsonf6849602010-09-19 09:29:33 +01002095static int
2096intel_dp_set_property(struct drm_connector *connector,
2097 struct drm_property *property,
2098 uint64_t val)
2099{
Chris Wilsone953fd72011-02-21 22:23:52 +00002100 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Chris Wilsonf6849602010-09-19 09:29:33 +01002101 struct intel_dp *intel_dp = intel_attached_dp(connector);
2102 int ret;
2103
2104 ret = drm_connector_property_set_value(connector, property, val);
2105 if (ret)
2106 return ret;
2107
Chris Wilson3f43c482011-05-12 22:17:24 +01002108 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002109 int i = val;
2110 bool has_audio;
2111
2112 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01002113 return 0;
2114
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002115 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01002116
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002117 if (i == 0)
2118 has_audio = intel_dp_detect_audio(connector);
2119 else
2120 has_audio = i > 0;
2121
2122 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01002123 return 0;
2124
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002125 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01002126 goto done;
2127 }
2128
Chris Wilsone953fd72011-02-21 22:23:52 +00002129 if (property == dev_priv->broadcast_rgb_property) {
2130 if (val == !!intel_dp->color_range)
2131 return 0;
2132
2133 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2134 goto done;
2135 }
2136
Chris Wilsonf6849602010-09-19 09:29:33 +01002137 return -EINVAL;
2138
2139done:
2140 if (intel_dp->base.base.crtc) {
2141 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2142 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2143 crtc->x, crtc->y,
2144 crtc->fb);
2145 }
2146
2147 return 0;
2148}
2149
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002150static void
Akshay Joshi0206e352011-08-16 15:34:10 -04002151intel_dp_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002152{
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02002153 struct drm_device *dev = connector->dev;
2154
2155 if (intel_dpd_is_edp(dev))
2156 intel_panel_destroy_backlight(dev);
2157
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002158 drm_sysfs_connector_remove(connector);
2159 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002160 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002161}
2162
Daniel Vetter24d05922010-08-20 18:08:28 +02002163static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2164{
2165 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2166
2167 i2c_del_adapter(&intel_dp->adapter);
2168 drm_encoder_cleanup(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07002169 if (is_edp(intel_dp)) {
2170 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2171 ironlake_panel_vdd_off_sync(intel_dp);
2172 }
Daniel Vetter24d05922010-08-20 18:08:28 +02002173 kfree(intel_dp);
2174}
2175
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002176static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2177 .dpms = intel_dp_dpms,
2178 .mode_fixup = intel_dp_mode_fixup,
Jesse Barnesd240f202010-08-13 15:43:26 -07002179 .prepare = intel_dp_prepare,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002180 .mode_set = intel_dp_mode_set,
Jesse Barnesd240f202010-08-13 15:43:26 -07002181 .commit = intel_dp_commit,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002182};
2183
2184static const struct drm_connector_funcs intel_dp_connector_funcs = {
2185 .dpms = drm_helper_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002186 .detect = intel_dp_detect,
2187 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01002188 .set_property = intel_dp_set_property,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002189 .destroy = intel_dp_destroy,
2190};
2191
2192static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2193 .get_modes = intel_dp_get_modes,
2194 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01002195 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002196};
2197
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002198static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Daniel Vetter24d05922010-08-20 18:08:28 +02002199 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002200};
2201
Chris Wilson995b6762010-08-20 13:23:26 +01002202static void
Eric Anholt21d40d32010-03-25 11:11:14 -07002203intel_dp_hot_plug(struct intel_encoder *intel_encoder)
Keith Packardc8110e52009-05-06 11:51:10 -07002204{
Chris Wilsonea5b2132010-08-04 13:50:23 +01002205 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
Keith Packardc8110e52009-05-06 11:51:10 -07002206
Jesse Barnes885a5012011-07-07 11:11:01 -07002207 intel_dp_check_link_status(intel_dp);
Keith Packardc8110e52009-05-06 11:51:10 -07002208}
2209
Zhenyu Wange3421a12010-04-08 09:43:27 +08002210/* Return which DP Port should be selected for Transcoder DP control */
2211int
Akshay Joshi0206e352011-08-16 15:34:10 -04002212intel_trans_dp_port_sel(struct drm_crtc *crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08002213{
2214 struct drm_device *dev = crtc->dev;
2215 struct drm_mode_config *mode_config = &dev->mode_config;
2216 struct drm_encoder *encoder;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002217
2218 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01002219 struct intel_dp *intel_dp;
2220
Dan Carpenterd8201ab2010-05-07 10:39:00 +02002221 if (encoder->crtc != crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08002222 continue;
2223
Chris Wilsonea5b2132010-08-04 13:50:23 +01002224 intel_dp = enc_to_intel_dp(encoder);
Keith Packard417e8222011-11-01 19:54:11 -07002225 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2226 intel_dp->base.type == INTEL_OUTPUT_EDP)
Chris Wilsonea5b2132010-08-04 13:50:23 +01002227 return intel_dp->output_reg;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002228 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01002229
Zhenyu Wange3421a12010-04-08 09:43:27 +08002230 return -1;
2231}
2232
Zhao Yakui36e83a12010-06-12 14:32:21 +08002233/* check the VBT to see whether the eDP is on DP-D port */
Adam Jacksoncb0953d2010-07-16 14:46:29 -04002234bool intel_dpd_is_edp(struct drm_device *dev)
Zhao Yakui36e83a12010-06-12 14:32:21 +08002235{
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237 struct child_device_config *p_child;
2238 int i;
2239
2240 if (!dev_priv->child_dev_num)
2241 return false;
2242
2243 for (i = 0; i < dev_priv->child_dev_num; i++) {
2244 p_child = dev_priv->child_dev + i;
2245
2246 if (p_child->dvo_port == PORT_IDPD &&
2247 p_child->device_type == DEVICE_TYPE_eDP)
2248 return true;
2249 }
2250 return false;
2251}
2252
Chris Wilsonf6849602010-09-19 09:29:33 +01002253static void
2254intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2255{
Chris Wilson3f43c482011-05-12 22:17:24 +01002256 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00002257 intel_attach_broadcast_rgb_property(connector);
Chris Wilsonf6849602010-09-19 09:29:33 +01002258}
2259
Keith Packardc8110e52009-05-06 11:51:10 -07002260void
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002261intel_dp_init(struct drm_device *dev, int output_reg)
2262{
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264 struct drm_connector *connector;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002265 struct intel_dp *intel_dp;
Eric Anholt21d40d32010-03-25 11:11:14 -07002266 struct intel_encoder *intel_encoder;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002267 struct intel_connector *intel_connector;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002268 const char *name = NULL;
Adam Jacksonb3295302010-07-16 14:46:28 -04002269 int type;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002270
Chris Wilsonea5b2132010-08-04 13:50:23 +01002271 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2272 if (!intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002273 return;
2274
Chris Wilson3d3dc142011-02-12 10:33:12 +00002275 intel_dp->output_reg = output_reg;
Keith Packardd2b996a2011-07-25 22:37:51 -07002276 intel_dp->dpms_mode = -1;
Chris Wilson3d3dc142011-02-12 10:33:12 +00002277
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002278 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2279 if (!intel_connector) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01002280 kfree(intel_dp);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002281 return;
2282 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01002283 intel_encoder = &intel_dp->base;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002284
Chris Wilsonea5b2132010-08-04 13:50:23 +01002285 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
Adam Jacksonb3295302010-07-16 14:46:28 -04002286 if (intel_dpd_is_edp(dev))
Chris Wilsonea5b2132010-08-04 13:50:23 +01002287 intel_dp->is_pch_edp = true;
Adam Jacksonb3295302010-07-16 14:46:28 -04002288
Jesse Barnescfcb0fc2010-10-07 16:01:06 -07002289 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
Adam Jacksonb3295302010-07-16 14:46:28 -04002290 type = DRM_MODE_CONNECTOR_eDP;
2291 intel_encoder->type = INTEL_OUTPUT_EDP;
2292 } else {
2293 type = DRM_MODE_CONNECTOR_DisplayPort;
2294 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2295 }
2296
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002297 connector = &intel_connector->base;
Adam Jacksonb3295302010-07-16 14:46:28 -04002298 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002299 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2300
Dave Airlieeb1f8e42010-05-07 06:42:51 +00002301 connector->polled = DRM_CONNECTOR_POLL_HPD;
2302
Zhao Yakui652af9d2009-12-02 10:03:33 +08002303 if (output_reg == DP_B || output_reg == PCH_DP_B)
Eric Anholt21d40d32010-03-25 11:11:14 -07002304 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
Zhao Yakui652af9d2009-12-02 10:03:33 +08002305 else if (output_reg == DP_C || output_reg == PCH_DP_C)
Eric Anholt21d40d32010-03-25 11:11:14 -07002306 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
Zhao Yakui652af9d2009-12-02 10:03:33 +08002307 else if (output_reg == DP_D || output_reg == PCH_DP_D)
Eric Anholt21d40d32010-03-25 11:11:14 -07002308 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
Ma Lingf8aed702009-08-24 13:50:24 +08002309
Keith Packardbd943152011-09-18 23:09:52 -07002310 if (is_edp(intel_dp)) {
Eric Anholt21d40d32010-03-25 11:11:14 -07002311 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
Keith Packardbd943152011-09-18 23:09:52 -07002312 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2313 ironlake_panel_vdd_work);
2314 }
Zhenyu Wang6251ec02010-01-12 05:38:32 +08002315
Jesse Barnes27f82272011-09-02 12:54:37 -07002316 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002317 connector->interlace_allowed = true;
2318 connector->doublescan_allowed = 0;
2319
Chris Wilson4ef69c72010-09-09 15:14:28 +01002320 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002321 DRM_MODE_ENCODER_TMDS);
Chris Wilson4ef69c72010-09-09 15:14:28 +01002322 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002323
Chris Wilsondf0e9242010-09-09 16:20:55 +01002324 intel_connector_attach_encoder(intel_connector, intel_encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002325 drm_sysfs_connector_add(connector);
2326
2327 /* Set up the DDC bus. */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002328 switch (output_reg) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002329 case DP_A:
2330 name = "DPDDC-A";
2331 break;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002332 case DP_B:
2333 case PCH_DP_B:
Jesse Barnesb01f2c32009-12-11 11:07:17 -08002334 dev_priv->hotplug_supported_mask |=
2335 HDMIB_HOTPLUG_INT_STATUS;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002336 name = "DPDDC-B";
2337 break;
2338 case DP_C:
2339 case PCH_DP_C:
Jesse Barnesb01f2c32009-12-11 11:07:17 -08002340 dev_priv->hotplug_supported_mask |=
2341 HDMIC_HOTPLUG_INT_STATUS;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002342 name = "DPDDC-C";
2343 break;
2344 case DP_D:
2345 case PCH_DP_D:
Jesse Barnesb01f2c32009-12-11 11:07:17 -08002346 dev_priv->hotplug_supported_mask |=
2347 HDMID_HOTPLUG_INT_STATUS;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002348 name = "DPDDC-D";
2349 break;
2350 }
2351
Jesse Barnes89667382010-10-07 16:01:21 -07002352 /* Cache some DPCD data in the eDP case */
2353 if (is_edp(intel_dp)) {
Keith Packard59f3e272011-07-25 20:01:56 -07002354 bool ret;
Keith Packardf01eca22011-09-28 16:48:10 -07002355 struct edp_power_seq cur, vbt;
2356 u32 pp_on, pp_off, pp_div;
Jesse Barnes89667382010-10-07 16:01:21 -07002357
Jesse Barnes5d613502011-01-24 17:10:54 -08002358 pp_on = I915_READ(PCH_PP_ON_DELAYS);
Keith Packardf01eca22011-09-28 16:48:10 -07002359 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
Jesse Barnes5d613502011-01-24 17:10:54 -08002360 pp_div = I915_READ(PCH_PP_DIVISOR);
2361
Keith Packardf01eca22011-09-28 16:48:10 -07002362 /* Pull timing values out of registers */
2363 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2364 PANEL_POWER_UP_DELAY_SHIFT;
2365
2366 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2367 PANEL_LIGHT_ON_DELAY_SHIFT;
2368
2369 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2370 PANEL_LIGHT_OFF_DELAY_SHIFT;
2371
2372 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2373 PANEL_POWER_DOWN_DELAY_SHIFT;
2374
2375 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2376 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2377
2378 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2379 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2380
2381 vbt = dev_priv->edp.pps;
2382
2383 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2384 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2385
2386#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2387
2388 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2389 intel_dp->backlight_on_delay = get_delay(t8);
2390 intel_dp->backlight_off_delay = get_delay(t9);
2391 intel_dp->panel_power_down_delay = get_delay(t10);
2392 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2393
2394 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2395 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2396 intel_dp->panel_power_cycle_delay);
2397
2398 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2399 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
Jesse Barnes5d613502011-01-24 17:10:54 -08002400
Keith Packardbd943152011-09-18 23:09:52 -07002401 intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
Jesse Barnes5d613502011-01-24 17:10:54 -08002402
2403 ironlake_edp_panel_vdd_on(intel_dp);
Keith Packard59f3e272011-07-25 20:01:56 -07002404 ret = intel_dp_get_dpcd(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07002405 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard59f3e272011-07-25 20:01:56 -07002406 if (ret) {
Jesse Barnes7183dc22011-07-07 11:10:58 -07002407 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2408 dev_priv->no_aux_handshake =
2409 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
Jesse Barnes89667382010-10-07 16:01:21 -07002410 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2411 } else {
Chris Wilson3d3dc142011-02-12 10:33:12 +00002412 /* if this fails, presume the device is a ghost */
Takashi Iwai48898b02011-03-18 09:06:49 +00002413 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Chris Wilson3d3dc142011-02-12 10:33:12 +00002414 intel_dp_encoder_destroy(&intel_dp->base.base);
Takashi Iwai48898b02011-03-18 09:06:49 +00002415 intel_dp_destroy(&intel_connector->base);
Chris Wilson3d3dc142011-02-12 10:33:12 +00002416 return;
Jesse Barnes89667382010-10-07 16:01:21 -07002417 }
Jesse Barnes89667382010-10-07 16:01:21 -07002418 }
2419
Keith Packard552fb0b2011-09-28 16:31:53 -07002420 intel_dp_i2c_init(intel_dp, intel_connector, name);
2421
Eric Anholt21d40d32010-03-25 11:11:14 -07002422 intel_encoder->hot_plug = intel_dp_hot_plug;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002423
Jesse Barnes4d926462010-10-07 16:01:07 -07002424 if (is_edp(intel_dp)) {
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02002425 dev_priv->int_edp_connector = connector;
2426 intel_panel_setup_backlight(dev);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002427 }
2428
Chris Wilsonf6849602010-09-19 09:29:33 +01002429 intel_dp_add_properties(intel_dp, connector);
2430
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002431 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2432 * 0xd. Failure to do so will result in spurious interrupts being
2433 * generated on the port when a cable is not attached.
2434 */
2435 if (IS_G4X(dev) && !IS_GM45(dev)) {
2436 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2437 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2438 }
2439}