aboutsummaryrefslogtreecommitdiff
path: root/hw/pl041.h
blob: 1f224326e59aeecc8dd667e6cd40fef1bb56234d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
/*
 * Arm PrimeCell PL041 Advanced Audio Codec Interface
 *
 * Copyright (c) 2011
 * Written by Mathieu Sonet - www.elasticsheep.com
 *
 * This code is licenced under the GPL.
 *
 * *****************************************************************
 */

#ifndef HW_PL041_H
#define HW_PL041_H

/* Register file */
#define REGISTER(name, offset) uint32_t name;
typedef struct {
    #include "pl041.hx"
} pl041_regfile;
#undef REGISTER

/* Register addresses */
#define REGISTER(name, offset) PL041_##name = offset,
enum {
    #include "pl041.hx"

    PL041_periphid0 = 0xFE0,
    PL041_periphid1 = 0xFE4,
    PL041_periphid2 = 0xFE8,
    PL041_periphid3 = 0xFEC,
    PL041_pcellid0  = 0xFF0,
    PL041_pcellid1  = 0xFF4,
    PL041_pcellid2  = 0xFF8,
    PL041_pcellid3  = 0xFFC,
};
#undef REGISTER

/* Register bits */

/* IEx */
#define TXCIE           (1 << 0)
#define RXTIE           (1 << 1)
#define TXIE            (1 << 2)
#define RXIE            (1 << 3)
#define RXOIE           (1 << 4)
#define TXUIE           (1 << 5)
#define RXTOIE          (1 << 6)

/* TXCRx */
#define TXEN            (1 << 0)
#define TXSLOT1         (1 << 1)
#define TXSLOT2         (1 << 2)
#define TXSLOT3         (1 << 3)
#define TXSLOT4         (1 << 4)
#define TXCOMPACT       (1 << 15)
#define TXFEN           (1 << 16)

#define TXSLOT_MASK_BIT (1)
#define TXSLOT_MASK     (0xFFF << TXSLOT_MASK_BIT)

#define TSIZE_MASK_BIT  (13)
#define TSIZE_MASK      (0x3 << TSIZE_MASK_BIT)

#define TSIZE_16BITS    (0x0 << TSIZE_MASK_BIT)
#define TSIZE_18BITS    (0x1 << TSIZE_MASK_BIT)
#define TSIZE_20BITS    (0x2 << TSIZE_MASK_BIT)
#define TSIZE_12BITS    (0x3 << TSIZE_MASK_BIT)

/* SRx */
#define RXFE         (1 << 0)
#define TXFE         (1 << 1)
#define RXHF         (1 << 2)
#define TXHE         (1 << 3)
#define RXFF         (1 << 4)
#define TXFF         (1 << 5)
#define RXBUSY       (1 << 6)
#define TXBUSY       (1 << 7)
#define RXOVERRUN    (1 << 8)
#define TXUNDERRUN   (1 << 9)
#define RXTIMEOUT    (1 << 10)
#define RXTOFE       (1 << 11)

/* ISRx */
#define TXCINTR      (1 << 0)
#define RXTOINTR     (1 << 1)
#define TXINTR       (1 << 2)
#define RXINTR       (1 << 3)
#define ORINTR       (1 << 4)
#define URINTR       (1 << 5)
#define RXTOFEINTR   (1 << 6)

/* SLFR */
#define SL1RXBUSY    (1 << 0)
#define SL1TXBUSY    (1 << 1)
#define SL2RXBUSY    (1 << 2)
#define SL2TXBUSY    (1 << 3)
#define SL12RXBUSY   (1 << 4)
#define SL12TXBUSY   (1 << 5)
#define SL1RXVALID   (1 << 6)
#define SL1TXEMPTY   (1 << 7)
#define SL2RXVALID   (1 << 8)
#define SL2TXEMPTY   (1 << 9)
#define SL12RXVALID  (1 << 10)
#define SL12TXEMPTY  (1 << 11)
#define RAWGPIOINT   (1 << 12)
#define RWIS         (1 << 13)

/* MAINCR */
#define AACIFE       (1 << 0)
#define LOOPBACK     (1 << 1)
#define LOWPOWER     (1 << 2)
#define SL1RXEN      (1 << 3)
#define SL1TXEN      (1 << 4)
#define SL2RXEN      (1 << 5)
#define SL2TXEN      (1 << 6)
#define SL12RXEN     (1 << 7)
#define SL12TXEN     (1 << 8)
#define DMAENABLE    (1 << 9)

/* INTCLR */
#define WISC         (1 << 0)
#define RXOEC1       (1 << 1)
#define RXOEC2       (1 << 2)
#define RXOEC3       (1 << 3)
#define RXOEC4       (1 << 4)
#define TXUEC1       (1 << 5)
#define TXUEC2       (1 << 6)
#define TXUEC3       (1 << 7)
#define TXUEC4       (1 << 8)
#define RXTOFEC1     (1 << 9)
#define RXTOFEC2     (1 << 10)
#define RXTOFEC3     (1 << 11)
#define RXTOFEC4     (1 << 12)

#endif /* #ifndef HW_PL041_H */