index
:
peter.maydell/qemu-arm.git
3phase-conversions
64-bit-physaddrs
a64-fifth-set
a64-first-set
a64-first-set-test-context
a64-for-marcus
a64-neon
a64-neon-sixth-set
a64-saverestore
a64-second-set
a64-sixth-set
a64-system
a64-system-3
a64-system-4
a64-system-sysregs
a64-third-fourth-set
a64-third-set
a64-vixl
a64-wip
a64-working
aarch32-guest
aarch32-hyp
aarch64
aarch64-busted
aarch64-kvm
aarch64-kvm-working
amba-virtio
arm-devs.for-upstream
arm-devs.next
arm-test
armhw-for-upstream
be-fixes
better-exec-logging
better-ifdefs
boot-fix-int-sizes
bsd-async-bug
bsd-fixes
bsd-user.for-upstream
bsd-user.next
bsd-user.to-test
bsd-warnings
clean-includes
clock-adjtime
cocoa-abs
cocoa-menu
cocoa-pools
cocoa.for-upstream
cocoa.next
configury.for-upstream
configury.next
cp15-barriers
cp15-on-qom
cp15-on-qom-on-miniqom
cp15-on-qom.2
cp15-rework
cpu-copy-method
cpu-max
crypto
darwin-9p
debug
dirent
docs.for-upstream
docs.next
drop-kvm32
drop-qemu-common-incs
drop-reset-model-id
ets
exynos-gic
feat-mops
feat-nv
fix-disas-addrs
fix-mig-3.0
fix-nptl
fix-pci
fix-sysreg-writeback
fix-thread-atexit
fix-vm-tests
for-anthony
for-upstream
for-upstream-0.15
fpcxt-ns-fix
fsr-in-faultinfo
full-tz-enable
gcc-guards
gdbstub
gic-as-device
gic-prio-bits
gicv3
gicv3-virt
gicv4
gpio-pwr
handle-gicv3-only
hvf-stuff
icount-debug
idreg-asserts
idreg-fixes
int-fast16-t
int-flag
ivshmem
javac-noodling
kvm-arm
kvm-arm-dev-addr-test
kvm-arm-gdb-repro
kvm-arm-irqchange
kvm-arm-onereg
kvm-arm-onereg-vfp
kvm-arm-onereg-working
kvm-arm-v12
kvm-arm-v13
kvm-arm-v14
kvm-arm-v17
kvm-arm-working
kvm-arm-working-2
kvm-el3
kvm-ioctl-eintr
kvm-psci-version
kvm-sync-regs
kvm-sync-test
kvm-work
kvm-x86isms
libusb-warning
linux-fixes
linux-user
linux-user-nuke-ifdefs
linux-user-pull
linux-user.for-upstream
linux-user.next
m-profile-fixes
m1-debug
mach-virt
mach-virt-64
master
merge-for-testing
mips-fix
misc.for-upstream
misc.next
missing-idregs
mojave-fixes
more-be-host-bugs
more-ram
multi-ases
multi-ases-2
mve-drop-1
mve-drop-3
mve-gdb
neon-decodetree
ninjatool-barf
no-uname
no-virt
no-werror-in-configure
nococoa
non-utf-fixes
num-pmu-ctrs
nvic-rebase
nvic-rewrite
objcc-cross
omap-for-upstream
osx-deprecated
overo
paolo-docs
ppcuic
preadv-osx
priplx
psci-messing
pxa-mmci-qomify
q-l-kvm-x86isms
q-l-msr-ops
q-l-on-64phys
q-l-pic-cleanup
qemu-char-warning
qerror-after-realized
ranchu
ranchu-adb
ranchu-linaro-beta1
ranchu-linaro-beta2
ranchu-pipe
ranchu-proposed
ranchu-virtserial
ranchu-virtserial-rebased
revert-branch-stuff
s390-barriers
sd-saveload
sf-relicensing
sigrace-fixes
sigrace-fixes-3
singlestep-rename
softfloat-types
softfloat.for-upstream
softfloat.next
sparc-buildfix
sparc-buildfixa
sparc-fixes
sparc-fprs
sparc-pagealign
sphinx-conv-broken
sphinx-conversions
sphinx-conversions-v5
sphinx-docs
sphinx.for-upstream
sphinx.next
sse-300
stable-0.10
stable-0.11
stable-0.12
stable-0.13
staging
systick-scale
target-arm-for-8.0
target-arm-for-8.2
target-arm-post-2.4
target-arm.for-3.1
target-arm.for-upstream
target-arm.next
tcg-aarch64.for-upstream
tcg-aarch64.next
tcg-arm-movcond
tcg-use-mov-reg
test-arm-hvf
test-aurel-arm-opt
test-avocado-sockpair
test-neon-be-fixes
test-nmi
test-ping-fixes
test-propagate-error
test-psci-6
test-ql
test-qom-kvm
test-ras
test-tls
test-uint16
test-utmpx
testendian
tge
transaction-attrs
txfail
tz-migration
uart-edk-investigation
use-esr-magic
v7m-hacks
v7m-mpu
v7m-qomify
v8-tz
v8m
vexpress-clocks
vfp-decodetree
vgic
virt-for-uefi
vixl-1.12
vmid16
x86-rdtsc
xopen-source
This qemu repo is mostly a place to put together pull requests for upstream
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riscv
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Author
2020-11-09
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
2020-11-09
target/riscv: Set the virtualised MMU mode when doing hyp accesses
Alistair Francis
2020-11-09
target/riscv: Add a virtualised MMU Mode
Alistair Francis
2020-11-03
target/riscv/csr.c : add space before the open parenthesis '('
Xinhao Zhang
2020-11-03
target/riscv: Add V extension state description
Yifei Jiang
2020-11-03
target/riscv: Add H extension state description
Yifei Jiang
2020-11-03
target/riscv: Add PMP state description
Yifei Jiang
2020-11-03
target/riscv: Add basic vmstate description of CPU
Yifei Jiang
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
2020-10-22
target/riscv: raise exception to HS-mode at get_physical_address
Yifei Jiang
2020-10-22
target/riscv: Fix implementation of HLVX.WU instruction
Georg Kotheimer
2020-10-22
target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt
Georg Kotheimer
2020-10-22
target/riscv: Fix update of hstatus.SPVP
Georg Kotheimer
2020-10-22
riscv: Convert interrupt logs to use qemu_log_mask()
Alistair Francis
2020-10-05
icount: rename functions to be consistent with the module name
Claudio Fontana
2020-10-05
cpu-timers, icount: new modules
Claudio Fontana
2020-09-23
qemu/atomic.h: rename atomic_ to qatomic_
Stefan Hajnoczi
2020-09-18
qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
Eduardo Habkost
2020-09-18
target/riscv: Set instance_align on RISCVCPU TypeInfo
Richard Henderson
2020-09-13
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...
Peter Maydell
2020-09-11
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...
Peter Maydell
2020-09-09
hw/riscv: clint: Avoid using hard-coded timebase frequency
Bin Meng
2020-09-09
target/riscv: cpu: Set reset vector based on the configured property value
Bin Meng
2020-09-09
target/riscv: cpu: Add a new 'resetvec' property
Bin Meng
2020-09-09
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
Yifei Jiang
2020-09-09
trace-events: Fix attribution of trace points to source
Markus Armbruster
2020-09-09
Use OBJECT_DECLARE_TYPE where possible
Eduardo Habkost
2020-09-09
Use DECLARE_*CHECKER* macros
Eduardo Habkost
2020-09-09
Move QOM typedefs and add missing includes
Eduardo Habkost
2020-08-28
softfloat: Implement the full set of comparisons for float16
Kito Cheng
2020-08-25
target/riscv: Support the Virtual Instruction fault
Alistair Francis
2020-08-25
target/riscv: Return the exception from invalid CSR accesses
Alistair Francis
2020-08-25
target/riscv: Support the v0.6 Hypervisor extension CRSs
Alistair Francis
2020-08-25
target/riscv: Only support little endian guests
Alistair Francis
2020-08-25
target/riscv: Only support a single VSXL length
Alistair Francis
2020-08-25
target/riscv: Update the CSRs to the v0.6 Hyp extension
Alistair Francis
2020-08-25
target/riscv: Update the Hypervisor trap return/entry
Alistair Francis
2020-08-25
target/riscv: Fix the interrupt cause code
Alistair Francis
2020-08-25
target/riscv: Convert MSTATUS MTL to GVA
Alistair Francis
2020-08-25
target/riscv: Don't allow guest to write to htinst
Alistair Francis
2020-08-25
target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
Alistair Francis
2020-08-25
target/riscv: Allow generating hlv/hlvx/hsv instructions
Alistair Francis
2020-08-25
target/riscv: Allow setting a two-stage lookup in the virt status
Alistair Francis
2020-08-21
target/riscv: Change the TLB page size depends on PMP entries.
Zong Li
2020-08-21
target/riscv: Fix the translation of physical address
Zong Li
2020-08-21
riscv: Fix bug in setting pmpcfg CSR for RISCV64
Hou Weiying
2020-08-21
target/riscv: check before allocating TCG temps
LIU Zhiwei
2020-08-21
target/riscv: Clean up fmv.w.x
LIU Zhiwei
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