aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Implement second stage MMUAlistair Francis
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis
2020-01-16target/riscv: Fix tb->flags FS statusShihPo Hung
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis
2019-06-25target/riscv: Remove user version informationAlistair Francis
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
2019-06-10cpu: Remove CPU_COMMONRichard Henderson
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-07 15:02:08 +0000