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-rw-r--r--include/fpu/softfloat.h7
-rw-r--r--include/hw/ppc/pnv_lpc.h8
-rw-r--r--include/hw/ppc/pnv_occ.h7
-rw-r--r--include/hw/ppc/pnv_psi.h7
-rw-r--r--include/hw/ppc/ppc.h10
-rw-r--r--include/hw/ppc/spapr.h1
-rw-r--r--include/qemu/int128.h21
7 files changed, 39 insertions, 22 deletions
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index d34b2c44d2..3dcf20e3a2 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -95,6 +95,7 @@ typedef enum {
#include "fpu/softfloat-types.h"
#include "fpu/softfloat-helpers.h"
+#include "qemu/int128.h"
/*----------------------------------------------------------------------------
| Routine to raise any or all of the software IEC/IEEE floating-point
@@ -182,7 +183,9 @@ floatx80 int64_to_floatx80(int64_t, float_status *status);
float128 int32_to_float128(int32_t, float_status *status);
float128 int64_to_float128(int64_t, float_status *status);
+float128 int128_to_float128(Int128, float_status *status);
float128 uint64_to_float128(uint64_t, float_status *status);
+float128 uint128_to_float128(Int128, float_status *status);
/*----------------------------------------------------------------------------
| Software half-precision conversion routines.
@@ -1201,9 +1204,13 @@ floatx80 floatx80_default_nan(float_status *status);
int32_t float128_to_int32(float128, float_status *status);
int32_t float128_to_int32_round_to_zero(float128, float_status *status);
int64_t float128_to_int64(float128, float_status *status);
+Int128 float128_to_int128(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
+Int128 float128_to_int128_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
+Int128 float128_to_uint128(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
+Int128 float128_to_uint128_round_to_zero(float128, float_status *status);
uint32_t float128_to_uint32(float128, float_status *status);
uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index e893e763dd..8a8d1a3d42 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV LPC controller
*
- * Copyright (c) 2016, IBM Corporation.
+ * Copyright (c) 2016-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_LPC "pnv-lpc"
@@ -84,15 +83,12 @@ struct PnvLpcController {
MemoryRegion xscom_regs;
/* PSI to generate interrupts */
- PnvPsi *psi;
+ qemu_irq psi_irq;
};
-
struct PnvLpcClass {
DeviceClass parent_class;
- int psi_irq;
-
DeviceRealize parent_realize;
};
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index f982ba0024..90a81dae2b 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Emulation of a few OCC related registers
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_OCC_H
#define PPC_PNV_OCC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_OCC "pnv-occ"
@@ -44,19 +43,17 @@ struct PnvOCC {
/* OCC Misc interrupt */
uint64_t occmisc;
- PnvPsi *psi;
+ qemu_irq psi_irq;
MemoryRegion xscom_regs;
MemoryRegion sram_regs;
};
-
struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
const MemoryRegionOps *xscom_ops;
- int psi_irq;
};
#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index eb841b34a1..8253469b8f 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -79,13 +79,10 @@ struct PnvPsiClass {
uint64_t bar_mask;
const char *compat;
int compat_size;
-
- void (*irq_set)(PnvPsi *psi, int, bool state);
};
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
- PSIHB_IRQ_PSI, /* internal use only */
PSIHB_IRQ_FSP, /* internal use only */
PSIHB_IRQ_OCC,
PSIHB_IRQ_FSI,
@@ -96,8 +93,6 @@ typedef enum PnvPsiIrq {
#define PSI_NUM_INTERRUPTS 6
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
-
/* P9 PSI Interrupts */
#define PSIHB9_IRQ_PSI 0
#define PSIHB9_IRQ_OCC 1
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 364f165b4b..02af03ada2 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -99,11 +99,11 @@ enum {
ARCH_MAC99_U3,
};
-#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
-#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
-#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
+#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
+#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
+#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
+#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
+#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index f5c33dcc86..14b01c3f59 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -745,6 +745,7 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
#define RTAS_DDW_PGSIZE_128M 0x20
#define RTAS_DDW_PGSIZE_256M 0x40
#define RTAS_DDW_PGSIZE_16G 0x80
+#define RTAS_DDW_PGSIZE_2M 0x100
/* RTAS tokens */
#define RTAS_TOKEN_BASE 0x2000
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 37e07fd6dd..ef71f56e3f 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -83,6 +83,11 @@ static inline Int128 int128_rshift(Int128 a, int n)
return a >> n;
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+ return (__uint128_t)a >> n;
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
return a << n;
@@ -299,6 +304,20 @@ static inline Int128 int128_rshift(Int128 a, int n)
}
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+ uint64_t h = a.hi;
+ if (!n) {
+ return a;
+ }
+ h = h >> (n & 63);
+ if (n >= 64) {
+ return int128_make64(h);
+ } else {
+ return int128_make128((a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h);
+ }
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
uint64_t l = a.lo << (n & 63);
@@ -412,5 +431,7 @@ static inline void bswap128s(Int128 *s)
}
#define UINT128_MAX int128_make128(~0LL, ~0LL)
+#define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX)
+#define INT128_MIN int128_make128(0, INT64_MIN)
#endif /* INT128_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 03:14:09 +0000