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authorRichard Henderson <rth@twiddle.net>2013-04-29 08:08:22 -0700
committerAurelien Jarno <aurelien@aurel32.net>2013-05-03 11:53:29 +0200
commit8ddaeb1be66246225fe5aeeec33e4e7b82762694 (patch)
tree202e3268915699354adad3d0c0b264a1e4fe53ee /tcg
parent29851ee7c8bd3fb8542e21cd0270c73132590350 (diff)
tcg-arm: Fix 64-bit tlb load for pre-v6
Found by inspection, since the effect of the bug was simply to send all memory ops through the slow path. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/arm/tcg-target.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 7216f7a63d..12edad4875 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1190,7 +1190,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
tcg_out_memop_12(s, COND_AL, INSN_LDR_IMM, TCG_REG_R0,
TCG_REG_R2, tlb_offset, 1, 1);
if (TARGET_LONG_BITS == 64) {
- tcg_out_memop_12(s, COND_AL, INSN_LDR_IMM, TCG_REG_R0,
+ tcg_out_memop_12(s, COND_AL, INSN_LDR_IMM, TCG_REG_R1,
TCG_REG_R2, 4, 1, 0);
}
}