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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-05-19 19:18:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-19 19:18:41 +0100 |
| commit | 956ae3e9265fd36cb1c487cb3c868e906bd55897 (patch) | |
| tree | 62e00e715b0217099392f6de49b7b8a0b913f92f /target/mips/msa_helper.c | |
| parent | f2465433b43fb87766d79f42191607dac4aed5b4 (diff) | |
| parent | 150c7a91ce7862bcaf7422f6038dcf0ba4a7eee3 (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20200519' into staging
Misc cleanups
# gpg: Signature made Tue 19 May 2020 16:51:38 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-fpu-20200519:
softfloat: Return bool from all classification predicates
softfloat: Inline floatx80 compare specializations
softfloat: Inline float128 compare specializations
softfloat: Inline float64 compare specializations
softfloat: Inline float32 compare specializations
softfloat: Name compare relation enum
softfloat: Name rounding mode enum
softfloat: Change tininess_before_rounding to bool
softfloat: Replace flag with bool
softfloat: Use post test for floatN_mul
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/msa_helper.c')
| -rw-r--r-- | target/mips/msa_helper.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 4065cfe4f7..3c7012c0b8 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -5508,7 +5508,7 @@ static inline int get_enabled_exceptions(const CPUMIPSState *env, int c) return c & enable; } -static inline float16 float16_from_float32(int32_t a, flag ieee, +static inline float16 float16_from_float32(int32_t a, bool ieee, float_status *status) { float16 f_val; @@ -5527,7 +5527,7 @@ static inline float32 float32_from_float64(int64_t a, float_status *status) return a < 0 ? (f_val | (1 << 31)) : f_val; } -static inline float32 float32_from_float16(int16_t a, flag ieee, +static inline float32 float32_from_float16(int16_t a, bool ieee, float_status *status) { float32 f_val; @@ -6564,7 +6564,7 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, * IEEE and "ARM" format. The latter gains extra exponent * range by omitting the NaN/Inf encodings. */ - flag ieee = 1; + bool ieee = true; MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16); MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16); @@ -7178,7 +7178,7 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, * IEEE and "ARM" format. The latter gains extra exponent * range by omitting the NaN/Inf encodings. */ - flag ieee = 1; + bool ieee = true; MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32); } @@ -7214,7 +7214,7 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, * IEEE and "ARM" format. The latter gains extra exponent * range by omitting the NaN/Inf encodings. */ - flag ieee = 1; + bool ieee = true; MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32); } |