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authorRichard Henderson <rth@twiddle.net>2015-10-01 12:32:52 +1000
committerRichard Henderson <rth@twiddle.net>2015-10-07 20:03:16 +1100
commit133b84c819166a6da1425a007cf44d7a96d507a4 (patch)
tree5418c048f1c669eee80221251d9466fb48575cc0 /target-sparc
parent95df61e6238c79c2dc14f2bffa76abb2bd3acba7 (diff)
target-tilegx: Handle nofault prefetch instructions
These are mapped onto some of the normal load instructions, when the destination is the zero register. Other load insns do fault even when targeting the zero register. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-sparc')
0 files changed, 0 insertions, 0 deletions