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authorPaul Brook <paul@codesourcery.com>2010-03-17 02:14:28 +0000
committerPaul Brook <paul@codesourcery.com>2010-03-17 02:44:41 +0000
commitd4c430a80f000d722bb70287af4d4c184a8d7006 (patch)
tree9b9d059b2158f25fc0629fddcef192e3d791b187 /target-sh4
parent409dbce54b57b85bd229174da86d77ca08508508 (diff)
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'target-sh4')
-rw-r--r--target-sh4/helper.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 486be5d511..6c3f896a2d 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -470,7 +470,8 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
address &= TARGET_PAGE_MASK;
physical &= TARGET_PAGE_MASK;
- return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
+ tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+ return 0;
}
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)